CN114721983A - DDR4 accelerates readwrite device - Google Patents
DDR4 accelerates readwrite device Download PDFInfo
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- CN114721983A CN114721983A CN202210382504.9A CN202210382504A CN114721983A CN 114721983 A CN114721983 A CN 114721983A CN 202210382504 A CN202210382504 A CN 202210382504A CN 114721983 A CN114721983 A CN 114721983A
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 18
- 230000005540 biological transmission Effects 0.000 claims abstract description 10
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- 238000000034 method Methods 0.000 abstract description 6
- 230000001133 acceleration Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000003139 buffering effect Effects 0.000 description 3
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0613—Improving I/O performance in relation to throughput
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
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Abstract
The invention particularly relates to a DDR4 acceleration read-write device. The DDR4 accelerated reading and writing device comprises a data cache module, a priority module, a data format conversion module, an arbitration module, a DDR data module and an upper computer; the data is transmitted in a ping-pong transmission mode, the priority module determines the read-write priority in a mode of determining the priority by address gating and increasing individual data bit width, and after the data format conversion module converts the data into the data bit width supported by the DDR4, the DDR4 module is interacted to read and write the data by the arbitration module in combination with the priority and the read-write operation mode. The DDR4 acceleration read-write device can self-determine a transceiving time sequence while ensuring high-capacity data throughput storage processing, and transmits information to an upper computer according to a designated transceiving speed; in the process of receiving and sending, the whole process is a scrambling transmission mode, so that the stability and the safety of information transmission are ensured.
Description
Technical Field
The invention relates to the technical field of electronics and communication, in particular to a DDR4 accelerated read-write device.
Background
The most significant advantage of DDR4 memory is its ability to increase frequency and bandwidth and support the storage and retrieval of large amounts of data. On the premise that the throughput of data in the wireless communication field is increasing, increasing the throughput and the processing manner of large data volume are becoming increasingly demanded. And the data requests with various priority sequences are realized by using FPGA (field programmable gate array) parallel processing, so that the reliability is higher.
Based on the above situation, the invention provides a DDR4 accelerated read-write device.
Disclosure of Invention
In order to make up for the defects of the prior art, the invention provides a simple and efficient DDR4 acceleration read-write device.
The invention is realized by the following technical scheme:
a DDR4 accelerates read-write equipment, its characterized in that: the device comprises a data cache module, a priority module, a data format conversion module, an arbitration module, a DDR data module and an upper computer;
the data is transmitted in a ping-pong transmission mode, the priority module determines the read-write priority in a mode of determining the priority by address gating and increasing individual data bit width, and after the data format conversion module converts the data into the data bit width supported by the DDR4, the DDR4 module is interacted to read and write the data by the arbitration module in combination with the priority and the read-write operation mode.
The data buffer module comprises a written data buffer module and a read data buffer module, is respectively positioned at the input end and the output end of the device, is respectively connected with the priority module, and performs high-capacity and uninterrupted data input and data read in a ping-pong operation mode;
after receiving a writing and reading instruction with priority, the priority module adds a mark signal to the first two bits of the address through comparison and judgment so as to judge the priority and the read-write mode;
if the data writing format does not meet the data bit requirement of DDR4 operation, the data format conversion module converts the data writing format into a data bit width corresponding to a DDR4 format;
the arbitration module is connected, performs read-write operation by combining with the instruction of the DDR user layer according to the priority level, and is connected with an upper computer; the physical connection is actually connected through a PHY (physical) layer of the DDR4, and after data processing is completed, if the connection is a read instruction, the arbitration module performs uninterrupted data output through ping-pong operation.
The data buffer module comprises two Multiplexers (MUXs), two First-in First-out (FIFO) queues and a data stream operation processing unit;
one multiplexer MUX is used as input selection, and the other multiplexer MUX is used as output selection; the two FIFOs are used as data buffer units, the data stream operation processing unit is responsible for data splicing, and the upper limit of the data stream operation processing unit is the data bit width corresponding to the DDR, 64 or 128 bits.
The priority setting module comprises a DDR initial address setting unit, a read-write request receiving unit and a priority sorting unit;
and (3) leading out a DDR4_ app _ addr pin of a DDR4 user layer to determine an initial value, performing address operation by adding the length of a burst address each time, and receiving a read-write priority request corresponding to the address, so as to generate an operand obtained by adding the address number and the priority judgment number, and entering the operand into an arbitration module.
The data format conversion module comprises a data inflow interface and a mask interface interacting with the DDR user layer, detects the data bit width by adopting a cycle statement, and fills the data bit width to the specified data bit width, thereby ensuring the orderly operation of the DDR read-write operation.
The data format conversion module is interacted with an app _ mask signal of a DDR4 user layer interface, an input signal is supplemented to 64bits/128bits, namely the data format adapted to the DDR4 module, and therefore stability and data alignment of the DDR4 during reading and writing operations are guaranteed.
The read-write arbitration module comprises a state machine judgment unit of read-write mode priority, a user layer interface for controlling DDR and a DDR read-write operation unit;
the state machine judging unit priority judging criteria of the read-write mode priority are divided into 2 types: the writing mode is divided into 00 and 01 from low to high, and the reading mode is divided into 10 and 11 from low to high;
if the read and write conditions with the same priority occur, preferentially executing a write instruction, executing a read instruction with the same priority after an overflow instruction or a write completion instruction exists, if the same instruction with different priorities is found, executing an instruction with high priority, and if the same instruction with the same priority is found, sequentially executing.
The DDR data module and the read-write arbitration module are used as an input-output inout interface for data receiving and transmitting and are connected with an upper computer.
The invention has the beneficial effects that: the DDR4 acceleration read-write device can self-determine a transceiving time sequence while ensuring high-capacity data throughput storage processing, and transmits information to an upper computer according to a designated transceiving speed; in the process of receiving and sending, the whole process is a scrambling code transmission mode, so that the stability and the safety of information transmission are ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of data buffering of a DDR4 accelerated read/write device according to the invention.
FIG. 2 is a schematic diagram illustrating the priority setting of the DDR4 accelerated read/write device according to the invention.
FIG. 3 is a diagram illustrating data format conversion of a DDR4 accelerated read/write device according to the invention.
FIG. 4 is a schematic diagram illustrating a processing flow of the read-write arbitration module of the DDR4 accelerated read-write device of the invention.
FIG. 5 is a diagram of a DDR4 accelerated read/write device according to the invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the embodiment of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The DDR4 accelerated reading and writing device comprises a data cache module, a priority module, a data format conversion module, an arbitration module, a DDR data module and an upper computer;
the data is transmitted in a ping-pong transmission mode, the priority module determines the read-write priority in a mode of determining the priority by address gating and increasing individual data bit width, and after the data format conversion module converts the data into the data bit width supported by the DDR4, the DDR4 module is interacted to read and write the data by the arbitration module in combination with the priority and the read-write operation mode.
The data buffer module comprises a written data buffer module and a read data buffer module, is respectively positioned at the input end and the output end of the device, is respectively connected with the priority module, and performs high-capacity and uninterrupted data input and data read in a ping-pong operation mode;
after receiving a writing and reading instruction with priority, the priority module adds a mark signal to the first two bits of the address through comparison and judgment so as to judge the priority and the read-write mode;
if the data writing format does not meet the data bit requirement of DDR4 operation, the data format conversion module converts the data writing format into a data bit width corresponding to a DDR4 format;
the arbitration module is connected, performs read-write operation by combining with the instruction of the DDR user layer according to the priority level, and is connected with an upper computer; the physical connection is actually connected through a PHY (physical) layer of the DDR4, and after data processing is completed, if the connection is a read instruction, the arbitration module performs uninterrupted data output through ping-pong operation.
The data buffer module comprises two Multiplexers (MUXs), two First-in First-out (FIFO) queues and a data stream operation processing unit;
one multiplexer MUX is used as input selection, and the other multiplexer MUX is used as output selection; the two FIFOs are used as data buffer units, the data stream operation processing unit is responsible for data splicing, and the upper limit of the data stream operation processing unit is the data bit width corresponding to the DDR, 64bits or 128 bits.
The priority setting module comprises a DDR initial address setting unit, a read-write request receiving unit and a priority sorting unit;
because the burst mode corresponding to the DDR4 is fixed (burst is 4bits), only the DDR4_ app _ addr pin of the DDR4 user layer needs to be led out to determine an initial value, on this basis, the length of the burst address is added each time to perform address operation, and meanwhile, the read-write priority request corresponding to the address is received, so that an operand obtained by adding the address number and the priority judgment number is generated and enters the arbitration module.
The data format conversion module comprises a data inflow interface and a mask interface interacting with a DDR user layer, and because the inflow upper limit is set to be 64/128bit in the data buffering stage and an instruction of DDR _ app _ mask is used for complementing data bit width in the user layer interface of the DDR, a circulation statement is adopted to detect the data bit width and complement the data bit width to a specified data bit width, so that the orderly progress of DDR read-write operation is ensured.
The data format conversion module is interacted with an app _ mask signal of a DDR4 user layer interface, an input signal is supplemented to 64bits/128bits, namely the data format adapted to the DDR4 module, and therefore stability and data alignment of the DDR4 during reading and writing operations are guaranteed.
The read-write arbitration module comprises a state machine judgment unit of read-write mode priority, a user layer interface for controlling DDR and a DDR read-write operation unit;
the state machine judging unit priority judging criteria of the read-write mode priority are divided into 2 types: the writing mode is divided into 00 and 01 from low to high, and the reading mode is divided into 10 and 11 from low to high;
if the read and write conditions with the same priority occur, preferentially executing a write instruction, executing a read instruction with the same priority after an overflow instruction or a write completion instruction exists, if the same instruction with different priorities is found, executing an instruction with high priority, and if the same instruction with the same priority is found, sequentially executing.
The DDR data module and the read-write arbitration module are used as input and output inout interfaces for data receiving and transmitting and are connected with an upper computer.
The upper computer is a general computer and supports a gigabit Ethernet communication mode. The resource released or written by DDR4 can be directly controlled, stored, and read by being connected to DDR4 through physical layer.
Compared with the prior art, the DDR4 acceleration read-write device has the following characteristics:
first, DDR data input is based on burst and the self discrete read-write speed, and the actual use efficiency can be greatly reduced; the data caching module adopts a ping-pong operation mode to ensure high-speed inflow of data, ensure seamless buffering and processing of the data and save the space of a buffer area at the same time.
And secondly, judging the priority of the initial address and the data read-write instruction, so that the data request with the priority and the burst mode (burst) are corresponding.
Thirdly, the receiving and sending time sequence can be set by oneself while ensuring the handling and storage processing of the large-capacity data, and the information is transmitted to the upper computer according to the designated receiving and sending speed.
Fourthly, in the process of receiving and sending, the whole process is a scrambling code transmission mode, and therefore the stability and the safety of information transmission are guaranteed.
The above-described embodiment is only one specific embodiment of the present invention, and general changes and substitutions by those skilled in the art within the technical scope of the present invention are included in the protection scope of the present invention.
Claims (8)
1. A DDR4 accelerates read-write equipment, its characterized in that: the device comprises a data cache module, a priority module, a data format conversion module, an arbitration module, a DDR data module and an upper computer;
the data is transmitted in a ping-pong transmission mode, the priority module determines the read-write priority in a mode of determining the priority by address gating and increasing individual data bit width, and after the data format conversion module converts the data into the data bit width supported by the DDR4, the DDR4 module is interacted to read and write the data by the arbitration module in combination with the priority and the read-write operation mode.
2. The DDR4 accelerated read/write device of claim 1, wherein: the data buffer module comprises a written data buffer module and a read data buffer module, is respectively positioned at the input end and the output end of the device, is respectively connected with the priority module, and performs high-capacity and uninterrupted data input and data read in a ping-pong operation mode;
after receiving a writing and reading instruction with priority, the priority module adds a mark signal to the first two bits of the address through comparison and judgment so as to judge the priority and the read-write mode;
if the data writing format does not meet the data bit requirement of DDR4 operation, the data format conversion module converts the data writing format into a data bit width corresponding to a DDR4 format;
the arbitration module is connected, performs read-write operation by combining with the instruction of the DDR user layer according to the priority level, and is connected with an upper computer; the physical connection is actually connected through a PHY layer of the DDR4, and after data processing is finished, if the physical connection is a read instruction, the arbitration module performs uninterrupted data output through ping-pong operation.
3. The DDR4 accelerated read/write device of claim 2, wherein: the data buffer module comprises two Multiplexers (MUX), two FIFOs and a data stream operation processing unit;
one multiplexer MUX is used as input selection, and the other multiplexer MUX is used as output selection; the two FIFOs are used as data buffer units, the data stream operation processing unit is responsible for data splicing, and the upper limit of the data stream operation processing unit is the data bit width corresponding to the DDR, 64bits or 128 bits.
4. The DDR4 accelerated read/write device of claim 2, wherein: the priority setting module comprises a DDR initial address setting unit, a read-write request receiving unit and a priority sorting unit;
and (3) leading out a DDR4_ app _ addr pin of a DDR4 user layer to determine an initial value, performing address operation by adding the length of a burst address each time, and receiving a read-write priority request corresponding to the address, so as to generate an operand obtained by adding the address number and the priority judgment number, and entering the operand into an arbitration module.
5. The DDR4 accelerated read/write device of claim 2, wherein: the data format conversion module comprises a data inflow interface and a mask interface interacting with the DDR user layer, detects the data bit width by adopting a cycle statement, and fills the data bit width to the specified data bit width, thereby ensuring the orderly operation of the DDR read-write operation.
6. The DDR4 accelerated read-write device of claim 5, wherein: the data format conversion module is used for complementing the input signal to 64bits/128bits through interaction with an app _ mask signal of a DDR4 user layer interface, namely, the data format adapted to the DDR4 module, so that the stability and data alignment of the DDR4 during read-write operation are ensured.
7. The DDR4 accelerated read/write device of claim 2, wherein: the read-write arbitration module comprises a state machine judgment unit of read-write mode priority, a user layer interface for controlling DDR and a DDR read-write operation unit;
the state machine judging unit priority judging criteria of the read-write mode priority are divided into 2 types: the writing mode is divided into 00 and 01 from low to high, and the reading mode is divided into 10 and 11 from low to high;
if the read and write conditions with the same priority occur, preferentially executing a write instruction, executing a read instruction with the same priority after an overflow instruction or a write completion instruction exists, if the same instruction with different priorities is found, executing an instruction with high priority, and if the same instruction with the same priority is found, sequentially executing.
8. The DDR4 accelerated read/write device of claim 2, wherein: the DDR data module and the read-write arbitration module are used as input and output inout interfaces for data receiving and transmitting and are connected with an upper computer.
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| CN115328822A (en) * | 2022-08-19 | 2022-11-11 | 扬州宇安电子科技有限公司 | DDR 3-based read-write control dynamic scheduling method and storage medium thereof |
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