CN110888765A - Device and method for counting number of data 0 and 1 flip bits - Google Patents
Device and method for counting number of data 0 and 1 flip bits Download PDFInfo
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The invention discloses a device and a method for counting the number of data 0 and 1 turning bits, wherein the device comprises a configuration module, a command FIFO, a response FIFO, a data flow control module, an adder, a master interface 1 and a master interface 2, the data flow control module comprises a command processing module and a data processing module, the configuration module is connected with a control bus and used for receiving configuration information and a starting signal written by an external CPU through the control bus, and the command FIFO is connected between the configuration module and the command processing module and used for receiving and storing the configuration information written by the configuration module and writing the configuration information into the command processing module. The invention adopts two master interfaces to fetch data simultaneously, does not need to additionally develop space to store intermediate data, and simplifies the design. Meanwhile, the device supports a plurality of commands, supports a large number of operations, greatly improves the efficiency of the whole system and saves the test time.
Description
Technical Field
The invention relates to a device and a method for counting the number of turning bits of data 0 and 1, belonging to the technical field of storage component testing.
Background
In testing the characteristics of memory devices (e.g., NAND FLASH), statistics are needed to flip the number of bits before writing data to the device and after reading data from the device to 0/1. The statistical data plays an important role in subsequent device characteristic analysis and research, and a large amount of test statistics are required in the whole characteristic test process. According to the traditional method, software is adopted for statistical processing, namely, the lower computer transmits all data to the upper computer, and the upper computer software compares the data, so that a large amount of time is used for data transmission, the efficiency of a test system is low, and the test time is prolonged.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a device and a method for counting the number of turning bits of data 0 and 1, so that the data comparison speed is improved, and the time is saved.
In order to solve the technical problem, the technical scheme adopted by the invention is as follows: a device for counting the number of bits of data 0 and 1, comprising a configuration module, a command FIFO, a response FIFO, a data flow control module, an adder, a master interface 1 and a master interface 2, wherein the data flow control module comprises a command processing module and a data processing module, the configuration module is connected with a control bus and used for receiving configuration information and a starting signal written by an external CPU through the control bus, the command FIFO is connected between the configuration module and the command processing module and used for receiving and storing the configuration information written by the configuration module and writing the configuration information into the command processing module, the command processing module calculates the storage address and the data length of original data and read data according to the configuration information, then sends the calculated original data address and data length signals to the master interface 1 and sends the calculated read data address and data length signals to the master interface 2, the master interface 1 and the master interface 2 respectively capture corresponding data from a memory through a data bus according to a received data address and a received data length, the captured data are returned to the data processing module, the data processing module compares the data returned by the master interface 1 and the master interface 2 bit by bit, the number of bit 0 overturned to bit 1 and the number of bit 1 overturned to bit 0 are counted, the adder accumulates the number of bit 0 overturned to bit 1 and the number of bit 1 overturned to bit 0, and an accumulation result is written into a response FIFO; the configuration information includes an original data address, a read data address, and a data length.
Further, the command FIFO stores configuration information for the plurality of commands.
Further, the master interface 1 and the master interface 2 capture data in parallel.
Further, the external CPU writes configuration information into the configuration module when a start signal of the configuration module is invalid, sets the start signal of the configuration module to be valid when full signals of the command FIFO and the response FIFO are both invalid, and sets the start signal to be invalid after the configuration information of the command is written into the command FIFO.
Further, the data processing module outputs an effective ending signal after finishing the number of the turning bits of all the data of the command, at this time, the accumulation result of the adder is the number of the turning bits of all the data of the command, and the adder writes the accumulation result into the response FIFO and clears 0.
The invention also discloses a method for counting the number of the data 0 and 1 upset bits, which comprises the following steps:
s01), the external CPU writes the configuration information of the command and the starting signal into the configuration module, and the configuration module writes the configuration information into the command FIFO, wherein the configuration information refers to the original data address of the command, the read data address and the data length;
s02), the command processing module in the data flow control module receives the configuration information transmitted by the command FIFO and obtains the information required by the current operation: the method comprises the steps that an original data address, a read data address and a read data length are obtained, because configuration information of a command needs to be split into a plurality of addresses and data lengths to be sent to a master interface, a command processing module splits the configuration information into a plurality of pieces according to a bus protocol and calculates the initial address and the data length of each piece, then the calculated original data address and the calculated data length are sent to the master interface 1, the calculated read data address and the calculated data length are sent to the master interface 2, and the data lengths sent to the two master interfaces are kept consistent;
s03), the master interface 1 receives the data address and the data length sent by the command processing module, starts data capture, and returns data to the data flow control module;
s04), the master interface 2 receives the data address and the data length sent by the command processing module, starts data capture and returns data to the data flow control module;
s05), the data processing module in the data flow control module compares and calculates the number of the bit 0 inverted into the bit and the number of the bit 1 inverted into the bit 0 bit by bit from the head address of the returned data, and outputs the result to the adder until the comparison of all the data of the current comparison command is completed, and then outputs an effective ending signal;
s06), when step S05 is executed, the adder adds the output result of the data flow control module and the last accumulated result in real time, and outputs the current accumulated result, and when the data flow control module outputs an effective end signal, the accumulated result of the current adder is the final result;
s07), after the response FIFO receives the effective ending signal, the accumulation result of the current adder is stored;
s08), when the adder detects the effective end signal, the accumulated result is cleared to 0, and the next calculation is waited to start.
Further, the action of the external CPU writing the configuration information to the configuration module is executed in a loop until all the configuration information of the command is written to the configuration module.
Further, step S03 is performed in parallel with step S04.
Further, whether the configured starting signal is valid or not is inquired through the control bus, and if the configured starting signal is invalid, the external CPU writes the configuration information and the starting signal into the configuration module; the configuration module starting signal is set to be valid when full signals of the command FIFO and the response FIFO are invalid, and the starting signal is set to be invalid after the compared configuration information is written into the command FIFO.
Further, the external CPU checks the state of the response FIFO through the configuration module, and if the response FIFO is not empty, the response FIFO indicates that a valid result is currently stored and can be read.
The invention has the beneficial effects that: the device and the method can improve the data comparison speed and improve the system efficiency; this device adopts two master interfaces to get the number simultaneously, and a master interface is not needn't additionally develop the space and save intermediate data, the simplified design. Meanwhile, the device supports a plurality of commands, supports a large number of operations, greatly improves the efficiency of the whole system and saves the test time.
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FIG. 1 is a block diagram of the apparatus of the present invention;
in the figure: start represents the start signal, cmd _ info represents the configuration information, cmd _ FIFO represents the command FIFO, cmplete _ FIFO represents the response FIFO, full represents the full signal, empty represents the empty signal, and the end push represents the active end signal.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments.
Example 1
The embodiment discloses a device for counting bit numbers of data 0 and 1, which comprises a configuration module, a command FIFO, a response FIFO, a data flow control module, an adder, a master interface 1 and a master interface 2, wherein the data flow control module comprises a command processing module and a data processing module, as shown in fig. 1.
The configuration module is connected with the control bus and used for receiving configuration information and a starting signal written by an external CPU through the control bus, the command FIFO is connected between the configuration module and the command processing module and used for receiving and storing the configuration information written by the configuration module and writing the configuration information into the command processing module, the command processing module calculates the storage address and the data length of original data and read data according to the configuration information, then sends the calculated original data address and data length signals to the master interface 1 and sends the calculated read data address and data length signals to the master interface 2, the master interface 1 and the master interface 2 respectively and actively grab corresponding data from the memory through the data bus according to the received data address and data length and return the grabbed data to the data processing module, and the data processing module compares the data returned by the master interface 1 and the master interface 2 bit by bit, counting the number of bit 0 turned into bit 1 and the number of bit 1 turned into bit 0, accumulating the number of bit 0 turned into bit 1 and the number of bit 1 turned into bit 0 by the adder, and writing the accumulated result into a response FIFO; the configuration information includes an original data address, a read data address, and a data length.
In this embodiment, the command FIFO can store configuration information of a plurality of commands, support a plurality of commands, and support a large number of operations.
The master interface 1 and the master interface 2 capture data in parallel without interference.
In this embodiment, after receiving the start signal, the configuration module determines whether both the current command FIFO and the response FIFO are full (full signal), and if both are not full, the configuration module asserts the start signal, writes the configuration information into the command FIFO, and sets the start signal in the configuration module to invalid. When the CPU detects that the starting signal is invalid, the CPU indicates that the last command configuration is successful, and writes configuration information into the command configuration, otherwise, the CPU waits until the current command is correctly configured.
In this embodiment, the data processing module outputs an effective end signal after completing the number of flip bits of all data of the command, at this time, the accumulation result of the adder is the number of flip bits of all data of the command, and the adder writes the accumulation result into the response FIFO and clears 0.
Example 2
The embodiment discloses a method for counting bit numbers of data 0 and 1, which comprises the following steps:
1. the microcontroller such as an external CPU inquires whether the starting signal of the configuration module is effective or not through a control bus; and if the data is invalid, writing the original data address, the data length and the read data address into the configuration module, finally writing a starting signal into the configuration module, and starting one-time comparison operation. Step 1 may be performed in a loop until all commands are written to the configuration module.
2. And when the configuration module detects that the full signals of the command FIFO and the response FIFO are invalid, the high-valid starting signal writes the current configuration information into the command FIFO. While the enable signal is deasserted.
3. The command processing module in the data flow control module receives the configuration information transmitted by the command FIFO and obtains the information required by the current operation: the method comprises the steps that original data addresses, data lengths and read data addresses are obtained, configuration information of a command needs to be split into a plurality of addresses and data lengths to be sent to a master interface, a command processing module splits the configuration information into a plurality of pieces according to a bus protocol and calculates the initial address and the data length of each piece, then the calculated original data addresses and the calculated data lengths are sent to the master interface 1, the calculated read data addresses and the calculated data lengths are sent to the master interface 2, and the data lengths sent to the two master interfaces are kept consistent.
4. The master interface 1 receives the data address and the data length sent by the data flow control module, starts data capture, and returns data to the data flow control module.
5. Meanwhile, the master interface 2 receives the data address and the data length sent by the data flow control module, starts data capture, and returns data to the data flow control module. The master interface 1 and the master interface 2 are completely parallel and do not interfere with each other.
6. If the master interface 1 and the master interface 2 both have data to return, the data processing module in the data flow control module simultaneously takes out one data from the master interface 1 and the master interface 2, compares the data, calculates the number of the bit 0 which is turned into the bit 1 and the number of the bit 1 which is turned into the bit 0, and outputs the result. And repeating the step 6 until the data processing module finishes the comparison of the data with the specified length in the current configuration information. Outputting a valid end signal.
7. And 6, when the operation is carried out, the adder adds the output result of the data flow control module and the last accumulated result in real time and outputs the current accumulated result. When the data flow control module outputs an effective end signal, the accumulation result of the current adder is the final result.
8. And after receiving the effective end signal, the response FIFO stores the accumulation result of the current adder.
9. And after the adder detects the end signal, clearing 0 from the accumulation result. Waiting for the next calculation to start. And repeating the comparison operation from the time when the starting signal is high and effective for the next calculation until the calculation results of all the commands are finished.
10. The CPU can check the state of the response FIFO through the configuration module, if the response FIFO is not empty, the CPU indicates that a valid result exists currently, and the response FIFO can be read out.
Compared with the traditional method for detecting the number of the turning bits of 0 and 1, the method can improve the data comparison speed and improve the system efficiency. The device adopts two MASTER ports to fetch data at the same time instead of one MASTER port, so that extra space is not required to be opened up to store intermediate data, and the design is simplified. Meanwhile, the device supports a plurality of commands, supports a large number of operations, greatly improves the efficiency of the whole system and saves the test time.
The foregoing description is only for the basic principle and the preferred embodiments of the present invention, and modifications and substitutions by those skilled in the art are included in the scope of the present invention.
Claims (10)
1. An apparatus for counting the number of bits for turning over data 0 and 1, comprising: the system comprises a configuration module, a command FIFO, a response FIFO, a data flow control module, an adder, a master interface 1 and a master interface 2, wherein the data flow control module comprises a command processing module and a data processing module, the configuration module is connected with a control bus and used for receiving configuration information and a starting signal written by an external CPU through the control bus, the command FIFO is connected between the configuration module and the command processing module and used for receiving and storing the configuration information written by the configuration module and writing the configuration information into the command processing module, the command processing module calculates the storage address and the data length of original data and read data according to the configuration information, then sends the calculated original data address and data length signals to the master interface 1 and sends the calculated read data address and data length signals to the master interface 2, and the master interface 1 and the master interface 2 send the read data address and data length signals to the master interface 2 according to the received data address, The data length respectively captures corresponding data from the memory through a data bus, the captured data are returned to a data processing module, the data processing module compares the data returned by the master interface 1 and the master interface 2 bit by bit, the number of bit 1 inverted by bit 0 and the number of bit 0 inverted by bit 1 are counted, an adder accumulates the number of bit 1 inverted by bit 0 and the number of bit 0 inverted by bit 1, and the accumulated result is written into a response FIFO; the configuration information includes an original data address, a read data address, and a data length.
2. The apparatus for counting 0 and 1 bit flipping bits according to claim 1, wherein: the command FIFO stores configuration information for a plurality of commands.
3. The apparatus for counting 0 and 1 bit flipping bits according to claim 1, wherein: the master interface 1 and the master interface 2 capture data in parallel.
4. The apparatus for counting 0 and 1 bit flipping bits according to claim 1, wherein: the external CPU writes configuration information into the configuration module when the start signal of the configuration module is invalid, the start signal of the configuration module is set to be valid when full signals of the command FIFO and the response FIFO are invalid, and the start signal is set to be invalid after the configuration information of the command is written into the command FIFO.
5. The apparatus for counting 0 and 1 bit flipping bits according to claim 1, wherein: the data processing module outputs an effective ending signal after finishing the turning bit number of all the data of the command, at the moment, the accumulation result of the adder is the turning bit number of all the data of the command, and the adder writes the accumulation result into a response FIFO and then clears 0.
6. A method for counting the number of bits for turning over data 0 and 1 is characterized in that: the method comprises the following steps:
s01), the external CPU writes the configuration information of the command and the starting signal into the configuration module, and the configuration module writes the configuration information into the command FIFO, wherein the configuration information refers to the original data address of the command, the read data address and the data length;
s02), the command processing module in the data flow control module receives the configuration information transmitted by the command FIFO and obtains the information required by the current operation: the method comprises the steps that an original data address, a read data address and a read data length are obtained, because configuration information of a command needs to be split into a plurality of addresses and data lengths to be sent to a master interface, a command processing module splits the configuration information into a plurality of pieces according to a bus protocol and calculates the initial address and the data length of each piece, then the calculated original data address and the calculated data length are sent to the master interface 1, the calculated read data address and the calculated data length are sent to the master interface 2, and the data lengths sent to the two master interfaces are kept consistent;
s03), the master interface 1 receives the data address and the data length sent by the command processing module, starts data capture, and returns data to the data flow control module;
s04), the master interface 2 receives the data address and the data length sent by the command processing module, starts data capture and returns data to the data flow control module;
s05), the data processing module in the data flow control module compares and calculates the number of the bit 0 inverted into the bit and the number of the bit 1 inverted into the bit 0 from the head address of the returned data bit by bit, and outputs the result to the adder until the comparison of all the data of the current command is completed, and then outputs an effective ending signal;
s06), when step S05 is executed, the adder adds the output result of the data flow control module and the last accumulated result in real time, and outputs the current accumulated result, and when the data flow control module outputs an effective end signal, the accumulated result of the current adder is the final result;
s07), after the response FIFO receives the effective ending signal, the accumulation result of the current adder is stored;
s08), when the adder detects the effective end signal, the accumulated result is cleared to 0, and the next calculation is waited to start.
7. The method of claim 6, wherein the statistical data of 0 and 1 flip bit number comprises: and the action of writing the configuration information into the configuration module by the external CPU is executed circularly until the configuration information of all commands is written into the configuration module.
8. The method of claim 6, wherein the statistical data of 0 and 1 flip bit number comprises: step S03 is performed in parallel with step S04.
9. The method of claim 6, wherein the statistical data of 0 and 1 flip bit number comprises: inquiring whether the configured starting signal is valid or not through the control bus, and if the configured starting signal is invalid, writing the configuration information and the starting signal into the configuration module by the external CPU; the configuration module starting signal is set to be valid when full signals of the command FIFO and the response FIFO are invalid, and the starting signal is set to be invalid after the compared configuration information is written into the command FIFO.
10. The method of claim 6, wherein the method further comprises the following steps: the external CPU checks the state of the response FIFO through the configuration module, and if the response FIFO is not empty, the response FIFO indicates that a valid result is currently stored and can be read.
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