CN110888480A - Circuit for improving transient response of LDO (low dropout regulator) load - Google Patents
Circuit for improving transient response of LDO (low dropout regulator) load Download PDFInfo
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- CN110888480A CN110888480A CN201910961949.0A CN201910961949A CN110888480A CN 110888480 A CN110888480 A CN 110888480A CN 201910961949 A CN201910961949 A CN 201910961949A CN 110888480 A CN110888480 A CN 110888480A
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- mos tube
- ldo
- mpp
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Abstract
The invention discloses a circuit for improving transient response of LDO load, wherein a gate of an MPP of an MOS (metal oxide semiconductor) tube for supplying LDO power is connected with a main control loop, and the circuit is characterized in that: the LDO is connected with an auxiliary response circuit which is connected to the grid of the MOS tube MPP in a whole, the auxiliary response circuit is provided with an MOS tube MN2 and an amplifier AMP2, wherein the source electrode of the MOS tube MN2 is grounded, the drain electrode of the MOS tube MPP is connected with the grid of the MOS tube MPP, the grid of the MOS tube MN2 is connected with the output of the amplifier AMP2, one input end of the amplifier AMP2 is connected with a reference voltage VREF, and the other input end of the amplifier AMP2 is connected with a load feedback voltage VFB through. By applying the circuit improvement of the invention, the grid potential of the power supply MOS tube can be quickly responded and reduced by copying the precursor MOS and preferably selecting the amplifier as the alternative configuration when the load current is increased sharply, and the reduction amplitude of the output voltage is reduced, so that the stability of the output performance of the LDO is improved, the occupied area of the introduced device is limited, and the design requirement of chip miniaturization is met.
Description
Technical Field
The invention relates to a circuit design for optimizing the performance of an LDO (low dropout regulator), in particular to an improved circuit for overcoming the poor response speed of a traditional main control loop.
Background
The LDO, i.e., low dropout regulator, is a low dropout linear regulator, which is compared with a conventional linear regulator. The traditional linear voltage regulators such as 78XX series chips all require that the input voltage is at least 2V-3V higher than the output voltage, otherwise, the traditional linear voltage regulators cannot work normally. However, in some cases, such conditions are obviously too harsh, e.g. 5V to 3.3V, and the voltage difference between the input and the output is only 1.7V, which obviously does not satisfy the operating conditions of the conventional linear regulator. Under the circumstances, the voltage conversion chips of LDO type have been developed by chip manufacturers.
An LDO is a linear regulator that uses a transistor or Field Effect Transistor (FET) operating in its saturation region to subtract excess voltage from the applied input voltage to produce a regulated output voltage. By droop voltage is meant the minimum value of the difference between the input voltage and the output voltage required by the regulator to maintain the output voltage within 100mV above or below its nominal value. LDO (low dropout) regulators with a positive output voltage typically use a power transistor (also called pass device) as the PNP. This transistor allows saturation so the regulator can have a very low dropout voltage, typically around 200 mV; in contrast, the voltage drop of the conventional linear regulator using the NPN composite power transistor is about 2V. The negative output LDO uses an NPN as its pass device, which operates in a similar mode as the PNP device of the positive output LDO.
As can be seen from the circuit of the LOOP1 part outlined in fig. 1, the LDO is provided with a main control LOOP in addition to the POWER MOS and the load. Specifically, the source of the MOS transistor MPP (power MOS) of the LDO is connected to the input voltage VIN, the gate of the MOS transistor MPP is connected to the MOS transistor control output terminal of the main control loop, and the drain of the MOS transistor MPP is the output voltage VOUT and is connected to the load. The main control loop is provided with a MOS tube MN1 and an amplifier AMP1, wherein the source electrode of the MOS tube MN1 is grounded, the drain electrode is connected with the grid electrode of the MOS tube MPP, the grid electrode is connected with the output of the amplifier AMP1, one input end of the amplifier AMP1 is connected with a reference voltage VREF, and the other input end of the amplifier AMP1 is connected with a load feedback voltage VFB. To stabilize the output of the LDO, the main control loop tracks the load current through the feedback voltage VFB and passes control through the amplifier AMP1 and the MOS transistor MN1 to pull the gate of the POWER MOS low, thereby stabilizing the output voltage VOUT. However, the amplifier AMP1 commonly used at present is designed in a circuit system with consideration of the characteristic requirements of reducing noise interference and increasing the power supply ripple rejection ratio, and is often relatively complex in structure, thereby causing a deviation in the transient response effect of the load of the LDO, which results in a dip in the output voltage VOUT.
Disclosure of Invention
The invention aims to provide a circuit for improving the transient response of an LDO load, which solves the problem of insufficient transient response of the load.
The technical solution of the present invention for achieving the above object is a circuit for improving transient response of an LDO load, wherein a gate of an MPP of an MOS transistor for supplying the LDO load is connected to a main control loop, and the circuit is characterized in that: the LDO is connected with an auxiliary response circuit which is connected to the grid of the MOS tube MPP in a whole, the auxiliary response circuit is provided with an MOS tube MN2 and an amplifier AMP2, wherein the source electrode of the MOS tube MN2 is grounded, the drain electrode of the MOS tube MPP is connected with the grid of the MOS tube MPP, the grid of the MOS tube MN2 is connected with the output of the amplifier AMP2, one input end of the amplifier AMP2 is connected with a reference voltage VREF, and the other input end of the amplifier AMP2 is connected with a load feedback voltage VFB through.
Further, the master control loop is provided with a MOS tube MN1 and an amplifier AMP1, wherein the source electrode of the MOS tube MN1 is grounded, the drain electrode is connected with the gate electrode of the MOS tube MPP, the gate electrode is connected with the output of the amplifier AMP1, one input end of the amplifier AMP1 is connected with a reference voltage VREF, and the other input end of the amplifier AMP1 is connected with a load feedback voltage VFB.
Further, a source electrode of a MOS transistor MPP of the LDO is connected to the input voltage VIN, a gate electrode of the MOS transistor MPP is connected to respective MOS transistor control output terminals of the main control loop and the auxiliary response circuit, and a drain electrode of the MOS transistor MPP is connected to a load and is the output voltage VOUT.
The circuit improvement of the invention has prominent substantive features and remarkable progress: the circuit can quickly respond to the grid potential of a pull-down power supply MOS tube by copying a precursor MOS (MN 2) and preferably selecting an amplifier as a successive configuration when the load current is increased sharply, and the reduction amplitude of the output voltage is reduced, so that the stability of the output performance of the LDO is improved, the occupied area of an introduced device is limited, and the design requirement of chip miniaturization is met.
Drawings
Fig. 1 is a schematic circuit diagram of a transient response of a conventional LDO load.
FIG. 2 is a schematic diagram of the circuit structure for improving transient response of LDO load according to the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention is provided in connection with the accompanying drawings for the purpose of understanding and controlling the technical solutions of the present invention, so as to define the protection scope of the present invention more clearly.
The designer of the invention aims at the problem that the control loop of the prior LDO load transient response is objectively existed, namely, the amplifier AMP1 needs to consider the characteristic requirements of reducing noise interference, improving power supply ripple rejection ratio and the like in the traditional system design, and the structure is often relatively complex, so that the effect of the LDO load transient response is deviated, and the output voltage VOUT performance is unstable. The experience of the industry for many years is synthesized, and a circuit architecture for improving the transient response of the LDO load is innovated and provided, so as to be dedicated to the steady-state output of the LDO.
To more specifically understand, the schematic diagram of the circuit structure for improving the transient response of the LDO load according to the present invention as shown in fig. 2 can be seen. As described in detail in the background art, the main control LOOP1 connected to the gate of the LDO power supply MOS transistor MPP mainly plays a role in responding to changes in the load current slowly, and accurately adjusts the output voltage VOUT. As the specific characteristics of improvement of improving the transient response, the LDO is connected with an auxiliary response circuit which is connected into the MPP grid of the MOS tube together. Specifically, the auxiliary response circuit is provided with a MOS tube MN2 and an amplifier AMP2, wherein the source electrode of the MOS tube MN2 is grounded, the drain electrode is connected with the grid electrode of the MOS tube MPP, the grid electrode is connected with the output of the amplifier AMP2, one input end of the amplifier AMP2 is connected with a reference voltage VREF, and the other input end is connected with a load feedback voltage VFB through an offset voltage Vos. The figure shows that the amplifier is a mirror loop similar to the main control loop, and the implemented functions are the same, and the difference is that the selected amplifier AMP2 has simple structure and response speed which is much faster than that of the amplifier AMP 1. And the offset voltage Vos is a fixed value which is self-defined according to the variation range of the load current.
When the load current increases suddenly, the main control LOOP1 fails to respond due to inherent design defects, and in order to prevent the output voltage VOUT from falling off in a cliff manner, the auxiliary response circuit LOOP2 is utilized, when the load feedback voltage VFB decreases to the difference between the reference voltage VREF and the offset voltage Vos, the amplifier AMP2 outputs a high voltage, so that the MOS transistor MN2 replaces the MOS transistor MN1 of the main control LOOP for a short time, the POWER MOS gate of the LDO is pulled down rapidly, and the VOUT drop amplitude is within a controllable range.
In summary, with reference to the detailed description of the illustrated embodiments, the load transient response solution of the present invention has prominent substantive features and significant improvements: the circuit can quickly respond to the grid potential of a pull-down power supply MOS tube by copying a precursor MOS (MN 2) and preferably selecting an amplifier as a successive configuration when the load current is increased sharply, and the reduction amplitude of the output voltage is reduced, so that the stability of the output performance of the LDO is improved, the occupied area of an introduced device is limited, and the design requirement of chip miniaturization is met.
Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and modifications and equivalents within the scope of the claims may be made by those skilled in the art and are included in the scope of the present invention.
Claims (3)
1. The utility model provides a circuit for improving LDO load transient response, the grid of LDO power supply MOS pipe MPP connects to be equipped with main control loop, its characterized in that: the LDO is connected with an auxiliary response circuit which is connected to the grid of the MOS tube MPP in a whole, the auxiliary response circuit is provided with an MOS tube MN2 and an amplifier AMP2, wherein the source electrode of the MOS tube MN2 is grounded, the drain electrode of the MOS tube MPP is connected with the grid of the MOS tube MPP, the grid of the MOS tube MN2 is connected with the output of the amplifier AMP2, one input end of the amplifier AMP2 is connected with a reference voltage VREF, and the other input end of the amplifier AMP2 is connected with a load feedback voltage VFB through.
2. The circuit of claim 1, wherein the output of the LDO driver is configured to: the main control loop is provided with a MOS tube MN1 and an amplifier AMP1, wherein the source electrode of the MOS tube MN1 is grounded, the drain electrode of the MOS tube MPP is connected with the grid electrode of the MOS tube MPP, the grid electrode of the MOS tube MN is connected with the output of the amplifier AMP1, one input end of the amplifier AMP1 is connected with a reference voltage VREF, and the other input end of the amplifier AMP1 is connected with a load feedback voltage VFB.
3. The circuit of claim 1, wherein the output of the LDO driver is configured to: the source electrode of the MOS tube MPP of the LDO is connected with the input voltage VIN, the grid electrode of the MOS tube MPP is connected with the respective MOS tube control output ends of the main control loop and the auxiliary response circuit, and the drain electrode of the MOS tube MPP is the output voltage VOUT and is connected with the load.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910961949.0A CN110888480B (en) | 2019-10-11 | 2019-10-11 | Circuit for improving transient response of LDO (low dropout regulator) load |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910961949.0A CN110888480B (en) | 2019-10-11 | 2019-10-11 | Circuit for improving transient response of LDO (low dropout regulator) load |
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| CN110888480A true CN110888480A (en) | 2020-03-17 |
| CN110888480B CN110888480B (en) | 2022-03-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115129102A (en) * | 2022-05-27 | 2022-09-30 | 深圳市泰德半导体有限公司 | Low dropout regulator circuit and power management chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6201375B1 (en) * | 2000-04-28 | 2001-03-13 | Burr-Brown Corporation | Overvoltage sensing and correction circuitry and method for low dropout voltage regulator |
| CN102495656A (en) * | 2011-12-09 | 2012-06-13 | 电子科技大学 | Low dropout linear regulator |
| CN105549673A (en) * | 2015-12-25 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | Dual-mode switching type LDO circuit |
| US20160299518A1 (en) * | 2015-04-10 | 2016-10-13 | Rohm Co., Ltd. | Linear power supply circuit |
| US20190079552A1 (en) * | 2017-09-13 | 2019-03-14 | Rohm Co., Ltd. | Regulator circuit |
| US20190302819A1 (en) * | 2018-03-28 | 2019-10-03 | Qualcomm Incorporated | Methods and apparatuses for multiple-mode low drop out regulators |
| US20190302820A1 (en) * | 2018-04-02 | 2019-10-03 | Rohm Co., Ltd. | Series regulator |
-
2019
- 2019-10-11 CN CN201910961949.0A patent/CN110888480B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6201375B1 (en) * | 2000-04-28 | 2001-03-13 | Burr-Brown Corporation | Overvoltage sensing and correction circuitry and method for low dropout voltage regulator |
| CN102495656A (en) * | 2011-12-09 | 2012-06-13 | 电子科技大学 | Low dropout linear regulator |
| US20160299518A1 (en) * | 2015-04-10 | 2016-10-13 | Rohm Co., Ltd. | Linear power supply circuit |
| CN105549673A (en) * | 2015-12-25 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | Dual-mode switching type LDO circuit |
| US20190079552A1 (en) * | 2017-09-13 | 2019-03-14 | Rohm Co., Ltd. | Regulator circuit |
| US20190302819A1 (en) * | 2018-03-28 | 2019-10-03 | Qualcomm Incorporated | Methods and apparatuses for multiple-mode low drop out regulators |
| US20190302820A1 (en) * | 2018-04-02 | 2019-10-03 | Rohm Co., Ltd. | Series regulator |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115129102A (en) * | 2022-05-27 | 2022-09-30 | 深圳市泰德半导体有限公司 | Low dropout regulator circuit and power management chip |
| CN115129102B (en) * | 2022-05-27 | 2023-11-17 | 深圳市泰德半导体有限公司 | Low-dropout linear voltage regulator circuit and power management chip |
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| CN110888480B (en) | 2022-03-04 |
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