CN110888278A - Display panel - Google Patents
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- CN110888278A CN110888278A CN201911133623.5A CN201911133623A CN110888278A CN 110888278 A CN110888278 A CN 110888278A CN 201911133623 A CN201911133623 A CN 201911133623A CN 110888278 A CN110888278 A CN 110888278A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Mathematical Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
A display panel comprises a gate driving circuit, a plurality of pixels, a common electrode signal line and a plurality of scanning lines, wherein part of the pixels comprise virtual sub-pixels and normal sub-pixels, the virtual sub-pixels are arranged on the periphery of a display area, the common electrode signal line is located between the gate driving circuit and the display area of the display panel, the scanning lines comprise first scanning signal lines and second scanning signal lines which are arranged in different layers and connected through switching holes, a line changing area is arranged in the virtual sub-pixels, and the switching holes are arranged in the line changing area. The line changing area of the scanning line is internally arranged in the dotted line pixel, so that the scanning line is changed in the virtual pixel area, the original line changing area can be saved, the common electrode signal line has larger space, the common electrode signal line can be thickened, and the stability of the common electrode signal line is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel.
Background
The Gate Driver On Array, referred to as GOA for short, implements a driving method of scanning the Gate line by fabricating a line scanning driving signal circuit On an Array substrate by using an Array process in the existing thin film transistor liquid crystal display.
In the conventional GOA circuit design, because the output gate trace is a second-layer metal layer trace, if the common electrode trace is also designed as a second-layer metal layer trace, the gate trace can intersect with the common trace to form a shape similar to a Chinese character 'ding', and ESD (Electro-Static discharge) explosion easily occurs on the same-layer metal, so in order to avoid the risk of ESD explosion, generally, the common electrode trace adopts a first-layer metal trace, and the gate trace crosses the common electrode trace and then is switched into the first-layer metal trace to be connected into the display area through the via hole.
In the display panel, the more stable the common electrode is, the better the common electrode is, the common capacitance is generally increased, that is, the common electrode routing on the second metal layer is increased, so that the capacitance formed by the common electrode routing and the upper plate is increased. However, the space of the display panel is limited, the via hole of the gate line occupies a certain space, and there is not enough space reserved for the common electrode line, so that the common electrode line cannot be designed thick enough, and the stability of the common electrode line can be affected.
Disclosure of Invention
The invention provides a display panel, which can solve the technical problem that the stability of common electrode wiring is influenced because the common electrode wiring cannot be designed to be thick enough due to limited space of the conventional display panel.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the invention provides a display panel, which is provided with a display area and a non-display area, and comprises a grid driving circuit, a plurality of pixels, a common electrode signal line and a plurality of scanning lines; the grid driving circuit is arranged in the non-display area; the pixel arrays are arranged in the display area, part of the pixels comprise virtual sub-pixels and normal sub-pixels, and the virtual sub-pixels are arranged on the periphery of the display area; the common electrode signal line is arranged in a non-display area and is positioned between the grid driving circuit and the display area; the plurality of scanning lines are connected with the grid driving circuit and extend to the display area, and the scanning lines comprise first scanning signal lines and second scanning signal lines which are arranged in different layers and connected through switching holes; the virtual sub-pixels are internally provided with a line changing area, and the switching holes are arranged in the line changing area.
In at least one embodiment of the present invention, a thin film transistor is disposed in the normal sub-pixel, and the thin film transistor is not disposed in the dummy sub-pixel.
In at least one embodiment of the present invention, the first scanning signal line and the common electrode signal line are disposed in different layers, and the second scanning signal line and the common electrode signal line are disposed in the same layer.
In at least one embodiment of the present invention, the first scan signal line is connected to the gate driving circuit, and the second scan signal line is connected to a plurality of the pixels in the same row in the display region.
In at least one embodiment of the present invention, a plurality of the dummy sub-pixels are arranged along an extending direction of the common electrode signal line, and one of the dummy sub-pixels corresponds to one of the transfer holes.
In at least one embodiment of the present invention, one of the pixels located at the edge of the display area includes one of the dummy sub-pixels and two of the normal sub-pixels, and the dummy sub-pixel is adjacent to the common electrode signal line.
In at least one embodiment of the present invention, each of the dummy sub-pixels and the normal sub-pixels includes a main pixel region and a sub-pixel region, and the line changing region is disposed between the main pixel region and the sub-pixel region.
In at least one embodiment of the present invention, the dummy sub-pixel and the normal sub-pixel each include a pixel electrode.
In at least one embodiment of the present invention, the pixel electrode includes a main pixel electrode located in the main pixel region and a sub pixel electrode located in the sub pixel region.
In at least one embodiment of the present invention, the transfer hole is located between the main pixel electrode and the sub-pixel electrode of the dummy sub-pixel.
The invention has the beneficial effects that: the line changing area of the scanning line is internally arranged in the dotted line pixel, so that the scanning line is changed in the virtual pixel area, the original line changing area can be saved, the common electrode signal line has larger space, the common electrode signal line can be thickened, and the stability of the common electrode signal line is improved.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a pixel structure at the edge of a display panel according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a scan line on line change area of a display panel according to an embodiment of the invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
The invention aims at the technical problem that the stability of the common electrode wiring is influenced because the common electrode wiring cannot be designed to be thick enough due to the limited space of the display panel of the existing display panel, and the embodiment can solve the defect.
As shown in fig. 1, an embodiment of the present invention provides a display panel 100, where the display panel has a display area 101 and a non-display area 102, the non-display area 102 is located at a periphery of the display area 101, the display area 101 is used for implementing a display function, and the non-display area 102 is used for routing a driving circuit and providing a camera. The display panel 100 includes a gate driving circuit 10 located in a non-display region 102, a plurality of pixels 20 arranged in an array in the display region 101, a common electrode signal line 30 arranged in the non-display region 102, and a plurality of scan lines 40.
The common electrode signal line 30 is disposed between the gate driving circuit 10 and the display region 101, and the scan line 40 is connected to the gate driving circuit 10 and extends into the display region 101.
Since the scan line 40 needs to cross the common electrode signal line 30 and then be connected to the display region 101, if the scan line 40 and the common electrode signal line 30 are disposed on the same layer, the two signal lines will intersect inevitably to cause ESD damage, so as to avoid the risk of ESD damage, in the embodiment of the present invention, the scan line 40 is subjected to line replacement processing, such that a portion of the scan line 40 is disposed on a different layer from the common electrode signal line 30, and another portion is disposed on the same layer as the common electrode signal line 30, thereby avoiding the scan line 40 from contacting the common electrode signal line 30.
As shown in fig. 2, specifically, the scan line 40 includes a first scan signal line 41 and a second scan signal line 42, the first scan signal line 41 and the second scan signal line 42 are disposed in different layers, and the first scan signal line 41 and the second scan signal line 42 are connected through a via hole 401. Since the switch hole 401 is used to electrically connect the first scanning signal line 41 and the second scanning signal line 42, no other conductive device can be disposed in the film layer region where the switch hole 401 is located, and the switch hole 401 needs to be disposed separately, so as to avoid contact with other conductive devices.
One of the pixels 20 includes three sub-pixels, each of which is one of R, G, B sub-pixels. As shown in fig. 2, a part of the pixels 20 includes, in addition to the normal sub-pixels 22, the virtual sub-pixels 21, the normal sub-pixels 22 are used for emitting light normally and displaying corresponding colors, the virtual sub-pixels 21 are not used for displaying, and the virtual sub-pixels 21 are used for etching the pixel electrodes mentioned later uniformly on the display panel 100.
The virtual sub-pixels 21 are arranged on the periphery of the display area 101, the line changing area 203 is arranged in the virtual sub-pixels 21, the switching holes 401 are arranged in the line changing area 203, and since the virtual sub-pixels 21 are not used for displaying and do not need to access corresponding signals, original thin film transistors of the virtual sub-pixels 21 are not connected with other devices and belong to an independent state, the thin film transistors in the virtual sub-pixels 21 can be removed, the line changing area 203 is arranged in the area where the thin film transistors are located, and therefore the switching holes 401 are prevented from contacting other metal devices.
In the prior art, generally, line changing is performed between the common electrode signal line 30 and the display area 101, and the switching hole 401 for line changing of the scan line 40 needs to be separately arranged, and occupies a space of the common electrode signal line 30, so that a line width of the common electrode signal line 30 cannot be designed to be wide, and stability of the common electrode signal line 30 is affected.
In the horizontal direction of the display panel 100, one end of the first scanning signal line 41 is connected to the gate driving circuit 10, and the other end crosses over the common electrode signal line 30, and is connected to the second scanning signal line 42 through the switch hole 401, and the second scanning signal line 42 is connected to the plurality of pixels 20 in the same row.
The first scanning signal line 41 and the common electrode signal line 30 are arranged in different layers, the second scanning signal line 42 and the common electrode signal line 30 are arranged in the same layer, and the second scanning signal line 42 is arranged to avoid other metal signal lines.
The first scanning signal line 41 and the second scanning signal line 42 are separated by an insulating layer, and the switch hole 401 penetrates through the insulating layer.
A plurality of the dummy sub-pixels 21 are arranged along the extending direction of the common electrode signal line 30, and each of the dummy sub-pixels 21 has one of the switch holes 401, that is, one of the dummy sub-pixels 21 corresponds to one of the scan lines 40.
The gate driving circuit 10 may be disposed at one side of the display region 101, or disposed at multiple sides of the display region 101, as shown in fig. 1, in this embodiment, the gate driving circuit 10 is disposed at two opposite sides of the display region 101, two opposite ends of one scanning line 40 are respectively connected to the gate driving circuits 10 at two sides of the display region 101, and the gate driving circuits 10 at two sides input driving signals from the edge of the display region 101 to the middle, so as to quickly implement gate scanning on the same row and avoid the delay of the signals. In other embodiments, the gate driving circuit 10 on one side of the display region 101 is connected to the scan lines 40 in odd rows, and the gate driving circuit 10 on the other opposite side is connected to the scan lines 40 in even rows.
Since one scanning line 40 connects the gate driving circuits 10 on both sides in the present embodiment, the scanning line 40 includes two first scanning signal lines 41 and one second scanning signal line 42 connecting the two first scanning signal lines 41. In other embodiments, when the gate driving circuit 10 is disposed only on one side of the display region 101, the scan lines 40 may include one first scan signal line 41 and one second scan signal line.
Since the same scan line 40 needs two switching holes 401 to perform line switching, a plurality of dummy sub-pixels 21 provided with the line switching region 203 are arranged along the edges of two opposite sides of the display region 101, that is, two columns of the dummy sub-pixels 21 are provided in the two side edge regions of the display region 101 corresponding to two gate driving circuits 10, and the scan line 40 in the same row corresponds to two of the dummy sub-pixels 21.
As shown in fig. 2, one of the pixels 20 at the edge of the display region 101 includes one of the dummy sub-pixels 21 and two of the normal sub-pixels 22, and the dummy sub-pixel 21 is closer to the common electrode signal line 30 than the other two of the normal sub-pixels 22.
The sub-pixels (the dummy sub-pixel 21 and the normal sub-pixel 22) of the pixel 20 include a main pixel area 201 and a sub-pixel area 202, the line changing area 203 of the dummy sub-pixel 21 is disposed between the main pixel area 201 and the sub-pixel area 202, and the normal sub-pixel 22 is disposed with a thin film transistor at a position corresponding to the line changing area 203.
The sub-pixels of the pixel 20 include pixel electrodes, the pixel electrodes include a main pixel electrode 211 and a sub-pixel electrode 212, the main pixel electrode 211 is located in the main pixel region 201, the sub-pixel electrode 212 is located in the sub-pixel region 202, the scan line 40 is located between the main pixel electrode 211 and the sub-pixel electrode 212, and the switch hole 401 is located between the main pixel electrode 211 and the sub-pixel electrode 212 of the virtual sub-pixel 21.
The display panel 100 further includes a plurality of data lines 50, the data lines 50 and the scan lines 40 are perpendicularly crossed to each other to define a plurality of sub-pixel regions, and each data line 50 corresponds to a column of normal sub-pixels 22.
In the present embodiment, the normal sub-pixel 22 includes three thin film transistors including a gate electrode, an active layer, a source electrode, a drain electrode, and the like.
The first scanning signal line 41, the data line 50, the source electrode, and the drain electrode may be disposed at the same layer and formed through the same patterning process.
The second scan signal line 42, the common electrode signal line 30, and the gate electrode may be disposed at the same layer and formed through the same patterning process.
As shown in fig. 3, the display panel 100 further includes a substrate 23, a buffer layer 24, the second scanning signal line 42, a gate insulating layer 25, the first scanning signal line 41, an interlayer insulating layer 26, the main pixel electrode 211 and the sub-pixel electrode 212 are sequentially disposed on the substrate 23, the switch hole 401 is disposed on the gate insulating layer 25, and when the first scanning signal line 41 and the second scanning signal line 42 are disposed on other film layers, the switch hole 401 may be located on other insulating layers.
As shown in fig. 1, the non-display area 102 is further provided with a control board (C-board)60 and two source boards 70 (X-boards) connected to the control board 60, an edge area of the display area 101 near the source board 70 is provided with fan-shaped WOA (Wire On Array) areas 80 distributed at intervals, the WOA areas 80 are connected to the source boards 70, a plurality of WOA traces are connected to the WOA areas 80, and the WOA traces the data lines 50, so as to connect the data lines 50 to the control board 60, thereby realizing control of the control board 60 On power signals of corresponding timings of the display area.
Has the advantages that: the line changing area of the scanning line is internally arranged in the dotted line pixel, so that the scanning line is changed in the virtual pixel area, the original line changing area can be saved, the common electrode signal line has larger space, the common electrode signal line can be thickened, and the stability of the common electrode signal line is improved.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. A display panel having a display region and a non-display region,
the display panel includes:
the grid driving circuit is arranged in the non-display area;
the array is arranged in the display area, part of the pixels comprise virtual sub-pixels and normal sub-pixels, and the virtual sub-pixels are arranged on the periphery of the display area;
the common electrode signal line is arranged in a non-display area and is positioned between the grid driving circuit and the display area; and
the scanning lines are connected with the grid driving circuit and extend to the display area, and comprise first scanning signal lines and second scanning signal lines which are arranged in different layers and connected through switching holes; wherein the content of the first and second substances,
a line changing area is arranged in the virtual sub-pixel, and the switching hole is arranged in the line changing area.
2. The display panel according to claim 1, wherein a thin film transistor is disposed in the normal sub-pixel, and the thin film transistor is not disposed in the dummy sub-pixel.
3. The display panel according to claim 1, wherein the first scanning signal line and the common electrode signal line are provided in different layers, and wherein the second scanning signal line and the common electrode signal line are provided in the same layer.
4. The display panel according to claim 1, wherein the first scanning signal line is connected to the gate driver circuit, and wherein the second scanning signal line is connected to a plurality of the pixels in a same row in the display region.
5. The display panel according to claim 4, wherein a plurality of the dummy sub-pixels are arranged along an extending direction of the common electrode signal line, and one of the dummy sub-pixels corresponds to one of the transfer holes.
6. The display panel according to claim 1, wherein one of the pixels located at the edge of the display region includes one of the dummy sub-pixels and two of the normal sub-pixels, and the dummy sub-pixel is close to the common electrode signal line.
7. The display panel according to claim 1, wherein the dummy sub-pixel and the normal sub-pixel each include a main pixel region and a sub-pixel region, and the line change region is disposed between the main pixel region and the sub-pixel region.
8. The display panel according to claim 7, wherein the dummy sub-pixel and the normal sub-pixel each include a pixel electrode.
9. The display panel according to claim 8, wherein the pixel electrode comprises a main pixel electrode located in the main pixel region and a sub-pixel electrode located in the sub-pixel region.
10. The display panel of claim 9, wherein the transfer aperture is located between the main pixel electrode and the sub-pixel electrode of the dummy sub-pixel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911133623.5A CN110888278B (en) | 2019-11-19 | 2019-11-19 | Display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911133623.5A CN110888278B (en) | 2019-11-19 | 2019-11-19 | Display panel |
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| CN110888278A true CN110888278A (en) | 2020-03-17 |
| CN110888278B CN110888278B (en) | 2023-02-28 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111427206A (en) * | 2020-03-24 | 2020-07-17 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN111474781A (en) * | 2020-04-13 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN111752022A (en) * | 2020-07-14 | 2020-10-09 | 武汉华星光电技术有限公司 | Display panel and display device |
| CN111798755A (en) * | 2020-07-07 | 2020-10-20 | Tcl华星光电技术有限公司 | Display panel |
| CN112068728A (en) * | 2020-08-17 | 2020-12-11 | 武汉华星光电技术有限公司 | Display device and electronic apparatus |
| CN113471257A (en) * | 2021-06-21 | 2021-10-01 | Tcl华星光电技术有限公司 | Display panel and mobile terminal |
| CN114446260A (en) * | 2022-03-24 | 2022-05-06 | 北京京东方显示技术有限公司 | Array substrate and display device |
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