KR20140116990A

KR20140116990A - Array substrate

Info

Publication number: KR20140116990A
Application number: KR1020130031364A
Authority: KR
Inventors: 김대일; 한용철; 홍성일; 장형진
Original assignee: 엘지디스플레이 주식회사
Priority date: 2013-03-25
Filing date: 2013-03-25
Publication date: 2014-10-07

Abstract

The present invention provides, in an array substrate which has an image display region at the center thereof and a first, a second, a third, and a forth non-display region which are defined in the upper, the lower, the left, and the right part of the display region, an array substrate including gate lines and date lines which are formed by defining pixel regions which intersect with each other in the display region; and a pad part defined in at least one non-display region among the first, the second, the third, and the forth non-display region. In the pad part, one end of the gate line and the data line is connected to a pad electrode and is arranged in a multi row structure.

Description

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate, and more particularly, to an array substrate having a pad electrode arrangement structure capable of realizing a fixed display area without reduction in width.

Recently, the display field for processing and displaying a large amount of information has been rapidly developed as society has entered into a full-fledged information age. Recently, flat panel display devices having excellent performance such as thinning, light weight, and low power consumption have been developed A liquid crystal display or an organic electroluminescent device has been developed to replace a conventional cathode ray tube (CRT).

Among liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching device capable of controlling voltage on and off for each pixel, The ability is excellent and is getting the most attention.

In addition, since the organic electroluminescent device has a high luminance and a low operating voltage characteristic and is a self-luminous type that emits light by itself, it has a large contrast ratio, can realize an ultra-thin display, has a response time of several microseconds Mu s), has no limitation of viewing angles, is stable at low temperatures, and is driven at a low voltage of 5 to 15 V DC, making it easy to manufacture and design a driving circuit, and has recently attracted attention as a flat panel display device.

In this liquid crystal display device and the organic electroluminescent device, an array substrate including a thin film transistor, which is a switching element, is constituted in order to commonly turn on / off each pixel region.

Fig. 1 is a schematic plan view of a conventional general array substrate, and Fig. 2 is an enlarged view of a pad portion of a conventional general array substrate.

A plurality of gate pad electrodes (not shown) and data pad electrodes (not shown) connected to the printed circuit board 50, which is an external circuit, are formed on the upper and left non-display areas NA1 and NA4 of the array substrate 1, 37, and a gate and a data link wiring (not shown) connected to the gate and the data line, respectively.

A plurality of gate wirings 13 connected to the respective gate pad electrodes (not shown) through the gate link wirings (not shown) and extending in the horizontal direction are formed in the display area DA of the array substrate 1, And data lines (not shown) extending in the vertical direction connected to the respective data pad electrodes 37 and the data link lines 31 intersect with each other to define a plurality of pixel regions P .

In the display area DA, a thin film transistor Tr is formed in the vicinity of the intersection of the gate and the data line (not shown). In each pixel area P, And a pixel electrode 40 connected to an electrode (not shown).

The driving unit for driving the array substrate 1 having such a configuration is implemented in the printed circuit board 50. The printed circuit board 50 is connected to the gate pad (Not shown) and the data pad electrode 37. To this end, the printed circuit board 50 is electrically connected to the gate and data pad electrodes (not shown) And a flexible printed circuit board (FPC) 62 provided with a driving IC chip 72. The flexible printed circuit board (FPC)

The pad portion PA of the general array substrate 1 is connected to the gate or data lines 13 and 30 through the link line 31 and includes a gate and a data pad electrode (not shown).

At this time, the gate pad electrode (not shown) and the data pad electrode 37 have a width larger than that of the gate wiring 13, the data wiring 30, or the link wiring 31 in the same single column, .

Meanwhile, in recent years, the flat panel display device is provided with a smaller pixel area (P) in order to realize a clearer picture quality. For this purpose, the pitch between the pixel areas (P) is gradually decreasing.

Therefore, as the width of the pixel region P is reduced for realizing the picture pitch, the spacing between the gate and the data lines 13 and 30 defined by defining the pixel region P is narrowed.

As a result, the spacing distance between the gate and the data pad electrode (not shown) connected to the gate and data lines 13 and 30 is also narrowed. By reaching the minimum limit at which the short defect can be prevented, (Not shown) can not be reduced.

The gate and data pad electrodes (not shown) are electrically connected to a driving unit provided in the printed circuit board 50 via the FPC 62. The FPC 62 is electrically connected to the driving circuit There is a minimum required width since the FPC 62 should be considered to expand and contract due to a process such as alignment error and thermocompression in the process of bonding to the pad portion PA. (Not shown) 37 having a plurality of through holes (not shown) is formed, the contact failure with the wiring (not shown) provided in the FPC 62 is frequent.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an array substrate having a pad structure capable of suppressing defects in mounting a pad and a printed circuit board while realizing high quality display quality with fixed pitch and pitch The purpose is to provide.

According to an embodiment of the present invention, there is provided an array substrate having first, second, third, and fourth non-display regions defined by a central image display region and upper and lower, left and right sides of the display region, A plurality of gate wirings and data wirings formed to define a plurality of pixel regions crossing each other in the display region; A pad portion is defined in at least one non-display region of the first, second, third, and fourth non-display regions, and the pad portion is connected to one end of the gate wiring and the data wiring, As shown in FIG.

At this time, in the pad electrode arranged in the multi-column structure, an insulating film is formed on the gate wiring and the data wiring located between neighboring pad electrodes.

And an auxiliary pad electrode made of a transparent conductive material is formed on the pad electrode.

The pad electrode, the gate wiring and the data wiring are connected to each other via a link wiring. In the pad electrode arranged in the multi-column structure, the link wiring located between neighboring pad electrodes is connected to the upper Is formed. An auxiliary pad electrode made of a transparent conductive material is formed on the pad electrode. The pad electrode and the link wiring are formed in different layers, and the pad electrode and the link wiring are electrically connected by the auxiliary pad electrode Feature.

The pad electrodes are sequentially numbered from 1 to n (n is an integer greater than m) sequentially from the top down or from left to right, and m (m is any one of 2, 3, and 4) column arrangement, the first to m columns are arranged such that the same pad electrode is located when n is divided by m.

The pad electrode may have a polygonal shape, a circular or elliptic shape, and the wiring connected to the pad electrode may have a straight line shape or a shape bent or bent along the shape of the pad electrode .

In each pixel region, a thin film transistor connected to the gate and the data line and a pixel electrode connected to one electrode of the thin film transistor are formed.

The array substrate according to an exemplary embodiment of the present invention may be configured such that the gate pad electrode and the data pad electrode connected to the gate and the data line are arranged in a multi-row structure corresponding to a plurality of columns of the second column to the fourth column without being arranged in a single column, It is possible to have a pixel area of a fixed number of pixels and to have a size larger than a predetermined width required for mounting the printed circuit board via the FPC, thereby suppressing a poor mounting defect including a short defect.

In addition, since the area of the pad electrode itself can be increased relative to the single row arrangement structure by the multi-row arrangement of the pad electrode, the increase in indentation has the effect of improving the conduction capability between the pad portion and the FPC.

In addition, since the width of the pad electrode according to the embodiment of the present invention can be reduced, the length of the pad electrode in the direction perpendicular to the width of the pad electrode can be reduced compared to the array substrate having a single column arrangement structure. .

In addition, since the width of the pad electrode of the array substrate according to the embodiment of the present invention is not equal to or greater than the width level of the pad electrode of the array substrate, the FPC bonded to the array substrate is also bent, It is possible to mount an FPC having a structure capable of suppressing the occurrence of the defects.

Further, the array substrate according to the embodiment of the present invention may have a structure in which the shape of the pad electrode in each column is different or the wiring located in the periphery of the pad electrode is bent or bent along the shape of the pad electrode Thereby effectively increasing the surface area of the pad electrode itself and finally increasing the amount of indentation.

1 is a schematic plan view of a conventional array substrate;
2 is an enlarged view of a pad portion of a conventional array substrate;
3 is a schematic plan view of an array substrate according to an embodiment of the present invention.
4 is an enlarged view of a part of a pad portion of an array substrate according to an embodiment of the present invention;
5A and 5B are diagrams showing the arrangement of pad electrodes in an array substrate according to a modification of the embodiment of the present invention.
6 is a sectional view of a general FPC;
7 is a cross-sectional view of an FPC having bending durability.
8A to 8C are diagrams showing various plan shapes of pad electrodes in an array substrate according to an embodiment of the present invention.
9 is a cross-sectional view of a portion cut along line IX-IX of Fig. 4; Fig.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the accompanying drawings.

FIG. 3 is a schematic plan view of an array substrate according to an embodiment of the present invention, and FIG. 4 is an enlarged view of a part of a pad portion of an array substrate according to an embodiment of the present invention.

The array substrate 101 according to the embodiment of the present invention includes a rectangular display area DA for displaying an image when a flat panel display device is constructed and a display area DA outside the display area DA Four non-display areas NA1, NA2, NA3, and NA4 are provided in a frame shape.

NA1, NA2, NA3 and NA4 of one of the four non-display areas NA1, NA2, NA3 and NA4. More precisely, one end of the data line 130 or a link wiring (not shown) (Not shown) connected to an internal wiring (not shown) and an IC chip 172 connected to a non-display area (hereinafter referred to as a first non-display area) The printed circuit board 150 is mounted through a plurality of FPCs 162. [

Although the printed circuit board 150 is shown only in the first non-display area NA1 in the drawing, the printed circuit board 150 may include a gate printed circuit board 150 connected to the gate wiring 113, (Not shown) for data and a data circuit board (not shown) connected to the data line 130. The liquid crystal display device according to any one of the first to fourth non-display areas NA1, NA2, NA3, Area.

In this case, when the printed circuit board 150 is mounted only on one non-display area NA1 as in the embodiment of the present invention, the remaining non-display areas NA2, NA3, Display area NA1 on which the printed circuit board 150 is mounted, it is possible to realize a narrow bezel.

Referring to the display area DA of the array substrate 101 according to the embodiment of the present invention, gate wirings are formed with a predetermined spacing.

Although not shown in the drawing, a common wiring (not shown) may be formed in parallel with the gate wiring 113, selectively spaced apart from the gate wiring 113 depending on what type of flat panel display device the array substrate 101 is formed .

In addition, a plurality of data lines 130 are formed to intersect the gate line 113 with a gate insulating film (not shown) interposed therebetween. At this time, the regions that are intersected by the gate wiring 113 and the data wiring 130 intersect each other constitute the pixel region P. [

Each pixel region P is provided with a thin film transistor Tr which is connected to the gate wiring 113 and the data wiring 130 and is a switching element.

Although not shown in the drawings, when the array substrate 101 is an array substrate constituting an organic electroluminescent device in a flat panel display device, power supply lines (not shown) arranged in parallel with the gate lines 113 or the data lines 130 In addition to the thin film transistors Tr connected to the gate and data lines 113 and 130, one or more driving thin film transistors (not shown) are additionally provided in each pixel region P .

The driving thin film transistor (not shown) is selectively connected to the thin film transistor Tr and power supply wiring (not shown) serving as a switching element and further includes a first electrode (not shown) and an organic light emitting layer And an organic light emitting diode (not shown) including a second electrode (not shown).

The thin film transistor Tr may be a thin film transistor including a semiconductor layer or an oxide semiconductor layer of amorphous silicon, or may be a thin film transistor including polysilicon as a semiconductor layer.

The gate wiring 113 and the data wiring 130 are connected to the gate of the pad portion PA implemented at one end of the first non-display area NA1 through the link wiring 131, And is connected to a data pad electrode (not shown) 131.

The gate line 113 and the data line 130 may extend to the pad portion PA to form the link wiring 131 itself.

At this time, the gate and data pad electrodes (not shown) 131 are the most characteristic configuration of the embodiment of the present invention and have a width larger than the width of the gate wiring 113, the data wiring 130, or the wiring wiring 131 And the gate and data pad electrodes (not shown) 137 provided in the pad portion PA are arranged in a plurality of rows, for example, the first to fourth rows, instead of being arranged in a single row .

Hereinafter, the gate pad electrode (not shown) and the data pad electrode 137 have the same planar structure. Therefore, for convenience of explanation, the gate pad electrode 137 and the data pad electrode 137 are referred to as a pad electrode 137.

4A and 4B show one example in which the pad electrodes 137 are arranged in two rows. As a variation thereof, Figs. 5A to 5B (Figs. 5A to 5B are views showing an example of a modification of the array substrate according to the modification of the embodiment of the present invention 5A, the pad electrode 137 may have a three-row arrangement structure. Further, as shown in FIG. 5B, the pad electrode 137 may be arranged in a four- Structure.

4, the gate wiring (113 in FIG. 3) and the data wiring (130 in FIG. 3) provided in the display region are moved from the upper portion to the lower portion Numbered data (or gate) wiring 130 and the odd-numbered pad electrodes 137a connected to the odd-numbered data (or gate) wiring 130 are all located in the first column when sequentially numbered from left to right, And the even-numbered pad electrodes 137b connected to the even-numbered pad electrodes 137b may all be located in the second column.

5A, when the pad electrode 137 has a three-row arrangement structure, when data (or gate) wiring 130 connected to the pad electrode 137 (130 in FIG. 3) The data (or gate) wiring 130 of the first group (or the gate) wiring 130 (FIG. 3) having 0, 1 and 2 is defined as the first, The pad electrode 137a connected to the second group of data (or gate) lines 130 is located in the second column and the pad electrode 137b connected to the second group of data (or gate) The pad electrode 137c connected to the wiring (130 in FIG. 3) may be located in the third row.

5B, when the pad electrode 137 has a four-row arrangement structure, when data (or gate) wiring 130 connected to the pad electrode 137 (130 in FIG. 3) (Or gate) wiring (130 in FIG. 3) having 0, 1, 2 and 3 as the first, second, third and fourth groups, respectively, The pad electrode 137a connected to the second group of data (or gate) wiring 130 (FIG. 3) is located in the first column, and the pad electrode 137b connected to the second group of data (or gate) , The pad electrode 137c connected to the third group of data (or gate) wiring (130 in FIG. 3) is located in the third column, and the data (or gate) wiring And the pad electrode 137d connected to the pad electrode 137d may be located in the fourth column.

At this time, the positions of the pad electrodes connected to the data (or gate) wiring (130 in FIG. 3) of each group need not always be located at the above-mentioned positions, can do.

Referring to FIGS. 3 and 4, when the pad electrode 137 has a plurality of column arrangement structures instead of a single column, the pixel area P has a fixed pitch structure with a smaller pitch, The pad electrode 137 itself has a width corresponding to the pitch of the pixel region provided in the array substrate having a normal pitch rather than the pitch of the fine pitches even if the width of the spacing between the gate lines 130 or the gate lines 113 becomes narrow The spacing between the pad electrodes 137 can be maintained at least as wide as the width at which no short-circuiting occurs. As a result, the short-circuit defect caused by the small width of the pad electrode 137 generated when the FPC 162 is bonded It is possible to suppress the occurrence of such a phenomenon.

In addition, since the area of the pad electrode 137 itself can be increased relative to the single column arrangement structure by the multi-row arrangement of the pad electrode 137, it is possible to increase the conductivity between the pad portion PA and the FPC 162 .

The indentation means a connection between the pad electrode 137 and a plurality of internal wirings (not shown) provided on the FPC 162 in the process of bonding the FPC 162 to the pad portion PA of the array substrate 101 (Not shown) having a plurality of conductive balls (not shown) is resumed, and the ACFs (not shown) for resuming the ACFs (not shown) between the pad electrodes 137 and the internal wirings Is defined as the number of balls (not shown).

Therefore, there is a range of indentation required for normal conduction between the pad electrode 137 and the corresponding internal wiring (not shown) in the FPC 162. In order to have a minimum indentation, the pad electrode 137 It should have an area over a certain size.

Therefore, in the case of a general array substrate (1 in Fig. 1) in which the pad electrodes 137 are arranged in a single row, in order to satisfy the indentation range required when reducing the width of the pad electrode (37 in Fig. 2) The length of the pad electrode (37 in Fig. 2) is relatively increased.

However, in the case of the array substrate 101 according to the embodiment of the present invention, since the pad electrode 137 has a multi-row arrangement structure, each pad electrode 137 has a sufficiently large width Therefore, since the length of the pad electrode 137 does not need to be increased, the increase in the width of the pad portion PA can be relatively reduced.

Accordingly, in the array substrate 101 according to the embodiment of the present invention, the width of the pad electrode 137 is increased to reduce the length of the pad electrode 137 in the direction perpendicular to the width of the pad electrode 137, So that it is advantageous in that the width of the pad portion PA is relatively reduced.

In order to realize a fixed three-dimensional structure capable of suppressing a short-circuit defect when the FPC 162 is bonded, the pad electrodes 137 are arranged in a multi-row structure. Since the width of the pad electrode 137 is not equal to or greater than the width of the pad electrode of a general array substrate other than the fixed three-dimensional structure, the FPC 162 bonded to the pad electrode 137 is also bent It is also possible to mount the FPC 162 having a structure capable of suppressing the defects.

In the case of a general FPC, as shown in FIG. 6 (a sectional view of a general FPC), an internal wiring 220 made of a conductive material is formed on a base film 210, 230, and the insulating layer 230 is removed and exposed in correspondence with one end of the internal wiring 220 bonded to the pad portion of the array substrate.

In the case of a general FPC 201 having such a configuration, an ACF (anisotropic conductive film) (not shown) is interposed and bonded corresponding to a portion A1 attached to the pad portion of the array substrate, A part of the area A1 where the insulating layer 230 is not formed is present in the area A1 and the part of the internal wiring 220 that is the closest to the area A1 is bonded to the FPC 201, A phenomenon occurs in which the durability is reduced.

Therefore, as shown in Fig. 7 (sectional view of the FPC having bending durability) in place of the FPC 201 in which the durability of the base film 310 is lowered during bending, And a metal pattern 340 corresponding to each pad electrode of a portion of the insulating layer 330 which is to be bonded to a pad portion of the array substrate. And the internal wiring 320 are electrically connected to each other through the via hole hl.

The FPC 301 having such a structure including the metal pattern 340 is provided with the insulating layer 330 on the entire surface of the inner wiring 320 so that the effect of suppressing the creep generated in the inner wiring 320 upon bending .

However, in the case of the FPC 301 resistant to bending, in order to form the via hole hl for the conduction between the metal pattern 340 and the inner wiring 320, the metal pattern 340 must be at least a predetermined width do. At this time, the predetermined width is about the width of the pad electrode provided on the array substrate, not the fixed three-dimensional structure.

In the case of the array substrate (1 in FIG. 1) having the pad electrode having the single column array structure, if the fixed three-layer structure having the fine pitch is formed, the width of the pad electrode (37 in FIG. 2) The FPC (301 in Fig. 7) having excellent durability can not be used.

7) of the metal pattern (340 in FIG. 7) formed in the FPC having the bending durability (301 in FIG. 7) is formed larger than the pad electrode, the metal pattern (340 in FIG. 7) Contact with the pad electrode which causes short-circuit failure.

3 and 4, in the case of the array substrate 101 having the pad electrode 137 having the multi-row arrangement structure according to the embodiment of the present invention, the pad electrode 137 has a pitch of The width of the pad electrode 137 itself is equal to or greater than the width of the pad electrode (37 in FIG. 2) of the array substrate (1 in FIG. 1) It is possible to freely use the FPC (301 in Fig. 7) resistant to bending.

Therefore, the array substrate 101 according to the embodiment of the present invention has the durability in bending the FPC (301 in Fig. 7) compared to the conventional array substrate (1 in Fig. 1) Is improved.

Referring to FIG. 4, the pad electrode 137 of the array substrate 101 according to the embodiment of the present invention has a rectangular shape. However, FIGS. 8A to 8C The pad electrode 137 may have a polygonal shape such as a pentagon or a hexagon as well as a circular or elliptical shape as well as a rectangular shape as shown in various plane shapes of the pad electrode in the array substrate according to the present invention. It can be done.

In this case, the wiring (gate and data wiring or link wiring) 131 connected to the pad electrode 137 having various various shapes may be formed by bending or bending along the shape of the pad electrode 137.

Furthermore, the pad electrodes 137 arranged in multiple rows in the pad portion PA of the array substrate 101 may have different shapes in each row. That is, for example, the pad electrode 137 located in the first column has a rectangular shape, and the pad electrode 137 located in the second column may have a hexagonal shape.

The shape of the pad electrode 137 in each row is different and the wiring 131 located around the pad electrode 137 is bent or bent along the shape of the pad electrode 137, To effectively increase the surface area by effectively utilizing the spacing between the wirings 131 through the efficient arrangement of the electrodes 137 to finally increase the amount of indentation.

As another structural feature of the array substrate 101 according to the embodiment and the modification example of the present invention having the pad electrode 137 having the various features and having the multi-row arrangement characteristic, Sectional view of a portion cut along the cutting line IX-IX), the wiring (the gate or the data wiring itself or the wiring wiring connected to these wirings) 131 located between the adjacent pad electrodes 137 The insulating film 190 is provided on each of the wirings 131.

Since the insulating layer 190 is provided on the wiring 131 located between the neighboring pad electrodes 137, the pad portion provided with the pad electrode 137 and the FPC (162 of FIG. 3) (Not shown) or a metal pattern (not shown) provided in the FPC (FIG. 3) 162 is exposed to the outside of the corresponding pad electrode 137, (A gate or a data wiring itself or a link wiring connected to these wirings) 131 connected to another pad electrode 137 located closest to the pad electrode 137 is suppressed You can do it.

3, the pad electrode 137 and the wiring 131 connected to the pad electrode 137 are connected to the substrate (not shown). The pad electrode 137 and the data pad electrode 137 are connected to the data line The gate insulating layer 114 covers the wiring 131 and the insulating layer 190 is formed on the gate insulating layer 114. When the pad electrode 137 is a gate pad electrode, The pad electrode and the wiring connected to the pad electrode may be formed on the substrate 101, and the gate insulating film 114 and the insulating film 190 may be formed to cover the wiring.

In this case, the pad electrode 137 and the wiring 131 connected thereto are formed in different layers without necessarily being formed on the same layer where the pad electrode 137 is formed. In this case, corresponding to the pad electrode 137 And the auxiliary pad electrode 193 may be electrically connected.

The auxiliary pad electrode 193 can be formed at the same time as forming the pixel electrode (140 in FIG. 3) provided in each pixel region (P in FIG. 3) located in the display region And is made of a transparent conductive material having corrosion resistance.

Although the auxiliary pad electrode 193 made of a transparent conductive material is formed in contact with the pad electrode 137 in correspondence with each pad electrode 137 in the drawing, The auxiliary pad electrode 193 may be omitted if the pad electrode 137 and the wiring 131 are formed on the same layer, except for the case where the pad electrode 137 and the wiring 131 are formed on different layers.

3) of the thin film transistor (Tr in FIG. 3) provided in the display region (DA in FIG. 3) covers the pad electrode 137, the wiring 131 connected thereto and the wiring 131 It will be appreciated that the cross-sectional structure of the auxiliary pad electrode 193 selectively formed along with the insulating film 190 may be variously changed.

101: array substrate
131: Wiring (connected to the pad electrode)
137: pad electrode

Claims

And the first, second, third, and fourth non-display regions are defined in upper, lower, right, and left sides of the display region,
A plurality of gate wirings and data wirings formed to define a plurality of pixel regions crossing each other in the display region;
A pad portion is defined in at least one non-display region of the first, second, third, and fourth non-display regions, and the pad portion is connected to one end of the gate wiring and the data wiring, A pad electrode
&Lt; / RTI >

The method according to claim 1,
Wherein an insulating film is formed on the gate wiring and the data wiring located between adjacent pad electrodes in the pad electrode arranged in the multi-column structure.

The method according to claim 1,
And an auxiliary pad electrode made of a transparent conductive material is formed on the pad electrode.

The method according to claim 1,
Wherein the pad electrode, the gate wiring, and the data wiring are connected to each other via a link wiring.

5. The method of claim 4,
Wherein an insulating film is formed on the link wiring located between adjacent pad electrodes in the pad electrode arranged in the multi-column structure.

5. The method of claim 4,
And an auxiliary pad electrode made of a transparent conductive material is formed on the pad electrode.

The method according to claim 6,
Wherein the pad electrode and the link wiring are formed in different layers, and the pad electrode and the link wiring are electrically connected by the auxiliary pad electrode.

The method according to claim 1 or 4,
Wherein the multiple columns are comprised of two to four columns.

9. The method of claim 8,
The pad electrode is numbered sequentially from 1 to n (n is an integer greater than m) in the downward direction or left to right direction, and m (m is any one of 2, 3, and 4) Wherein the first to m-th columns are arranged so that when the n is divided by m, the remaining pad electrodes are located.

The method according to claim 1 or 4,
Wherein the pad electrode has a polygonal shape or a circular or elliptic shape.

11. The method of claim 10,
Wherein the wiring connected to the pad electrode has a linear shape or a shape bent or bent along the shape of the pad electrode.

The method according to claim 1 or 4,
A thin film transistor connected to the gate and the data line, and a pixel electrode connected to one electrode of the thin film transistor are formed in each of the pixel regions.