CN111474781B

CN111474781B - Array substrate and display panel

Info

Publication number: CN111474781B
Application number: CN202010284881.XA
Authority: CN
Inventors: 奚苏萍
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2020-04-13
Filing date: 2020-04-13
Publication date: 2022-04-08
Anticipated expiration: 2040-04-13
Also published as: CN111474781A

Abstract

The application provides an array substrate and display panel, array substrate include the display area and set up the GOA circuit region in at least one side of display area, and the display area includes effective display area and sets up the invalid display area in at least one side of effective display area, and invalid display area is located between effective display area and the GOA circuit region. The array substrate further comprises a public electrode wire and a plurality of redundant pixel electrodes, the public electrode wire is arranged in the display area, the redundant pixel electrodes are arranged in the invalid display area, the redundant pixel electrodes are electrically connected with the public electrode wire, and at least one redundant pixel electrode in the same invalid display area serves as the public electrode. The space of display panel has been saved to this application, has satisfied the design demand of narrow frame display product.

Description

Array substrate and display panel

Technical Field

The application relates to the technical field of display, in particular to an array substrate and a display panel.

Background

The GOA (Gate Driver On Array) technology integrates a Gate switching circuit composed of thin film transistors On an Array substrate to realize a driving method of scanning gates row by row. The GOA technology can realize narrow-frame or even frameless design of display products, and is gradually favored by researchers.

In the design of the current GOA display product, a peripheral circuit between a GOA circuit area and a panel effective display area is usually provided with a common electrode, and the public electrode in the area occupies a larger space, so that a frame in a panel non-display area cannot be further compressed, and the design of a narrow-frame product is limited.

Disclosure of Invention

The application provides an array substrate and display panel, has saved display panel's space, has satisfied the design demand of narrow frame display product.

The application provides an array substrate, it includes the display area and sets up the GOA circuit region of at least one side of display area, the display area includes effective display area and sets up the invalid display area of at least one side of effective display area, invalid display area is located effective display area with between the GOA circuit region, array substrate includes:

the public electrode wire is arranged in the display area; and

the redundant pixel electrodes are arranged in the invalid display area and electrically connected with the common electrode wires, and at least one redundant pixel electrode in the same invalid display area is used as a common electrode.

In the array substrate of the present application, in the same invalid display region, the plurality of electrically connected redundant pixel electrodes serve as the common electrode.

In the array substrate, the GOA circuit regions are arranged on two opposite sides of the display region, and the invalid display region is arranged between the effective display region and the two GOA circuit regions;

and the redundant pixel electrodes in the two invalid display areas are both used as the common electrode.

In the array substrate, the redundant pixel electrode is shaped like a plate.

In the array substrate of the present application, the array substrate further includes a plurality of display pixel electrodes, a plurality of first thin film transistors and a plurality of second thin film transistors, the plurality of display pixel electrodes and the plurality of first thin film transistors are disposed in the effective display area, each display pixel electrode corresponds to one of the first thin film transistors one by one, and each display pixel electrode is electrically connected to a drain electrode of the corresponding first thin film transistor;

the plurality of second thin film transistors are arranged in the invalid display area, each redundant pixel electrode corresponds to one second thin film transistor one by one, and each redundant pixel electrode is arranged with the drain electrode of the corresponding second thin film transistor in an insulating mode.

In the array substrate, a plurality of through holes are formed in the part of the array substrate corresponding to the invalid display area, and the public electrode is electrically connected with the part of the public electrode line located in the invalid display area through the through holes.

In the array substrate, the array substrate comprises a substrate, a grid metal layer, a grid insulating layer, an active layer, a source drain metal layer and an interlayer insulating layer which are sequentially arranged;

the redundant pixel electrode and the display pixel electrode are arranged on the interlayer insulating layer at the same layer.

In the array substrate, the gate metal layer includes scan lines, the common electrode lines and the scan lines are disposed on the same layer, and the scan lines are located between adjacent common electrode lines;

the via hole penetrates through the interlayer insulating layer and the gate insulating layer.

The application further provides a display panel, which comprises an array substrate, wherein the array substrate comprises a display area and a GOA circuit area arranged on at least one side of the display area, the display area comprises an effective display area and an ineffective display area arranged on at least one side of the effective display area, and the ineffective display area is positioned between the effective display area and the GOA circuit area;

the array substrate further comprises a common electrode wire and a plurality of redundant pixel electrodes, and the common electrode wire is arranged in the display area; the redundant pixel electrodes are arranged in the invalid display area, the redundant pixel electrodes are electrically connected with the common electrode wires, and at least one redundant pixel electrode in the same invalid display area serves as a first common electrode.

In the display panel of the present application, the display panel further includes a color film substrate, and the color film substrate is arranged opposite to the array substrate;

the color film substrate comprises a second common electrode, the second common electrode is arranged on one side, close to the array substrate, of the color film substrate, and a capacitor is formed between the first common electrode and the part, corresponding to the first common electrode, of the second common electrode.

Compared with the array substrate in the prior art, the array substrate provided by the application takes the redundant pixel electrode in the invalid display area as the common electrode, the common electrode is electrically connected with the common electrode wire in the display area, and the redundant pixel electrode and the drain electrode of the thin film transistor are arranged in an insulating mode, so that the function of the common electrode is realized, and the normal function of the redundant pixel can be ensured. This application has reduced the area occupied of peripheral circuit through shifting the common electrode in the peripheral circuit to invalid display area, has saved the panel space, has effectively reduced display panel's frame to the design demand of narrow frame display product has been satisfied.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic plan view of an array substrate provided in an embodiment of the present application;

fig. 2 is a schematic view of an arrangement structure from a grade of GOA unit to a display area in an array substrate according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a redundant pixel and a display pixel in an array substrate according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram illustrating a film structure of an inactive display area in an array substrate according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

fig. 6 is a schematic plan view illustrating an array substrate in a display panel according to an embodiment of the present disclosure;

fig. 7 is a schematic view of an arrangement structure of a certain grade of GOA units of the array substrate to the display area in the display panel according to the embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

It should be noted that the array substrate in the present application includes a plurality of display pixels and a plurality of redundant pixels. The display pixels are arranged in an array mode, the display pixels are arranged in the effective display area, and each display pixel corresponds to one display pixel electrode one by one. The redundant pixels are arranged in the invalid display area, and each redundant pixel corresponds to a redundant pixel electrode one by one. In the column direction of the array substrate, the redundant pixels in the same inactive display area may be in one, two, or more columns.

It can be understood that the invalid display area in the present application is set for improving the uniformity of the valid display area of the liquid crystal display panel, and the redundant pixels set in the invalid display area are considered for the etching uniformity, and the embodiment of the present application does not specifically limit the specific structure and number of the redundant pixels.

In addition, the structure of the GOA unit in the drawings of the present application is merely an example for convenience of describing the embodiments of the present application, but is not to be construed as a limitation of the present application.

Please refer to fig. 1 to 4. The array substrate 100 provided in the embodiment of the present application includes a display area 10 and a GOA circuit area 11 disposed on at least one side of the display area 10. The display area 10 includes an effective display area 10A and an ineffective display area 10B disposed on at least one side of the effective display area 10A. The inactive display area 10B is located between the active display area 10A and the GOA circuit area 11. The array substrate 100 further includes a common electrode line 12, a plurality of redundant pixel electrodes 13, and a plurality of display pixel electrodes 15. The common electrode lines 12 are disposed in the display area 10. The redundant pixel electrode 13 is disposed in the ineffective display area 10B. The display pixel electrode 15 is disposed in the effective display region 10A. The redundant pixel electrodes 13 are electrically connected to the common electrode line 12, and at least one redundant pixel electrode 13 in the same inactive display area 10B is used as the common electrode 14.

Therefore, the array substrate 100 provided in the embodiment of the present application reduces the occupied area of the peripheral circuit, saves the panel space, and effectively reduces the frame of the display panel by using the redundant pixel electrode 13 in the inactive display area 10B as the common electrode 14, electrically connecting the common electrode 14 with the common electrode line 12 in the display area 10, and transferring the common electrode in the peripheral circuit to the inactive display area 10B, thereby satisfying the design requirement of the narrow-frame display product.

It should be noted that, in the embodiment of the present application, the peripheral circuit region refers to a non-display region (not labeled in the figure) between the GOA circuit region 11 and the display region 10, and the peripheral circuit region is provided with a peripheral circuit, and a specific structure of the peripheral circuit may refer to the prior art, which is not described herein again.

Specifically, the redundant pixel electrode 13 has a plate shape. The redundant pixel electrode 13 may be partially or entirely plate-shaped. In the embodiment of the present application, the redundant pixel electrodes 13 in the same inactive display area 10B are all plate-shaped structures. Compared with the design of a strip structure, the arrangement can reduce the use amount of mask plates when the film layer where the redundant pixel electrode 13 is located is etched, thereby being beneficial to saving the process cost.

In some embodiments, part of the redundant pixel electrode 13 is a plate-shaped structure. The redundant pixel electrode 13 of the partial plate-shaped structure can be used as the common electrode 14, and the redundant pixel electrode 13 which is not used as the common electrode 14 is arranged into a strip shape, namely, the same shape as the display pixel electrode 15 is reserved, and the arrangement can reduce the material consumption of the redundant pixel electrode 13 and is beneficial to saving the process cost.

Further, in the same inactive display area 10B, a plurality of electrically connected redundant pixel electrodes 13 are used as the common electrode 14. The plurality of redundant pixel electrodes 13 in the same inactive display area 10B may be partially used as the common electrode 14, or may be all used as the common electrode 14, and the redundant pixel electrodes 13 used as the common electrode 14 are electrically connected to each other.

In the embodiment of the present application, the redundant pixel electrodes 13 located in the same inactive display area 10B are all used as the common electrode 14. The arrangement can save the space of the panel, ensure the uniformity of the common electrode 14 and is beneficial to improving the stability of the common electrode 14. In addition, in the direction parallel to the plane of the array substrate 100, since the surface area of the redundant pixel electrode 13 is larger than the surface area of the common electrode 14 in the peripheral circuit region, the above arrangement is equivalent to increase the surface area of the common electrode 14, and further, the capacitance formed between the common electrode 14 and the transparent electrode on the panel color film substrate side can be increased, thereby further improving the stability of the common electrode 14.

Further, in the embodiment of the present application, the GOA circuit regions 11 are disposed on two opposite sides of the display region 10, and the inactive display region 10B is disposed between the active display region 10A and the two GOA circuit regions 11. The redundant pixel electrodes 13 in both of the inactive display areas 10B serve as common electrodes 14.

The common electrodes 14 of the peripheral circuit regions on the two sides are transferred to the invalid display region 10B, so that the panel space is further saved, and the design requirement of a narrow-frame product is met to the greatest extent. Meanwhile, the arrangement can further increase the surface area of the common electrode 14, thereby further improving the stability of the common electrode 14.

It should be noted that the array substrate 100 in the present application further includes a GOA circuit (not shown in the drawings), where the GOA circuit is disposed in the GOA circuit region 11, and the GOA circuit includes multiple stages of cascaded GOA units 111. Fig. 2 only shows a layout structure of a GOA unit 111 to the display area 10, wherein the GOA unit 111 includes a driving transistor 1111, a signal trace 1112, and a plurality of metal vias 1113. The signal trace 1112 is used for transmitting a scan signal to the scan line 181. The metal hole 1113 is used to electrically connect the signal trace 1112 and the scan line 181. In addition, the GOA unit 111 further includes other circuit structures (not shown in the drawings), and the specific structures of the GOA circuit and the GOA unit 111 can refer to the prior art, which is not described herein again.

Please continue to refer to fig. 3. In the embodiment of the present application, the array substrate 100 further includes a plurality of first thin film transistors 15A and a plurality of second thin film transistors 13A. A plurality of first thin film transistors 15A are disposed in the effective display area 10A. Each display pixel electrode 15 corresponds to one of the first thin film transistors 15A, and each display pixel electrode 15 is electrically connected to the drain 151A of the corresponding first thin film transistor 15A. A plurality of second thin film transistors 13A are disposed in the inactive display area 10B. Each of the redundant pixel electrodes 13 corresponds to one of the second tfts 13A, and each of the redundant pixel electrodes 13 is isolated from the drain 131A of the corresponding second tft 13A.

Please refer to fig. 3 and fig. 4. Further, a plurality of vias 16 are formed in a portion of the array substrate 100 corresponding to the inactive display area 10B. The common electrode 14 is electrically connected to the portion of the common electrode line 12 in the inactive display area 10B through the via hole 16.

Specifically, the array substrate 100 includes a substrate 17, a gate metal layer 18, a gate insulating layer 19, an active layer 20, a source/drain metal layer 21, and an interlayer insulating layer 22, which are sequentially disposed. The via hole 16 penetrates the interlayer insulating layer 22, the active layer 20, and the gate insulating layer 23.

The gate metal layer 18 includes a scan line 181 and a gate 182. The common electrode lines 12 and the scan lines 181 are disposed on the same layer, and the scan lines 181 are located between adjacent common electrode lines 12.

It is understood that the source-drain metal layer 21 includes a source electrode 21A and a drain electrode 21B. The gate 182, the active layer 20, the source 21A, and the drain 21B (151A) in the active display region 10A form a first thin film transistor 15A, and the gate 182, the active layer 20, the source 21A, and the drain 21B (131A) in the inactive display region 10B form a second thin film transistor 13A. The detailed structure of the first thin film transistor 15A and the second thin film transistor 13A can be referred to the prior art, and will not be described herein.

In the embodiment of the present application, the redundant pixel electrode 13 and the display pixel electrode 15 are disposed on the interlayer insulating layer 22 at the same layer. Therefore, when the redundant pixel electrode 13 is used as the common electrode 14, only the redundant pixel electrode 13 with the plate-shaped structure needs to be retained in the original process, and no new process needs to be added. In addition, the present embodiment omits the original process of the common electrode in the peripheral circuit region, thereby saving the panel space and achieving the purpose of simplifying the process.

According to the array substrate 100 provided by the embodiment of the application, the redundant pixel electrode 13 in the invalid display area 10B is used as the common electrode 14, the common electrode 14 is electrically connected with the common electrode line 12 in the display area 10, and the redundant pixel electrode 13 and the drain electrode of the thin film transistor are arranged in an insulating manner, so that the function of the common electrode 14 is realized, and the normal function of the redundant pixel can be ensured. The public electrode in the peripheral circuit is transferred to the invalid display area 10B, so that the occupied area of the peripheral circuit is reduced, the panel space is saved, the frame of the display panel is effectively reduced, and the design requirement of narrow-frame display products is met. In addition, the capacitance between the common electrode 14 and the transparent electrode on the panel color film substrate side can be increased, and the stability of the common electrode 14 can be further improved.

Please refer to fig. 5 to 7. The display panel 200 provided in the embodiment of the present application includes an array substrate 20, a color filter substrate 21, and a liquid crystal 22 disposed between the array substrate 20 and the color filter substrate 21. The array substrate 20 includes a display area 201 and a GOA circuit area 202 disposed on at least one side of the display area 201. The display area 201 includes an effective display area 201A and an ineffective display area 201B disposed on at least one side of the effective display area 201A. The inactive display area 201B is located between the active display area 201A and the GOA circuit area 202. The array substrate 20 further includes a common electrode line 203 and a plurality of redundant pixel electrodes 204. The common electrode line 203 is disposed in the display area 201. The redundant pixel electrode 204 is disposed in the ineffective display area 201B. The redundant pixel electrodes 204 are electrically connected to the common electrode line 203, and at least one of the redundant pixel electrodes 204 in the same inactive display area 201B is used as a first common electrode 205.

Therefore, in the display panel 200 provided in the embodiment of the present application, the redundant pixel electrode 204 in the invalid display area 201B is used as the first common electrode 205, the first common electrode 205 is electrically connected to the common electrode line 203 in the display area 201, and the common electrode in the peripheral circuit is transferred to the invalid display area 201B, so that the occupied area of the peripheral circuit is reduced, the panel space is saved, the frame of the display panel is effectively reduced, and the design requirement of a narrow-frame display product is met.

It should be noted that the peripheral circuit region mentioned in the embodiment of the present application refers to a non-display region (not labeled in the figure) between the GOA circuit region 202 and the display region 201, and the peripheral circuit region is provided with a peripheral circuit, and a specific structure of the peripheral circuit may refer to the prior art, which is not described herein again.

Further, the color filter substrate 21 includes a substrate 211 and a second common electrode 212. The second common electrode 212 is disposed on one side of the color filter substrate 21 close to the array substrate 20, and a capacitor is formed between a portion of the second common electrode 212 corresponding to the first common electrode 205 and the first common electrode 205.

Because the space of the peripheral circuit area is limited, when the first common electrode 205 is disposed in the peripheral circuit area, the first common electrode 205 occupies a limited space, so that the capacitance formed between the first common electrode 205 and the second common electrode 212 is small, and further the RC loading in the panel is small. In this embodiment, the first common electrode 205 is transferred to the invalid display area 201B, and the redundant pixel electrode 204 is used as the first common electrode 205, because the occupied space of the invalid display area 201B is larger than that of the peripheral circuit area, the occupied space of the first common electrode 205 can be increased, and further, the capacitance formed between the first common electrode 205 and the second common electrode 212 is increased, so that the stability of the first common electrode 205 is improved, and the panel performance is improved.

It should be noted that, the specific structure and the corresponding beneficial effects of the array substrate 20 in the present embodiment can refer to the description of the structure of the array substrate 100 in the foregoing embodiment, and are not repeated herein.

In the display panel 200 provided in the embodiment of the application, the redundant pixel electrode 204 in the invalid display area 201B is used as the first common electrode 205, the first common electrode 205 is electrically connected to the common electrode line 203 in the display area 201, and the redundant pixel electrode 204 is insulated from the drain of the thin film transistor, so that the function of the first common electrode 205 is realized, and the normal function of the redundant pixel can be ensured. This application has reduced the area occupied of peripheral circuit through shifting the common electrode in the peripheral circuit to invalid display area 201B, has saved the panel space, has effectively reduced display panel's frame to the design demand of narrow frame display product has been satisfied. In addition, the capacitance between the first common electrode 205 and the second common electrode 212 can be increased by the arrangement, so that the stability of the first common electrode 205 is improved, and the performance of the panel is improved.

Compared with the array substrate in the prior art, the array substrate provided by the application has the advantages that the redundant pixel electrode in the invalid display area is used as the common electrode, and the common electrode is electrically connected with the common electrode wire in the display area, so that the normal function of the redundant pixel is ensured, and meanwhile, the function of the common electrode is ensured. This application has reduced the area occupied of peripheral circuit through shifting the common electrode in the peripheral circuit to invalid display area, has saved the panel space, has effectively reduced display panel's frame to the design demand of narrow frame display product has been satisfied.

The foregoing provides a detailed description of embodiments of the present application, and the principles and embodiments of the present application have been described herein using specific examples, which are presented solely to aid in the understanding of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. An array substrate, comprising a display area and a GOA circuit area arranged on at least one side of the display area, wherein the display area comprises an effective display area and an ineffective display area arranged on at least one side of the effective display area, the ineffective display area is arranged between the effective display area and the GOA circuit area, and the array substrate comprises:

the public electrode wire is arranged in the display area; and

the redundant pixel electrodes are arranged in the invalid display area and electrically connected with the common electrode line, at least one redundant pixel electrode in the same invalid display area is multiplexed into a common electrode, the redundant pixel electrodes extend along the edge of the effective display area, the redundant pixel electrodes multiplexed into the common electrode are plate-shaped electrodes without slits, and the common electrode is omitted between the GOA circuit area and the invalid display area.

2. The array substrate of claim 1, wherein a plurality of the electrically connected redundant pixel electrodes are used as the common electrode in the same inactive display area.

3. The array substrate as claimed in claim 2, wherein the GOA circuit regions are disposed on opposite sides of the display region, and the inactive display region is disposed between the active display region and each of the two GOA circuit regions;

4. The array substrate of claim 1, further comprising a plurality of display pixel electrodes, a plurality of first thin film transistors and a plurality of second thin film transistors, wherein the plurality of display pixel electrodes and the plurality of first thin film transistors are disposed in the active display area, each display pixel electrode corresponds to one first thin film transistor, and each display pixel electrode is electrically connected to a drain of the corresponding first thin film transistor;

5. The array substrate of claim 4, wherein a plurality of via holes are formed in a portion of the array substrate corresponding to the inactive display area, and the common electrode is electrically connected to a portion of the common electrode line in the inactive display area through the via holes.

6. The array substrate according to claim 5, wherein the array substrate comprises a substrate, a gate metal layer, a gate insulating layer, an active layer, a source drain metal layer and an interlayer insulating layer which are arranged in sequence;

7. The array substrate of claim 6, wherein the gate metal layer comprises scan lines, the common electrode lines and the scan lines are disposed in the same layer, and the scan lines are located between the adjacent common electrode lines;

8. A display panel comprising an array substrate, the array substrate comprising a display area and a GOA circuit area arranged at least one side of the display area, the display area comprising an active display area and an inactive display area arranged at least one side of the active display area, the inactive display area being located between the active display area and the GOA circuit area,

the array substrate further comprises a common electrode wire and a plurality of redundant pixel electrodes, and the common electrode wire is arranged in the display area; the redundant pixel electrodes are arranged in the invalid display area and electrically connected with the common electrode wires, at least one redundant pixel electrode in the same invalid display area is multiplexed into a first common electrode, the redundant pixel electrodes extend along the edge of the valid display area, the redundant pixel electrodes multiplexed into the first common electrode are plate-shaped electrodes without slits, and the common electrode is omitted between the GOA circuit area and the invalid display area.

9. The display panel according to claim 8, further comprising a color filter substrate, wherein the color filter substrate is disposed opposite to the array substrate;