CN110887984A - Digital oscilloscope supporting eye pattern reconstruction - Google Patents
Digital oscilloscope supporting eye pattern reconstruction Download PDFInfo
- Publication number
- CN110887984A CN110887984A CN201911233785.6A CN201911233785A CN110887984A CN 110887984 A CN110887984 A CN 110887984A CN 201911233785 A CN201911233785 A CN 201911233785A CN 110887984 A CN110887984 A CN 110887984A
- Authority
- CN
- China
- Prior art keywords
- data
- waveform
- digital
- circuit
- display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
Abstract
A digital oscilloscope supporting eye pattern reconstruction mainly comprises a logic processing circuit, a central processing unit, a memory and a display; the memory is used for storing the collected data of the input signal; the logic processing circuit is used for constructing a digital waveform according to the acquired data, performing waveform search on the digital waveform to obtain statistical information of each edge event in the digital waveform, sending the statistical information to the central processing unit to obtain feedback configuration information, and performing superposition display by using display positions of each bit waveform configured in the configuration information to obtain an eye pattern corresponding to the input signal; the central processing unit is used for recovering clock data according to the statistical information of each edge event, configuring the display position of each bit waveform, forming configuration information and feeding the configuration information back to the logic processing circuit. According to the technical scheme, the logic processing circuit and the central processing unit can respectively undertake a part of operation processing tasks, and the improvement of the efficiency of eye diagram reconstruction is facilitated.
Description
Technical Field
The invention relates to the technical field of oscilloscopes, in particular to a digital oscilloscope supporting eye pattern reconstruction.
Background
The digital storage type oscilloscope is one of main instruments for testing and analyzing signals, and has wide application in various industries such as information communication, high-energy physics, medical electronics and the like. The digital storage oscilloscope mainly works on the principle that a signal conditioning circuit regulates an input signal into the optimal input range of an analog-to-digital converter (ADC), the ADC collects and quantizes the analog input signal, and a Field Programmable Gate Array (FPGA) controls a memory to access data according to a trigger condition. Due to the limitation of ADC sampling rate and other factors, the capacity of information that can be observed by the digital storage oscilloscope in the real-time sampling mode is very limited, and it is usually necessary to observe rich information contained in the digital waveform by using an eye diagram reconstruction technique.
The eye diagram is a display diagram formed by overlapping each symbol waveform obtained by scanning with an oscilloscope by using afterglow action. In general, the eye diagram contains rich information, the influence of intersymbol interference and noise can be observed from the eye diagram, the integral characteristics of the digital signal are reflected, and the quality degree of the system can be estimated, so that the eye diagram analysis is the core of the signal integrity analysis of the high-speed interconnection system. In addition, the characteristic of the receiving filter can be adjusted by the graph so as to reduce intersymbol interference and improve the transmission performance of the system.
Currently, eye diagram technology is mainly used for representing and analyzing high-speed digital signals, and key parameters in signal electrical quality can be rapidly determined through eye diagrams, so that hidden problems in signals and systems can be discovered. For example, as shown in fig. 1, in an ideal state without interference, the waveform of each bit of a segment of digital signal (i.e. each fluctuation interval T)bitInner waveform) with amplitude represented on the Y-axis and time represented on the X-axis, an eye diagram of the segment of digital signal can be simply constructed, the above construction is repeated for many samples of the waveform, and the resulting diagram can represent the average statistical value of the signal, which is similar to one eye, thereby forming the eye diagram. In addition to the time domain waveform display being clearly visible, the ideal eye diagram illustrated in fig. 1 can provide less additional information, however, in the real world, the high-speed digital signal has serious defects of attenuation, noise, crosstalk and the like, and the constructed eye diagram will present the graph shown in fig. 2, which is closer to the shape of the eye.
The existing digital oscilloscope mainly adopts a CPU to realize the eye pattern reconstruction function, high-speed digital signals are sent to a digital sampling chip after passing through an analog-to-digital converter, the digital sampling chip stores received data into an external memory, then the CPU reads and processes the acquired data stored in the external memory module to reconstruct an eye pattern, and the eye pattern is displayed on an LCD screen. However, there are some disadvantages in the existing technical solutions, and serial processing of the sampled data is required in the process of reconstructing the high-speed digital eye diagram by using the CPU, which increases the time for processing the sampled data each time and reduces the efficiency of eye diagram reconstruction; an external storage chip externally connected with the CPU is used for storing the sampling data, storing the processing result of the data and maintaining the running of CPU software, so that the space for storing the sampling data is reduced, and as much data as possible cannot be acquired every time for clock recovery.
Disclosure of Invention
The invention mainly solves the technical problem of how to reasonably set a unit framework for data processing in a digital oscilloscope so as to reduce the processing load of a single processing unit and quickly recover clock data in eye pattern reconstruction, thereby improving the efficiency of eye pattern reconstruction. In order to solve the technical problem, the application provides a digital oscilloscope and a storage medium supporting eye pattern reconstruction.
According to a first aspect, there is provided in one embodiment a digital oscilloscope supporting eye diagram reconstruction, comprising logic processing circuitry, a central processing unit, a memory, and a display; the memory is used for storing the collected data of the input signal; the logic processing circuit is in communication connection with the memory and is used for constructing digital waveforms according to the acquired data, searching the digital waveforms to obtain statistical information of each edge event in the digital waveforms, sending the statistical information to the central processing unit to obtain feedback configuration information, and performing afterglow display on each bit waveform one by using the display position of each bit waveform configured in the configuration information; the digital waveform comprises a plurality of edge events generated by rising edges and/or falling edges, and bit waveforms are formed between adjacent edge events; the central processing unit is in communication connection with the logic processing circuit and is used for performing clock data recovery according to the statistical information of each edge event, configuring the display position of each bit waveform to form the configuration information and feeding the configuration information back to the logic processing circuit; and the display is in communication connection with the logic processing circuit and is used for obtaining an eye pattern corresponding to the input signal by superposition display under afterglow display.
The logic processing circuit comprises a data processing circuit, a waveform searching circuit, a waveform navigation circuit and a data display circuit; the data processing circuit is in communication connection with the memory and is used for acquiring the acquired data from the memory, interpolating the acquired data according to a preset interpolation mode and an interpolation multiple to obtain sample interpolation data consisting of each data point in the acquired data and each inserted data point, and constructing a digital waveform by using the sample interpolation data; each data point in the sample interpolation data has a corresponding amplitude value and a continuous distribution serial number; the waveform searching circuit is in communication connection with the data processing circuit and the central processing unit respectively, and is used for comparing each data point in the sample insertion data with a preset searching level value to obtain a searching comparison result, detecting that the edge events are generated when a rising edge and/or a falling edge is formed in the searching comparison result, recording the event sequence, the event number and the distribution position of each edge event in the digital waveform to form statistical information of each edge event, and sending the statistical information to the central processing unit; the waveform navigation circuit is in communication connection with the central processing unit and the data processing circuit respectively, and is used for obtaining the display position of each bit waveform according to the configuration information fed back by the central processing unit, guiding the logic processing circuit to re-read the acquired data from the memory, and reconstructing a digital waveform; and the data display circuit is in communication connection with the data processing circuit and is used for performing afterglow display on each bit waveform one by utilizing the reconstructed digital waveform.
The logic processing circuit also comprises a digital trigger circuit and a data acquisition circuit; the digital trigger circuit is used for acquiring sampling data of an input signal, comparing each data point in the sampling data with a preset trigger level value respectively to obtain a digital comparison result, and generating a trigger signal when detecting that a rising edge and/or a falling edge are formed in the digital comparison result; the data acquisition circuit is in signal connection with the digital trigger circuit and is used for storing a frame of data consisting of the trigger signal and corresponding data points before and after the trigger signal to the memory when the digital trigger circuit generates the trigger signal so as to obtain the acquisition data of the input signal.
The digital oscilloscope further comprises an analog channel, wherein the analog channel comprises an input end and an output end, and the output end is in communication connection with the digital trigger circuit and the data acquisition circuit respectively; the analog channel is used for carrying out channel coupling and amplification processing on an input signal introduced into the input end, and carrying out analog-to-digital conversion on the amplified signal in a plurality of continuous clock cycles to obtain the sampling data; and transmitting the sampled data to the data trigger circuit and the data acquisition circuit using the output.
The data acquisition circuit stores, for each generated trigger signal, a frame of data composed of data points sampled in a clock cycle corresponding to the trigger signal and data points sampled in a plurality of clock cycles before and after the clock cycle into the memory, so as to constitute the acquired data of the input signal using the stored data points in the memory.
The data display circuit is also in communication connection with the display and is further used for controlling the display to enter an afterglow display mode, ideal sampling points of the bit waveforms are used as display positions, the bit waveforms are played one by one on the display, and graphics played in a superposition mode are used as eye diagrams corresponding to the input signals.
The central processing unit comprises a setting module which is in communication connection with the display and is used for forming a setting window on the display, responding to input information of a user on the setting window, and controlling and setting an interpolation mode and an interpolation multiple corresponding to the data processing circuit in the logic processing circuit, a search level value corresponding to the waveform search circuit and a trigger level value corresponding to the digital trigger circuit.
The central processing unit is respectively in communication connection with the waveform searching circuit and the waveform navigation circuit in the logic processing circuit; the central processing unit acquires the statistical information of each edge event from the waveform searching circuit, and is used for determining the number of the bit waveforms in the digital waveform according to the statistical information of each edge event; and the average period is used for calculating the average period of the bit waveforms in the digital waveforms according to the number of the bit waveforms, and the clock period of the digital waveforms is obtained by recovering the average period, wherein the average period is the average value of the number of data points in each bit waveform; the central processing unit is further configured to calculate an ideal sampling point of each bit waveform according to the recovered clock period, configure a display position of the bit waveform with the ideal sampling point, form the configuration information according to the display position of each bit waveform, and feed the configuration information back to the waveform navigation circuit.
When the central processing unit determines the number of the bit waveforms in the digital waveform according to the statistical information of each edge event, the method comprises the following steps: comparing the statistical information of each edge event to obtain a reference period of the bit waveform, wherein the reference period is a minor value of the number of data points in each bit waveform; and calculating the number of the bit waveforms according to the displacement deviation of the second edge event and the last edge event in each edge event and the reference period.
According to a second aspect, an embodiment provides a digital oscilloscope, wherein the logic processing circuit adopts an FPGA, and the central processing unit adopts a CPU.
The beneficial effect of this application is:
the digital oscilloscope supporting eye pattern reconstruction according to the embodiment mainly comprises a logic processing circuit, a central processing unit, a memory and a display; the memory is used for storing the collected data of the input signal; the logic processing circuit is used for constructing a digital waveform according to the acquired data, carrying out waveform search on the digital waveform to obtain statistical information of each edge event in the digital waveform, sending the statistical information to the central processing unit to obtain feedback configuration information, and utilizing the display position of each bit waveform configured in the configuration information to be superposed and displayed to obtain an eye pattern corresponding to the input signal, wherein the digital waveform comprises a plurality of edge events generated by rising edges and/or falling edges, and bit waveforms are formed between adjacent edge events; the central processing unit is used for recovering clock data according to the statistical information of each edge event, configuring the display position of each bit waveform, forming configuration information and feeding the configuration information back to the logic processing circuit; and the display is in communication connection with the logic processing circuit and is used for obtaining an eye pattern corresponding to the input signal by superposition display under afterglow display. On the first hand, the technical scheme of the application adopts a hardware framework combining a logic processing circuit, a central processing unit and a memory to realize the eye pattern reconstruction function of the digital oscilloscope, so that the logic processing circuit and the central processing unit can respectively undertake a part of operation processing tasks, and the improvement of the eye pattern reconstruction efficiency is facilitated; in the second aspect, when executing the operation processing task of eye diagram reconstruction, the interaction of the processing result is mainly realized between the logic processing circuit and the central processing unit, the information storage amount of the processing result by the memory is reduced, and the storage requirement of the acquired data is ensured by saving space in the memory, so that the operation of clock data recovery is realized by using more sampling data as much as possible, and the accuracy of clock data recovery is improved; in the technical scheme of the application, the functions of waveform construction, waveform search and waveform playing of digital waveforms are mainly realized by means of a logic processing circuit, and the functions of clock data recovery and bit waveform display position configuration are realized by means of a central processing unit, so that the situation that the central processing unit is used for bearing all data processing tasks in the conventional oscilloscope is avoided, the operation burden of the central processing unit is effectively reduced, and the processing performance of the central processing unit on other tasks is favorably enhanced; in the fourth aspect, the logic processing circuit performs waveform search on the digital waveform to obtain statistical information of each edge event in the digital waveform, so that the central processing unit can recover clock data according to the statistical information to achieve the purpose of configuring the display position of each bit waveform; in the fifth aspect, when the central processing unit recovers the clock data, the average period of the bit waveforms in the digital waveforms is calculated according to the number of the bit waveforms, and the clock period of the digital waveforms is recovered by utilizing the average period, so that the ideal sampling point of each bit waveform is calculated to configure the display position of the bit waveform, the clock data recovery process is more accurate and faster, and the high-efficiency data processing requirement is realized; in the sixth aspect, when the logic processing circuit independently searches the waveforms of the digital waveforms, the collected data are preprocessed in a parallel processing mode, so that the processing time of each frame of data is effectively reduced, and the overall efficiency of eye pattern reconstruction is improved.
Drawings
FIG. 1 is a diagram of a high speed digital signal and its eye diagram formation in a conventional oscilloscope;
FIG. 2 is a diagram of a high-speed digital signal with interference and an eye diagram formed by the high-speed digital signal in a conventional oscilloscope;
FIG. 3 is a schematic diagram of the overall structure of a digital oscilloscope according to the present application;
fig. 4 is a detailed structural diagram of a digital oscilloscope in the present application.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the elements as such, e.g., "first", "second", etc., herein is merely used to distinguish between the objects described and not to have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
Referring to fig. 3, the present embodiment discloses a digital oscilloscope supporting eye diagram reconstruction, which includes a logic processing circuit 2, a central processing unit 3, a memory 1 and a display 5, which are described below.
The memory 1 is used for storing the acquired data of the input signal. The memory 1 is a memory component for storing programs and various data information, and can be divided into a main memory (main memory or internal memory for short) and an auxiliary memory (auxiliary memory or external memory for short), which is not limited in application. It should be noted that the collected data stored in the memory 1 may be composed of a plurality of data points, and the fluctuation state of the amplitude when the data points are distributed according to a sequence represents the state of the digital waveform.
The logic processing circuit 2 is in communication connection with the memory 1 and is used for constructing a digital waveform according to the acquired data, performing waveform search on the digital waveform and obtaining statistical information of each edge event in the digital waveform; and the logic processing circuit 2 sends the statistical information to the central processing unit 3 to obtain the fed back configuration information, and afterglow display is performed on each bit waveform one by using the display position of each bit waveform configured in the configuration information. Digital waveforms referred to herein include a plurality of edge events generated by rising and/or falling edges, with a bit waveform formed between adjacent edge events.
The central processing unit 3 is in communication connection with the logic processing circuit 2, and is configured to perform clock data recovery according to the statistical information of each edge event, configure the display position of each bit waveform, form configuration information, and feed back the configuration information to the logic processing circuit 2.
It should be noted that the purpose of the central processing unit 3 for clock data recovery is to obtain the true number of bits in the collected data and the ideal sampling point of each bit, that is, the middle position information of each bit, and to regard the ideal sampling point as the display position, thereby facilitating the start of the subsequent waveform playing function. In addition, after the clock data is recovered, an ideal sampling point of each bit waveform can be calculated according to the recovered clock period, so that the ideal sampling point is configured to the display position of the bit waveform.
The display 5 is in communication connection with the logic processing circuit 2 and is used for obtaining an eye pattern corresponding to the input signal by superposition display in the afterglow display mode controlled by the logic processing circuit 2.
It should be noted that the eye pattern can be simply understood as a signal display pattern having a shape similar to an eye, and in essence, the eye pattern is a result of cumulatively displaying bits of the acquired serial signal in an afterglow manner, and the shape of the superimposed pattern looks similar to an eye, and is referred to as an eye pattern. The shapes of the eye patterns are various, and the quality of the signal can be judged quickly through the shape characteristics of the eye patterns. The eye diagram is a graph obtained by superposing waveforms of a plurality of bits, and the eye diagram can be seen as follows: 1 level and 0 level of the digital signal, whether the signal has overshoot and ringing or not, whether the jitter is large or not, the signal-to-noise ratio of an eye pattern and whether the rising/falling time is symmetrical or not (duty ratio). The eye diagram reflects the signal quality in the case of large data volume, and can describe the quality and performance of high-speed digital signals most intuitively. In the embodiment, the logic processing circuit 2 constructs the eye pattern by using a method of "synchronous triggering + superimposed displaying", wherein the synchronous triggering is a key for accurately measuring the eye pattern, and the superimposed displaying is continuously accumulated and displayed by using an infinite afterglow method. In short, a frame of data is collected once per synchronous trigger, and then the bit waveforms are respectively superposed. Each time the overlay is displayed, a UI is added to the eye pattern, data of each UI is arranged relative to the display position of the bit waveform, and each overlay is added with a bit on the eye pattern. It should be noted that a frame of data mentioned in this application is data sampled within a period of time (or a plurality of clock cycles), and is generally the amount of data required for a refresh of an on-screen signal waveform, where a frame of data may be formed with many rising edges and falling edges, so that a corresponding digital waveform includes many edge events and many bit waveforms.
In order to make the technical solution of the present application clearly understood by the skilled person, the following will specifically describe the hardware architecture of the logic processing circuit 2 and the central processing unit 3 and the implemented functions.
In the present embodiment, referring to fig. 4, the logic processing circuit 2 includes a data processing circuit 21, a waveform search circuit 22, a waveform navigation circuit 23, and a data display circuit 24, which are respectively explained as follows.
The data processing circuit 21 is in communication connection with the memory 1, and is configured to acquire the acquired data from the memory 1, interpolate the acquired data according to a preset interpolation mode and an interpolation multiple, obtain sample interpolation data composed of each data point in the acquired data and each inserted data point, and construct a digital waveform by using the sample interpolation data; each data point in the sample interpolation data has a corresponding amplitude and a continuous distribution index.
When the data processing circuit 21 obtains interpolation data by interpolation, a conventional high-speed digital signal interpolation method can be used. High-speed digital signal interpolation is a common technical means of oscilloscopes, and is mainly divided into a linear interpolation method and a sinusoidal interpolation method. The distribution density of data points in the acquired data within a unit time can be increased through interpolation, and accurate positioning of each data point is facilitated. In addition, after the data points in the sample interpolation data are sequentially arranged according to the distribution serial numbers, the amplitude of each data point shows continuous fluctuation change, and therefore a digital waveform can be formed.
The waveform searching circuit 22 is communicatively connected to the data processing circuit 21 and the central processing unit 3, and configured to compare each data point in the sample-inserted data with a preset search level value to obtain a search comparison result, detect that an edge event is generated when a rising edge and/or a falling edge is formed in the search comparison result, record an event sequence, an event number, and a distribution position in a digital waveform of each edge event, form statistical information of each edge event, and send the statistical information to the central processing unit 3.
It should be noted that each data point in the interpolated data has its own amplitude, which is represented by a voltage value, so that the waveform search circuit 22 can use the amplitude to compare with a preset search level value. If the amplitudes of the plurality of consecutive data points decrease sequentially and decrease below the search level value, indicating that the data are located on the falling edge of the digital waveform; if the amplitudes of consecutive data points increase sequentially and above the search level, it indicates that the data points are on the rising edge of the waveform.
In addition, the user can set the mode of detecting the search comparison result to be edge triggering through the user interface, and the rising edge is effective, the falling edge is effective or effective at the same time, and preferably set to be effective at the same time. For example, if waveform search circuit 22 detects a sequential decrease in the amplitude of a plurality of consecutive data points, and below a search level value, an edge event is generated; meanwhile, if the waveform searching circuit 22 detects that the amplitudes of a plurality of consecutive data points increase sequentially and increase above the search level value, an edge event is generated. The skilled person will appreciate that when each edge event is generated, the occurrence number of the edge event can be recorded by a counter; the distribution position of the edge event can be known by recording the sequence number of the data point which causes the edge event; after counting one frame of collected data, the total number of edge events in the frame of collected data can be known; thereby forming statistics for each edge event.
The waveform navigation circuit 23 is in communication connection with the central processing unit 3 and the data processing circuit 21, respectively, and is configured to obtain a display position of each bit waveform according to configuration information fed back by the central processing unit 3, and guide the logic processing circuit 21 to re-read the acquired data from the memory 1, and reconstruct the digital waveform.
The data display circuit 24 is communicatively connected to the data processing circuit 21, and is configured to perform persistence display on each bit waveform one by using the reconstructed digital waveform, so as to superimpose an eye pattern corresponding to the input signal on the display 5.
Further, referring to fig. 4, the logic processing circuit 2 further includes a digital trigger circuit 25 and a data acquisition circuit 26, which are respectively described below.
The digital trigger circuit 25 is configured to obtain sampling data of the input signal, compare each data point in the sampling data with a preset trigger level value, respectively, obtain a digital comparison result, and generate a trigger signal when a rising edge and/or a falling edge is formed in the digital comparison result.
It will be readily appreciated that the user may set the manner of detecting the digital comparison result to be edge triggered by the user interface, specifying that the rising edge is active, the falling edge is active, or both, preferably set to be active at the same time. For example, if digital trigger circuit 25 detects that the amplitudes of a plurality of consecutive data points decrease sequentially and decrease below the trigger level value, a trigger signal is generated, thus implementing falling edge triggering; meanwhile, if the digital trigger circuit 25 detects that the amplitudes of a plurality of consecutive data points increase sequentially and increase above the trigger level value, a trigger signal is generated, so that the rising edge trigger is realized.
The data acquisition circuit 26 is in signal connection with the digital trigger circuit 25, and is configured to store a frame of data composed of the trigger signal and corresponding data points before and after the trigger signal into the memory 1 when the digital trigger circuit 25 generates the trigger signal, so as to obtain the acquired data of the input signal.
In one embodiment, for each generated trigger signal, the data acquisition circuit 26 stores a frame of data formed by data points sampled in a clock period corresponding to the trigger signal and data points sampled in a plurality of clock periods before and after the clock period, that is, stores a frame of data formed by data points in the clock period in which the trigger signal is located and in the plurality of clock periods before and after the trigger signal, and stores the frame of data in the memory 1, so that the stored data points can be used to form the acquired data of the input signal.
In this implementation, referring to fig. 3 and 4, the digital oscilloscope in the present application further includes an analog channel 4, where the analog channel 4 includes an input end and an output end (the input end and the output end are not labeled in the figure), the output end is in communication connection with the digital trigger circuit 25 and the data acquisition circuit 26, respectively, and the input end is used for connecting a signal source and introducing an input signal.
The analog channel 4 is used for carrying out channel coupling and amplification processing on an input signal introduced into an input end, and carrying out analog-to-digital conversion on the amplified signal in a plurality of continuous clock cycles to obtain sampling data; and the analog channel 4 is used for transmitting the sampling data to the data trigger circuit and the data acquisition circuit by using the output end. It is easy to understand that the analog channel 4 can make the processed digital waveform displayed in the middle of the screen by adjusting the vertical shift and vertical offset of the channel coupling and amplifying circuit, for example, the display area of the digital waveform can be about 3/4 channel coupling and amplifying processing effect of the screen. In addition, the channel coupling and amplification processing can also play a role in noise filtering on the input signal, determine the way in which the signal enters the channel amplifier of the oscilloscope, namely determine the signal component entering the input channel, and therefore can filter out the unwanted component in the signal by setting the channel coupling.
Further, referring to fig. 4, the data acquisition circuit 26 stores, for each trigger signal generated by the digital trigger circuit 25, one frame data composed of the respective data points sampled in the clock cycle corresponding to the trigger signal and the respective data points sampled in a plurality of clock cycles before and after the clock cycle into the value memory 1 to constitute the acquired data of the input signal using the stored respective data points in the memory 1.
It should be noted that a clock cycle is defined as the reciprocal of a clock frequency, and is the most basic and smallest unit of time in a computer. In one clock cycle, the CPU only completes one of the most basic actions. A smaller clock period generally means a higher operating frequency. The ADC conversion is to input an analog signal quantity and convert the signal quantity into a digital quantity. Reading digital quantity must be completed by one channel after the conversion is completed, which is called sampling period. In general, the sampling period is the transition time + the read time, where the transition time is the sampling time + several clock cycles.
In the present embodiment, referring to fig. 3 and 4, the data display circuit 24 in the logic processing circuit 2 is communicatively connected to the display 5. Then, the data display circuit 24 is further configured to control the display 5 to enter the persistence display mode, play the bit waveforms one by one on the display 5 with the ideal sampling points of the bit waveforms as display positions, and use the graphics played in the superposition as the eye diagram corresponding to the input signal.
It should be noted that it is a common function of the present digital oscilloscope that the data display circuit 24 controls the display 5 to set and enter the afterglow display mode, in which the digital waveform can stay on the screen for a certain period of time and then gradually disappear, so as to prevent accidental signals or signals from being missed by a person when the person blinks. Typically, a digital oscilloscope may update a display with display data for a new waveform, but does not immediately erase the previous waveform, which would be displayed at a reduced brightness, and the new waveform would be displayed at a normal color and brightness.
It should be noted that, for each bit waveform, under the condition that the data display circuit 24 obtains an ideal sampling point thereof, the position of the ideal sampling point is taken as the middle position of the waveform playing, and then the bit waveform is triggered to be played, so that each bit waveform is displayed in a superimposed manner, the center point of the eye diagram is ensured to be positioned in the middle of the screen display area, and the whole eye diagram is favorably and effectively displayed. For example, the clock data recovery result is composed of the number of clocks and the phase information of the clock edges, assuming that the time base is T when the waveform is played, the waveform display area on the display 5 is horizontally divided into K grids, and when the waveform is played, the recovered clock edges (such as rising edges) are used as trigger points, and the data in the range of K × T around each edge is taken out edge by edge for processing and displaying until the last clock edge.
It should be noted that, the data display circuit 24 adds a UI (user interface) to the eye diagram in the display window once every time the ideal sampling point of each bit waveform is used for displaying in a superimposed manner, and the UI has a perspective superimposed display performance, and the data of each UI is arranged relative to the display position, so that only one bit is added to the eye diagram once every time the eye diagram is displayed in a superimposed manner, and finally the eye diagram is formed in a superimposed manner. In addition, the data display circuit 24 may form a corresponding eye pattern for each frame of the collected data of the input signal, and may also form a corresponding eye pattern for consecutive frames of the collected data of the input signal, which is not limited herein.
In this embodiment, in order to conveniently set the preset parameters related to the logic processing circuit 2, the central processing unit 3 in this embodiment may further include a setting module (which may be regarded as a functional module and implemented when the central processing unit 3 runs), the setting module is communicatively connected to the display 5, and is configured to form a setting window (such as an interactive setting interface of the UI) on the display 5, and in response to the input information of the user on the setting window, control and set the interpolation mode and the interpolation multiple corresponding to the data processing circuit 26 in the logic processing circuit, the search level value corresponding to the waveform searching circuit 22, and the trigger level value corresponding to the digital trigger circuit 25.
In the present embodiment, referring to fig. 4, the central processing unit 3 is communicatively connected to the waveform searching circuit 22 and the waveform navigating circuit 23 in the logic processing circuit 2, respectively. The clock data recovery function implemented by the central processing unit 3 will be described in detail here.
The central processing unit 3 obtains the statistical information of each edge event from the waveform searching circuit 22, and is used for determining the number of bit waveforms in the digital waveform according to the statistical information of each edge event; and the clock period used for calculating the average period of the bit waveform in the digital waveform according to the number of the bit waveforms and recovering the obtained digital waveform by using the average period. The average period here is an average value of the number of data points that each of the bit waveforms has.
When the central processing unit 3 determines the number of bit waveforms in the digital waveform according to the statistical information of each edge event, the method includes: comparing the statistical information of each edge event to obtain a reference period of the bit waveform, wherein the reference period is a minor value of the number of data points in each bit waveform; and the central processor 3 calculates the number of the bit waveforms according to the displacement deviation of the second edge event and the last edge event in each edge event and the reference period.
The central processing unit 3 is further configured to calculate an ideal sampling point of each bit waveform according to the recovered clock cycle, configure the display position of the bit waveform with the ideal sampling point, form configuration information according to the display position of each bit waveform, and feed back the configuration information to the waveform navigation circuit 23.
In a specific embodiment, the functions of the central processing unit 3 can be realized by dividing into a plurality of stages, which are respectively described as follows: (1) in the first stage, the central processing unit 3 calculates the positional information deviation (i.e., displacement deviation) of the acquired adjacent edge events one by one, and the positional information deviation is expressed as S by a formulax,x+1＝Sx+1-SxS is the serial number of the data point which causes the edge event to be generated, and x is the occurrence serial number of the edge event; edge events with x being 1 can be discarded, thereby preventing the influence of the misdetected edge events on the subsequent calculation. Each positional information deviation S is calculated within x {2,3, …, M }x,x+1M represents the total number of edge events, the minimum value is discarded, and the second minimum value is selected as the theoretical reference period Sbase. Calculating the position information deviation S of the last edge event and the 2 nd edge eventtotal＝Sn-S2Obtaining the number N of bit waveforms in the current acquisition frame, and expressing the number N asN＝floor(Stotal/Sbase) Where floor () is a floor function. (2) In the second stage, in the current frame of the collected data, the central processing unit 3 calculates the actual average period (unit is point number, not time) of the bit waveform at this time as Sreal＝StotalN; to ensure the accuracy of the calculation result of the average period, the average period (in points) of the calculated bit waveform in the previous frame of collected data is Save_oldThe actual average period S of the current frame of collected datarealAveraging to obtain Save_new＝(Sreal+Save_old) /2, finally adding Save_newAs the average period of the waveform of the bits in the current frame of acquired data. It should be noted that if S isave_oldAnd SrealWhen the deviation exceeds 1000ppm (0.1%) in terms of time, it is considered that S isave_new＝Sreal，Save_old＝Sreal. Thereby averaging the average period S of the bit waveform in the current frame of the collected dataave_newAs the clock period of the corresponding digital waveform. (3) In the third stage, the central processing unit 3 obtains the clock period (the unit is point number, can use S) of the digital waveform corresponding to the current frame of the collected dataave_newExpressed), an ideal sampling point for each bit waveform can be calculated, formulated as Tx＝S2+Save_new/2+(x-1)*Save_new(ii) a Wherein T represents the number of ideal sampling points; x is the sequence number of the edge event and also is the sequence number of the bit waveform of the position of the edge event, and x belongs to { 1-N }.
In this embodiment, the logic processing circuit 2 may adopt an FPGA (Field Programmable Gate Array) to implement functions of acquiring the collected data, interpolating the collected data, searching for a digital waveform, navigating a waveform, and controlling a waveform display, and the central processing unit 3 may adopt a CPU to implement functions of recovering clock data and configuring a bit waveform.
Those skilled in the art will appreciate that the following technical advantages may be realized when performing eye reconstruction operations using the digital oscilloscope disclosed herein: (1) the eye pattern reconstruction function of the digital oscilloscope is realized by adopting a hardware framework combining a logic processing circuit, a central processing unit and a memory, so that the logic processing circuit and the central processing unit can respectively undertake a part of operation processing tasks, and the improvement of the eye pattern reconstruction efficiency is facilitated; (2) when executing the operation processing task of eye diagram reconstruction, the interaction of the processing result is mainly realized between the logic processing circuit and the central processing unit, the information storage capacity of the memory to the processing result is reduced, and the space saving in the memory is facilitated to ensure the storage requirement of the acquired data, so that the operation of clock data recovery is realized by using more sampling data as much as possible, and the accuracy of the clock data recovery is improved; (3) the functions of waveform construction, waveform search and waveform playing of digital waveforms are realized by the aid of the logic processing circuit, and the functions of clock data recovery and bit waveform display position configuration are realized by the aid of the central processing unit, so that the situation that the central processing unit is used for bearing all data processing tasks in the conventional oscilloscope is avoided, the operation burden of the central processing unit is effectively reduced, and the processing performance of the central processing unit on other tasks is favorably enhanced; (4) the logic processing circuit carries out waveform search on the digital waveform to obtain statistical information of each edge event in the digital waveform, so that a central processing unit can be facilitated to carry out clock data recovery according to the statistical information, and the purpose of configuring the display position of each bit waveform is achieved; (5) when the central processing unit recovers the clock data, the average period of the bit waveforms in the digital waveforms is calculated according to the number of the bit waveforms, and the clock period of the digital waveforms is obtained by utilizing the average period recovery, so that the ideal sampling point of each bit waveform is calculated to configure the display position of the bit waveform, the clock data recovery process is more accurate and rapid, and the high-efficiency data processing requirement is realized; (6) when the logic processing circuit independently searches the waveform of the digital waveform, the collected data is preprocessed in a parallel processing mode, so that the processing time of each frame of data is effectively reduced, and the overall efficiency of eye pattern reconstruction is improved.
Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments may be implemented by hardware, or may be implemented by computer programs. When all or part of the functions of the above embodiments are implemented by a computer program, the program may be stored in a computer-readable storage medium, and the storage medium may include: a read only memory, a random access memory, a magnetic disk, an optical disk, a hard disk, etc., and the program is executed by a computer to realize the above functions. For example, the program may be stored in a memory of the device, and when the program in the memory is executed by the processor, all or part of the functions described above may be implemented. In addition, when all or part of the functions in the above embodiments are implemented by a computer program, the program may be stored in a storage medium such as a server, another computer, a magnetic disk, an optical disk, a flash disk, or a removable hard disk, and may be downloaded or copied to a memory of a local device, or may be version-updated in a system of the local device, and when the program in the memory is executed by a processor, all or part of the functions in the above embodiments may be implemented.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. A digital oscilloscope supporting eye pattern reconstruction is characterized by comprising a logic processing circuit, a central processing unit, a memory and a display;
the memory is used for storing the collected data of the input signal;
the logic processing circuit is in communication connection with the memory and is used for constructing digital waveforms according to the acquired data, searching the digital waveforms to obtain statistical information of each edge event in the digital waveforms, sending the statistical information to the central processing unit to obtain feedback configuration information, and performing afterglow display on each bit waveform one by using the display position of each bit waveform configured in the configuration information; the digital waveform comprises a plurality of edge events generated by rising edges and/or falling edges, and bit waveforms are formed between adjacent edge events;
the central processing unit is in communication connection with the logic processing circuit and is used for performing clock data recovery according to the statistical information of each edge event, configuring the display position of each bit waveform to form the configuration information and feeding the configuration information back to the logic processing circuit;
and the display is in communication connection with the logic processing circuit and is used for obtaining an eye pattern corresponding to the input signal by superposition display under afterglow display.
2. The digital oscilloscope of claim 1, wherein the logic processing circuit comprises a data processing circuit, a waveform searching circuit, a waveform navigation circuit, and a data display circuit;
the data processing circuit is in communication connection with the memory and is used for acquiring the acquired data from the memory, interpolating the acquired data according to a preset interpolation mode and an interpolation multiple to obtain sample interpolation data consisting of each data point in the acquired data and each inserted data point, and constructing a digital waveform by using the sample interpolation data; each data point in the sample interpolation data has a corresponding amplitude value and a continuous distribution serial number;
the waveform searching circuit is in communication connection with the data processing circuit and the central processing unit respectively, and is used for comparing each data point in the sample insertion data with a preset searching level value to obtain a searching comparison result, detecting that the edge events are generated when a rising edge and/or a falling edge is formed in the searching comparison result, recording the event sequence, the event number and the distribution position of each edge event in the digital waveform to form statistical information of each edge event, and sending the statistical information to the central processing unit;
the waveform navigation circuit is in communication connection with the central processing unit and the data processing circuit respectively, and is used for obtaining the display position of each bit waveform according to the configuration information fed back by the central processing unit, guiding the logic processing circuit to re-read the acquired data from the memory, and reconstructing a digital waveform;
and the data display circuit is in communication connection with the data processing circuit and is used for performing afterglow display on each bit waveform one by utilizing the reconstructed digital waveform.
3. The digital oscilloscope of claim 2, wherein the logic processing circuit further comprises a digital trigger circuit and a data acquisition circuit;
the digital trigger circuit is used for acquiring sampling data of an input signal, comparing each data point in the sampling data with a preset trigger level value respectively to obtain a digital comparison result, and generating a trigger signal when detecting that a rising edge and/or a falling edge are formed in the digital comparison result;
the data acquisition circuit is in signal connection with the digital trigger circuit and is used for storing a frame of data consisting of the trigger signal and corresponding data points before and after the trigger signal to the memory when the digital trigger circuit generates the trigger signal so as to obtain the acquisition data of the input signal.
4. The digital oscilloscope of claim 3, further comprising an analog channel, wherein said analog channel comprises an input end and an output end, and said output end is in communication connection with said digital trigger circuit and said data acquisition circuit, respectively;
the analog channel is used for carrying out channel coupling and amplification processing on an input signal introduced into the input end, and carrying out analog-to-digital conversion on the amplified signal in a plurality of continuous clock cycles to obtain the sampling data; and transmitting the sampled data to the data trigger circuit and the data acquisition circuit using the output.
5. The digital oscilloscope of claim 3, wherein the data acquisition circuit stores, for each of the generated trigger signals, a frame of data consisting of data points sampled in a clock cycle corresponding to the trigger signal and data points sampled in a plurality of clock cycles before and after the clock cycle into the memory to form the acquired data of the input signal using the stored data points in the memory.
6. The digital oscilloscope of claim 3, wherein the data display circuit is further communicatively connected to the display, and further configured to control the display to enter a persistence display mode, play each of the bit waveforms one by one on the display with ideal sampling points of each of the bit waveforms as display positions, and superimpose the played graphics on the display as an eye diagram corresponding to the input signal.
7. The digital oscilloscope of claim 6, wherein said central processing unit comprises a setting module communicatively connected to said display for forming a setting window on said display, and in response to input information from a user on said setting window, controlling setting of interpolation modes and interpolation multiples corresponding to said data processing circuits in said logic processing circuit, search level values corresponding to said waveform search circuit, and trigger level values corresponding to said digital trigger circuit.
8. The digital oscilloscope of any one of claims 2-7, wherein said central processing unit is communicatively connected to said waveform searching circuit and said waveform navigation circuit, respectively, in said logic processing circuit;
the central processing unit acquires the statistical information of each edge event from the waveform searching circuit, and is used for determining the number of the bit waveforms in the digital waveform according to the statistical information of each edge event; and the average period is used for calculating the average period of the bit waveforms in the digital waveforms according to the number of the bit waveforms, and the clock period of the digital waveforms is obtained by recovering the average period, wherein the average period is the average value of the number of data points in each bit waveform;
the central processing unit is further configured to calculate an ideal sampling point of each bit waveform according to the recovered clock period, configure a display position of the bit waveform with the ideal sampling point, form the configuration information according to the display position of each bit waveform, and feed the configuration information back to the waveform navigation circuit.
9. The digital oscilloscope of claim 8, wherein said central processing unit, when determining the number of said bit waveforms in said digital waveform based on the statistical information of each of said edge events, comprises: comparing the statistical information of each edge event to obtain a reference period of the bit waveform, wherein the reference period is a minor value of the number of data points in each bit waveform; and calculating the number of the bit waveforms according to the displacement deviation of the second edge event and the last edge event in each edge event and the reference period.
10. The digital oscilloscope of claim 1, wherein the logic processing circuit is an FPGA and the central processing unit is a CPU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911233785.6A CN110887984B (en) | 2019-12-05 | 2019-12-05 | Digital oscilloscope supporting eye pattern reconstruction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911233785.6A CN110887984B (en) | 2019-12-05 | 2019-12-05 | Digital oscilloscope supporting eye pattern reconstruction |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110887984A true CN110887984A (en) | 2020-03-17 |
| CN110887984B CN110887984B (en) | 2022-07-01 |
Family
ID=69750522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911233785.6A Active CN110887984B (en) | 2019-12-05 | 2019-12-05 | Digital oscilloscope supporting eye pattern reconstruction |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110887984B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111766423A (en) * | 2020-09-02 | 2020-10-13 | 深圳市鼎阳科技股份有限公司 | Signal display method of oscilloscope and oscilloscope |
| CN112469017A (en) * | 2020-11-02 | 2021-03-09 | 桃芯科技(苏州)有限公司 | Digital waveform forwarding method and device based on wireless communication and electronic device |
| WO2022160309A1 (en) * | 2021-01-30 | 2022-08-04 | 华为技术有限公司 | Receiver, electronic device, and eye diagram testing method for receiver |
Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030208328A1 (en) * | 2002-05-06 | 2003-11-06 | Pickerd John J. | Acquisition system for a multi-channel relatively long record length digital storage oscilloscope |
| US20040002826A1 (en) * | 2002-03-14 | 2004-01-01 | Kalev Sepp | Method for optimized rendering of eye diagrams synchronized to a recovered clock and based on a single shot acquisition |
| US20040183518A1 (en) * | 2003-03-19 | 2004-09-23 | Weller Dennis J. | Apparatus and method for clock recovery and eye diagram generation |
| CN101275973A (en) * | 2008-04-18 | 2008-10-01 | 电子科技大学 | Digital storage oscillograph with very high waveform capturing rate |
| US20090122852A1 (en) * | 2007-11-12 | 2009-05-14 | Tektronix, Inc. | Eye violation and excess jitter trigger |
| CN101571562A (en) * | 2009-05-27 | 2009-11-04 | 东南大学 | Method for building eye pattern and carrying out eye pattern template test |
| CN103884891A (en) * | 2012-12-21 | 2014-06-25 | 北京普源精电科技有限公司 | Digital oscilloscope with high waveform refresh rate |
| US20150066409A1 (en) * | 2013-09-01 | 2015-03-05 | Keysight Technologies, Inc. | Real-time Oscilloscope For Generating a Fast Real-time Eye Diagram |
| CN105044420A (en) * | 2015-08-27 | 2015-11-11 | 电子科技大学 | Waveform searching method of digital oscilloscope |
| CN106226573A (en) * | 2016-08-16 | 2016-12-14 | 中国电子科技集团公司第四十研究所 | A kind of digital signal processing method for digital fluorescence oscilloscope |
| JP2016213680A (en) * | 2015-05-08 | 2016-12-15 | 富士通株式会社 | Waveform analysis support method, waveform analysis support program, and waveform analysis support device |
| WO2017133022A1 (en) * | 2016-02-06 | 2017-08-10 | 深圳高宜电子科技有限公司 | Digital oscilloscope, waveform searching method and device therefor |
| CN107478883A (en) * | 2017-03-16 | 2017-12-15 | 深圳市鼎阳科技有限公司 | A kind of method and apparatus for realizing any N times of equivalent sampling |
| CN108663555A (en) * | 2017-03-29 | 2018-10-16 | 苏州普源精电科技有限公司 | A kind of the waveform searching method and digital oscilloscope of digital oscilloscope |
| CN109725185A (en) * | 2019-02-01 | 2019-05-07 | 中电科仪器仪表有限公司 | A kind of oscillograph and its operation method for realizing waveform fast Acquisition |
| CN109815260A (en) * | 2018-12-06 | 2019-05-28 | 广州致远电子有限公司 | Waveform display apparatus, waveform parameter statistical method, terminal device and storage medium |
-
2019
- 2019-12-05 CN CN201911233785.6A patent/CN110887984B/en active Active
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040002826A1 (en) * | 2002-03-14 | 2004-01-01 | Kalev Sepp | Method for optimized rendering of eye diagrams synchronized to a recovered clock and based on a single shot acquisition |
| US20030208328A1 (en) * | 2002-05-06 | 2003-11-06 | Pickerd John J. | Acquisition system for a multi-channel relatively long record length digital storage oscilloscope |
| US20040183518A1 (en) * | 2003-03-19 | 2004-09-23 | Weller Dennis J. | Apparatus and method for clock recovery and eye diagram generation |
| US20090122852A1 (en) * | 2007-11-12 | 2009-05-14 | Tektronix, Inc. | Eye violation and excess jitter trigger |
| CN101275973A (en) * | 2008-04-18 | 2008-10-01 | 电子科技大学 | Digital storage oscillograph with very high waveform capturing rate |
| CN101571562A (en) * | 2009-05-27 | 2009-11-04 | 东南大学 | Method for building eye pattern and carrying out eye pattern template test |
| CN103884891A (en) * | 2012-12-21 | 2014-06-25 | 北京普源精电科技有限公司 | Digital oscilloscope with high waveform refresh rate |
| US20150066409A1 (en) * | 2013-09-01 | 2015-03-05 | Keysight Technologies, Inc. | Real-time Oscilloscope For Generating a Fast Real-time Eye Diagram |
| JP2016213680A (en) * | 2015-05-08 | 2016-12-15 | 富士通株式会社 | Waveform analysis support method, waveform analysis support program, and waveform analysis support device |
| CN105044420A (en) * | 2015-08-27 | 2015-11-11 | 电子科技大学 | Waveform searching method of digital oscilloscope |
| WO2017133022A1 (en) * | 2016-02-06 | 2017-08-10 | 深圳高宜电子科技有限公司 | Digital oscilloscope, waveform searching method and device therefor |
| CN106226573A (en) * | 2016-08-16 | 2016-12-14 | 中国电子科技集团公司第四十研究所 | A kind of digital signal processing method for digital fluorescence oscilloscope |
| CN107478883A (en) * | 2017-03-16 | 2017-12-15 | 深圳市鼎阳科技有限公司 | A kind of method and apparatus for realizing any N times of equivalent sampling |
| CN108663555A (en) * | 2017-03-29 | 2018-10-16 | 苏州普源精电科技有限公司 | A kind of the waveform searching method and digital oscilloscope of digital oscilloscope |
| CN109815260A (en) * | 2018-12-06 | 2019-05-28 | 广州致远电子有限公司 | Waveform display apparatus, waveform parameter statistical method, terminal device and storage medium |
| CN109725185A (en) * | 2019-02-01 | 2019-05-07 | 中电科仪器仪表有限公司 | A kind of oscillograph and its operation method for realizing waveform fast Acquisition |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111766423A (en) * | 2020-09-02 | 2020-10-13 | 深圳市鼎阳科技股份有限公司 | Signal display method of oscilloscope and oscilloscope |
| CN112469017A (en) * | 2020-11-02 | 2021-03-09 | 桃芯科技(苏州)有限公司 | Digital waveform forwarding method and device based on wireless communication and electronic device |
| WO2022160309A1 (en) * | 2021-01-30 | 2022-08-04 | 华为技术有限公司 | Receiver, electronic device, and eye diagram testing method for receiver |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110887984B (en) | 2022-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110672899B (en) | Eye pattern reconstruction method for digital oscilloscope and storage medium | |
| CN110887984B (en) | Digital oscilloscope supporting eye pattern reconstruction | |
| US6753677B1 (en) | Trigger jitter reduction for an internally triggered real time digital oscilloscope | |
| CN104181365B (en) | A kind of measuring device with zooming display function | |
| US5854996A (en) | Logic signal extraction | |
| JP4723030B2 (en) | Improved digital trigger circuit | |
| CN102128963B (en) | Adopt equipment and the method for large acquisition memory high speed display waveform | |
| JP2007256284A (en) | Signal acquisition system and technique, and waveform displaying method | |
| CN108776249B (en) | Oscillograph recorder with double capturing functions | |
| CN102128962A (en) | Test and measurement instrument and method for providing post-acquisition trigger control and presentation | |
| CN110208589B (en) | Time domain signal waveform measuring method and device and digital oscilloscope | |
| CN206489205U (en) | Reduce system, digit chip and the oscillograph of oscillograph external trigger waveform shake | |
| CN110836992B (en) | Oscillography power meter acquisition system based on FPGA | |
| JPH0361908B2 (en) | ||
| CN102012445A (en) | Test and measurement instrument and method for providing post-acquisition trigger control and presentation | |
| CN101261300B (en) | Method for measuring digital storage oscillographs storage depth | |
| CN108982941A (en) | A kind of method for real-time measurement and device, oscillograph, storage medium of period frequency | |
| CN104076178B (en) | A kind of oscillograph with improvement Trigger Function | |
| CN109991458B (en) | FPGA-based waveform longitudinal averaging system | |
| CN109948223A (en) | A kind of impulse amplitude acquisition methods based on Lagrange's interpolation | |
| CN109142835B (en) | Data acquisition system with waveform multi-frame recording function | |
| CN110806501A (en) | Waveform measuring method | |
| US20120053875A1 (en) | Re-sampling acquired data to prevent coherent sampling artifacts | |
| JPH073445B2 (en) | Time interval analyzer | |
| CN113447692B (en) | Oscilloscope with data recording function and waveform display method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |