CN110875374B - 纳米线堆叠栅极全环绕元件及制造方法、及半导体结构 - Google Patents

纳米线堆叠栅极全环绕元件及制造方法、及半导体结构 Download PDF

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CN110875374B
CN110875374B CN201910329043.7A CN201910329043A CN110875374B CN 110875374 B CN110875374 B CN 110875374B CN 201910329043 A CN201910329043 A CN 201910329043A CN 110875374 B CN110875374 B CN 110875374B
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nanowire
section
gate
semiconductor
dielectric
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CN110875374A (zh
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王梓仲
郑兆钦
陈自强
李东颖
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本揭露描述用于形成栅极全环绕FET元件中源极/漏极区域与纳米线通道区域之间的低电阻接合面的技术。一种半导体结构包括基板、垂直堆叠于基板之上的多个单独半导体纳米线条、邻接多个单独半导体纳米线条中的每一者且侧向接触多个单独半导体纳米线条中的每一者的半导体磊晶区域、至少部分地在多个单独半导体纳米线条之上的栅极结构以及侧向位于半导体磊晶区域与栅极结构之间的介电结构。

Description

纳米线堆叠栅极全环绕元件及制造方法、及半导体结构
技术领域
本揭露是有关一种纳米线堆叠栅极全环绕元件、一种半导体结构及一种纳米线堆叠栅极全环绕的制造方法。
背景技术
互补金属氧化物半导体(CMOS)晶体管为用于集成电路的构建块。较快的CMOS切换速度需要较高的驱动电流，其压低CMOS晶体管的栅极长度。较短的栅极长度导致不当“短通道效应”，其中栅极的电流控制功能受损。已开发FinFET晶体管(除其他者以外)以克服短通道效应。作为改良通道静电控制的又一步骤，已开发了具有缠绕栅极的晶体管，其中栅极部分可自半导体通道或通道条的上表面及侧壁环绕半导体通道或通道条。
发明内容
根据本揭露一些实施例，一种纳米线堆叠栅极全环绕元件包含基板、通道区域、源极/漏极结构、栅极结构与内间隔件结构。通道区域包括在基板之上的纳米线结构的堆叠，纳米线结构的堆叠包括第一纳米线结构，纳米线结构包括在第一纳米线结构的边缘处的第一区段及邻接第一区段的第二区段，第二区段具有大于第一区段的一直径。源极/漏极结构邻接与接触第一纳米线结构的第一区段。栅极结构缠绕第一纳米线结构。内间隔件结构侧向上在源极/漏极结构及栅极结构之间。
根据本揭露一些实施例，一种半导体结构包括基板、多个单独半导体纳米线条、半导体磊晶区域、栅极结构与第一介电结构。单独半导体纳米线条垂直堆叠于基板之上。半导体磊晶区域邻接且侧向接触多个单独半导体纳米线条中的每一者。栅极结构至少部分地在单独半导体纳米线条之上。第一介电结构侧向上在半导体磊晶区域及栅极结构之间，第一介电结构具有帽形轮廓。
根据本揭露一些实施例，一种纳米线堆叠栅极全环绕的制造方法包括接纳晶圆，晶圆包括在基板之上的磊晶层的堆叠，磊晶层的堆叠包括以交替顺序堆叠的多个半导体磊晶层及多个牺牲磊晶层；通过图案化晶圆形成鳍结构，鳍结构包括多个半导体条及多个牺牲条的堆叠；在鳍结构之上形成牺牲栅极结构及外间隔件，牺牲栅极结构接触鳍结构的至少三个表面；通过移除侧向延伸超过外间隔件的牺牲条的部分形成后退的牺牲条，而半导体条保持侧向延伸超过外间隔件；形成在侧向上邻接后退的牺牲条的内间隔件；通过使半导体条后退而形成半导体条的经暴露的边缘表面；形成半导体层，其邻接内间隔件且接触半导体条的经暴露的边缘表面；通过移除牺牲栅极及后退的牺牲条而形成开放间隔；以及在开放间隔内形成替代栅极。
附图说明
当结合附图进行阅读时得以自以下详细描述最佳地理解本揭露的态样。在诸图中，除非上下文另外标识，否则相同元件符号标识类似元件或动作。诸图中元件的大小及相对位置未必按比例绘制。实际上，为了论述清楚可任意地增大或减小各特征的尺寸。
图1A至图1C为根据本揭露的实例实施例的元件的立体图及横截面图；
图1D至图1E为图1A至图1C的实例元件的内间隔件的实施例的横截面图；
图2为根据本揭露的实例实施例的制造过程的流程图；
图3A-C至图12为根据本揭露的实例实施例的制作图1A至图1C的实例元件的各阶段的立体图及横截面图；
图13及图14展示根据本揭露的实例实施例的元件的替代及/或额外实施例。
具体实施方式
本揭露描述用于栅极全环绕FET元件中源极/漏极区域与纳米线通道区域之间的低电阻接合面的技术。纳米线条的堆叠经形成而包括交替堆叠的硅纳米线条及硅锗纳米线条。虚设栅极结构经形成而在纳米线条的堆叠之上且环绕纳米线条的堆叠。硅锗(或硅)纳米线条用作牺牲条且硅(或硅锗)纳米线条用作FET元件的半导体主体或通道，且称作“半导体纳米线条”。牺牲条选择性地后退，剩余半导体纳米线条。内间隔件经形成而在侧向上邻接后退的牺牲条。半导体纳米线条与内间隔件形成同时后退或在内间隔件形成之后后退，使得确保后退的半导体纳米线条的边缘表面自内间隔件暴露。源极/漏极区域经由磊晶程序形成，接触后退的半导体纳米线条的经暴露边缘表面中的每一者。因为后退的半导体纳米线条的边缘表面不被内间隔件的介电材料覆盖，所以确保了源极/漏极区域及通道区域(亦即，后退的半导体纳米线条)之间的欧姆接合面。
以下揭示内容提供用于实施所描述标的物的不同特征的许多不同实施例或实例。以下描述组件及配置的特定实例以简化本描述。当然，此等仅为实例且并不意欲为限定性的。举例而言，在如下描述中第一特征在第二特征之上或在第二特征上的形成可包括其中第一及第二特征直接接触形成的实施例，且亦可包括其中额外特征可在第一及第二特征之间形成而使得第一及第二特征可不直接接触的实施例。另外，本揭露可在各种实例中重复元件符号及/或字母。此重复是出于简化及清楚目的，且其本身并不指示所论述的各种实施例及/或配置之间的关系。
另外，为了描述简单起见，可在本文中使用诸如“在……之下”、“在……下方”、“下方”、“在……上方”、“上方”以及其类似术语的空间相对术语，以描述如诸图中所说明的一个元件或特征相对于另一(其他)元件或特征的关系。除了诸图中所描绘的定向以外，所述空间相对术语意欲亦涵盖在使用中或操作中的元件的不同定向。设备可以其他方式定向(旋转90度或在其他定向上)，且可同样相应地解释本文中所使用的空间相对描述词。
在以下描述中，阐述特定细节，以便提供对本揭露的各种实施例的详尽理解。然而，熟悉此项技术者将理解，本揭露可在无此等特定细节的情况下进行。在其他情况下，未详细描述与电子组件及制造技术相关联的熟知结构，以避免不必要地模糊本揭露的实施例的描述。
除非上下文另外需要，否则贯穿以下说明书及申请专利范围，词语“包含”及其变形(诸如，“包含(comprises)及包含(comprising)”)应以开放性的、包括性的含义进行解释，亦即，解释为“包括但不限于”。
诸如第一、第二及第三的序数词的使用未必暗示次序的排名含义，而可仅仅在多个动作或结果之间进行区分。
贯穿此说明书对“一个实施例”或“实施例”的引用意谓结合实施例所描述的特定特征、结构或特性包括在至少一个实施例中。因此，贯穿此说明书在各处的短语“在一个实施例中”或“在实施例中”未必皆代表同一实施例。此外，特定特征、结构或特性可以任何合适方式在一或多个实施例中进行组合。
如在此说明书及附加申请专利范围中所使用，单数形式“一”以及“所述”包括多个引用，除非上下文另有清楚指示。亦应注意，术语“或”一般以其包括“及/或”的含义进行使用，除非上下文另有清楚指示。
栅极全环绕(Gate all around；GAA)晶体管结构可通过任何合适方法进行图案化。举例而言，可使用一或多个光微影制程(包括双图案化或多图案化制程)来图案化结构。大体而言，双图案化或多图案化制程组合了光微影及自对准制程，从而允许间距(例如)小于可使用单一、直接光微影制程获得的间距的图案产生。举例而言，在一个实施例中，牺牲层形成于基板之上且使用光微影制程进行图案化。使用自对准制程并靠着经图案化的牺牲层形成间隔件。牺牲层接着经移除，且剩余间隔件可接着用以图案化GAA结构。
图1A为元件100的立体图。参看图1A，元件100包括基板110，基板110包括下方鳍结构112。离散纳米线结构122的堆叠120(“纳米线堆叠”120)形成于基板110之上且更具体而言，在实施例中，在基板110的下方鳍结构112之上。纳米线堆叠120包括多个纳米线结构122(例如，纳米线条)，其在z方向上垂直地彼此堆叠。通过所接触的纳米线结构122的边缘表面122E，两个源极/漏极结构130经形成而邻接纳米线结构122中的至少一些且与其接触。注意，出于说明性目的，在图1A中，省略源极/漏极结构130中的一者以展示纳米线堆叠120。应了解，在最终元件100中，不暴露纳米线堆叠120。
栅极结构140形成于基板110之上。栅极结构140包括栅电极142及栅极介电层144。栅极结构140通过外间隔件结构150及内间隔件结构152中的至少一者与源极/漏极结构130分离。具体而言，例如，内间隔件结构152在x轴方向上侧向形成于源极/漏极结构130与栅极结构140之间。
一或多个绝缘层160、162经形成而邻接源极/漏极结构130及/或栅极结构140。绝缘层160/162包括氧化硅或其他合适介电材料。注意，在图1A中，仅出于说明性目的，省略绝缘层160、162的一些部分以展示源极/漏极结构130及/或纳米线堆叠120。绝缘层160、162可为介电材料的单一层、同一介电材料的两个单独形成的层，或不同介电材料的两个层。
作为说明性实例，图1A展示的是，源极/漏极结构130经形成而使得源极/漏极结构130的上表面132大体上与栅极结构140的上表面在同一位准上。此实例并非限制性的。视设计要求而定，在其他实例中，源极/漏极结构130高于或低于栅极结构140，其皆包括于本揭露中。
在实施例中，将接触源极/漏极结构130的纳米线结构122配置为元件100的(若干)通道区域。
基板110可包括呈结晶结构的硅基板及/或如锗的其他元素半导体。或者或另外，基板110可包括诸如碳化硅、砷化镓、砷化铟和/或磷化铟的化合物半导体。另外，基板110亦可包括绝缘体上硅(SOI)基板。基板110可包括磊晶层及/或可为了效能增强而发生应变。基板110亦可包括视设计要求(诸如P型基板及/或N型基板)而定的各种掺杂配置及诸如P井及/或N井的各种掺杂区域。
栅极结构140形成为替换栅极。以下描述列出用于包括栅电极142及栅极介电质144的栅极结构140的材料的实例，其为非限定性的。栅电极142包括导电材料，例如，金属或金属化合物。用于栅电极142的合适金属材料包括钌、钯、铂、钨、钴、镍及/或导电金属氧化物和其他合适P型金属材料，且包括铪(Hf)、锆(Zr)、钛(Ti)、钽(Ta)、铝(Al)、铝化物及/或导电金属碳化物(例如，碳化铪、碳化锆、碳化钛及碳化铝)，及用于N型金属材料的其他合适材料。在一些实例中，栅电极142包括功函数层，其经调谐以具有适当的功函数用于增强场效应晶体管元件的效能。举例而言，合适N型功函数金属包括Ta、TiAl、TiAlN、TaCN、其他N型功函数金属，或其组合，且合适P型功函数金属材料包括TiN、TaN、其他P型功函数金属，或其组合。在一些实例中，诸如铝层、铜层、钴层或钨层的导电层形成于功函数层之上，使得栅电极142包括安置于栅极介电质144之上的功函数层及安置于功函数层之上且在栅极帽盖(为了简化起见未展示)之下的导电层。在实例中，视设计要求而定，栅电极142具有范围为自约5nm至约40nm的厚度。
在实例实施例中，栅极介电层144包括界面氧化硅层(为了简化而未单独展示)，例如，具有范围为自约5埃
Figure GDA0002279398390000051
至约10埃
Figure GDA0002279398390000052
的热或化学氧化物。在实例实施例中，栅极介电层144还包括高介电常数(高K)介电材料，其选自氧化铪(HfO2)、氧化铪硅(HfSiO)、氧氮化铪硅(HfSiON)、氧化钽铪(HfTaO)、氧化铪钛(HfTiO)、氧化铪锆(HfZrO)、其组合及/或其他合适材料中的一或多者。在一些应用中，高K介电材料包括大于6的介电常数(K)值。视设计要求而定，使用介电常数(K)值为7或更高的介电材料。可通过原子层沉积(ALD)或其他合适技术形成高K介电层。根据本文中所描述的实施例，栅极介电层144的高K介电层包括范围为自约10埃
Figure GDA0002279398390000061
至约30埃
Figure GDA0002279398390000062
的厚度或其他合适厚度。
外间隔件150由诸如氮氧化硅(SiOxNy)、氮化硅(Si3N4)、一氧化硅(SiO)、碳氮氧化硅(SiONC)、碳氧化硅(SiOC)、真空及其他介电质或其他合适材料的低K介电材料形成。外间隔件150可经由化学气相沉积(CVD)、高密度电浆CVD、旋涂、溅射或其他合适方法形成。
内间隔件152由高K介电材料(例如，比外间隔件150的介电常数高的介电常数)形成。用于内间隔件152的高K材料包括氮化硅Si3N4、碳化硅(SiC)、氧化铪(HfO2)或其他合适的高K介电材料中的一或多者。在实施例中，内间隔件152材料的K值在约外间隔件150材料的K值三倍至四倍之间。在实例中，内间隔件152亦包括邻接栅极结构140或源极/漏极结构130中的一或多者的一或多个气隙。
内间隔件152包括形成于栅极结构140及源极/漏极结构130之间且邻接通道区域(纳米线条)122的第一区段152A。在实施例中，内间隔件结构152亦包括向上延伸邻接外间隔件150的第二区段152B。相比于第一区段152A，内间隔件152的第二区段152B更远离通道区域122。在此实施例中，源极/漏极结构130的部分可通过内间隔件152(具体而言为内间隔件152的第二区段152B)及外间隔件150两者与栅极结构140分离。在实施例中，第一区段152A为帽形的，其中帽形的凸起顶部指向栅极结构140。
图1B为元件100沿切割线B-B的横截面图。如在图1A及图1B中共同展示，栅极结构140在纳米线堆叠120的至少三个表面处(亦即，上表面及侧表面)处邻接纳米线堆叠122。图1B展示栅极结构140缠绕个别纳米线结构122中的一或多者。如图1B中所展示，栅电极142及栅极介电质144两者缠绕个别纳米线结构122，此非作限定。有可能仅栅极介电质144缠绕个别纳米线结构122且栅电极142作为整体邻接纳米线堆叠120的三个表面。
在实施例中，如图1B中所展示，纳米线结构122包括边缘区段(第一区段)124及邻接边缘区段124的环形部分126(第二区段)。环形区段126具有比边缘区段124大的直径。在另一实施例中，纳米线结构122亦包括中心区段128，其具有小于环形区段126的直径的直径。纳米线结构122的其他形状或轮廓亦是可能的且包括于本揭露中。
在实施例中，内间隔件结构152的第一区段152A“内间隔件152A”包括大体上圆顶形的轮廓。如在本揭露中所使用，圆顶形轮廓包括具有较大基底及较小顶尖的所有轮廓。锥形或金字塔形或其他类似形状皆包括于如本揭露中所使用的“圆顶形轮廓”中。圆顶形内间隔件152A的顶尖经定向而朝向栅极结构140。另外，圆顶形轮廓可包括一个以上顶尖且包括在两个顶尖之间的凹陷部分。
图1D展示取自图1B的内间隔件152A的放大的横截面图。如图1D中所展示，内间隔件152A包括大体上帽形的轮廓，其中帽形的凸起顶面指向栅极结构140。帽形轮廓包括凸起部分(例如，圆顶形部分)154及自圆顶形部分154突出的边沿形部分156。圆顶形部分154及边沿形部分156在界面158处相遇。在一些情况下，圆顶形部分154平滑地过渡进入边沿形部分126中且第一区段152A因此总体上包括圆顶形轮廓。
图1E包括来自横截面图的内间隔件152A的替代或额外轮廓实施例。实例I展示内间隔件152A可包括接近栅极结构140的锥形头部部分及远离栅极结构140的基底部分。实例II展示内间隔件152A可包括接近栅极结构140的圆顶形头部部分及远端基底部分。实例III展示内间隔件152A可包括接近栅极结构140的多圆顶形头部部分及远端基底部分。实例IV展示内间隔件152A可包括自近端(相对于栅极结构140而言)至远端的连续形状。
实例I至IV展示头部部分连同自头部部分延伸的基底部分的各种轮廓。在实例I至IV中，基底部分的边缘表面大体上铅垂或垂直。实例V至VIII展示基底部分的边缘表面包括朝向栅极结构140的缩进或凹陷的各种实例。实例V至VIII展示基底部分经最小化以变成凹陷基底表面，此非作限定。凹陷基底表面亦可存在于基底部分延伸远离头部部分的情况下。举例而言，图1D的边沿形部分156亦可包括凹陷基底表面。
在实施例中，源极/漏极结构130自经堆叠而在纳米线堆叠120中较高的纳米线结构122(“较高纳米线结构122”)一直向下延伸至经堆叠而在纳米线堆叠120中较低的纳米线结构122(“较低纳米线结构122”)。源极/漏极结构130分别通过其边缘表面122E接触较高纳米线结构122及较低纳米线结构122。
在实施例中，如图1B中所展示，所有纳米线结构122皆接触源极/漏极结构130，此非作限定。在其他情况下，视制造过程及产品设计而定，纳米线结构122中的一些(例如，堆叠于纳米线堆叠120的顶面上的纳米线结构)不接触源极/漏极结构130。举例而言，内间隔件结构150可形成于最顶纳米线结构122及源极/漏极结构130之间。
图1C为元件100沿图1A中的切割线C-C的横截面图。如图1A及图1C中共同展示，纳米线堆叠120的多个纳米线结构122由栅极结构140缠绕或环绕。具体而言，如图1C中所展示，纳米线结构122各自直接由栅极介电质144环绕，栅极介电质144定位于栅电极142及纳米线结构122之间。
纳米线堆叠120形成于基板110的下方鳍结构112之上且与下方鳍结构112重叠。作为说明性实例，图1C展示纳米线堆叠120的下方纳米线结构122与基板110的下方鳍结构112分离，此非作限定。在其他实施例中，视设计要求而定，最下方的纳米线结构122接触下方鳍结构112。亦即，纳米线堆叠120中的最下方纳米线122的底表面(或下方表面)129可不邻接栅极结构140。举例而言，在纳米线结构122及基板110由同一半导体材料(例如，硅)形成的情况下，可能为了符合一些设计要求而使最下方纳米线结构122接触下方鳍部分112。
图2为可用以制作图1A至图1D中所展示的实例元件100及其他元件的实例制造过程200。图3A-C至图12展示在制作实例元件100的过程中的晶圆300的阶段。在每一阶段处，展示晶圆300的三个视图中的一或多者，亦即，以字母“A”引用的立体图、以字母“B”引用且亦称作“B”平面(X-Z平面)的沿切割线B-B的截面图，以及以字母“C”引用且亦称作“C”平面的沿切割线C-C的截面图。在一些阶段处，展示晶圆300的仅一个视图，且为了简化将省略各别视图的参考字母。
参看图2，亦参看图3A至图3C，在实例操作210中，接纳晶圆300。图3A至图3C说明晶圆300。
{晶圆300包括基板110，例如，为硅、硅锗及/或其他合适半导体材料。举例而言，基板110可包括诸如碳化硅、砷化镓、砷化铟和/或磷化铟的化合物半导体。另外，基板110亦可包括绝缘体上硅(SOI)基板。
不同材料的磊晶层312/314的垂直堆叠形成于基板110之上且以交替顺序堆叠，亦即，每一磊晶层312、314紧接着且垂直邻接磊晶层314/312中的不同者。作为说明性实例，图3A至图3C展示总共四个磊晶层312及五个磊晶层314堆叠于基板110之上，此非作限定。其他数目的磊晶层312、314亦为可能的且包括于本揭露中。在实施例中，晶圆300包括与磊晶层314相同数目的磊晶层312。在另一实施例中，晶圆300包括与磊晶层314的数目不同的数目的磊晶层312。
磊晶层312由第一半导体材料形成且磊晶层314由不同于第一半导体材料的第二半导体材料形成。在实施例中，第一半导体材料及第二半导体材料具有不同蚀刻率(相对于相同蚀刻剂而言)，亦即，具有蚀刻选择性，使得可进行选择性蚀刻以移除磊晶层312、314中的一者而另一者得以保留。在实施例中，磊晶层312是为硅锗SixGe1-x，其中x大于0且小于1，且在一些实施例中，在约0.4及约0.9之间。在实施例中，磊晶层314为硅。
磊晶层312、314各自可以具有各种掺杂剂/杂质(诸如砷、磷、硼、镓、铟、锑、氧、氮或其各种组合)的各种方法进行掺杂。
在实施例中，磊晶层312、314各自分别为硅锗纳米线或硅纳米线的薄片，且称作纳米薄片312、314。纳米薄片312、314中的每一者可包括在约4nm至约20nm之间的厚度。在一些实施例中，纳米薄片312、314各自可包括在约5nm至约8nm之间的厚度。
磊晶层312、314亦可为其他半导体材料。
可使用蒸汽-液体-固体(VLS)技术或其他合适的生长程序形成磊晶层312、314。在本文描述中，分别将1-D纳米线硅或硅锗的纳米薄片314、312用作本揭露的描述中的说明性实例。
纳米薄片312/314可形成于基板110全域之上或可形成于基板110区域之上。在区域形成程序中，纳米薄片312、314形成于由浅沟槽隔离(STI)区域所界定的区域内及/或形成于掺杂基板区域(例如，P井或N井)之上。
返回参看图2，亦参看图4A至图4C，在实例操作220中，通过图案化晶圆300来形成鳍结构402。可使用任何合适的图案化程序且皆包括于本揭露中。鳍结构402包括两个部分，上方部分410及下方部分112。下方部分112是由图案化基板110(例如，为硅)来形成，且亦为基板110的部分，且称作“基板”或“下方鳍部分”或鳍的“下方部分”(随情况来应用)。上方部分410由图案化堆叠的磊晶层312、314来形成。在磊晶层312、314为纳米薄片的实例情形下，上方鳍部分410包括纳米线硅锗条412，且纳米线硅条414以交替方式垂直堆叠。包括纳米线条412、414的堆叠的上方鳍部分410亦称作纳米线堆叠410。注意，纳米线堆叠410不同于图1A至图1C中所展示的元件的纳米线堆叠120，因为纳米线条412、414的一个群组将作为牺牲条被移除，如本文中所描述。
在以下制造阶段中，纳米线条412或纳米线条414将自纳米线堆叠410移除且称作“牺牲条”。保留于纳米线堆叠410上的纳米线条412、414称作“半导体纳米线条”。作为说明性实例，硅锗纳米线条412作为牺牲条被移除，且硅纳米线条414最终得以保留变成元件100的纳米线堆叠120的纳米线结构122。
绝缘层160形成于基板110之上且邻接鳍结构402，如图4A中(在图4A中，出于说明性目的省略了绝缘层160的部分)及图4C中所展示。在实施例中，绝缘层160为氧化硅或其他合适介电材料。在一些实施例中，蚀刻终止层420形成于绝缘层160及包括鳍结构402的下方部分112的基板110之间。蚀刻终止层420为与绝缘层160不同的介电材料。在实施例中，蚀刻终止层420为氮化硅或其他合适的介电材料。在实施例中，绝缘层160及蚀刻终止层420仅邻接下方鳍部分112，且上方鳍部分410自绝缘层160及蚀刻终止层420暴露。
返回参看图2，亦参看图5A至图5C，在实例操作230中，牺牲或虚设栅极结构510形成于基板110之上且邻接上方鳍部分410的三个表面或环绕上方鳍部分410的三个表面，亦即，两个侧表面420S及上表面410U。在实施例中，牺牲栅极结构510可包括牺牲多晶硅层512、牺牲帽层(为了简化而未展示)，及牺牲衬垫层(为了简化而未展示)。牺牲帽层及牺牲衬垫层可为氧化硅或其他合适的介电材料。牺牲栅极结构510的总高度可高于或大体上等于(但不低于)替换栅极，其将被制作在由牺牲栅极结构510所占用的空间中。
外间隔件520经形成而邻接牺牲栅极结构510。外间隔件520可为氮化硅或其他合适介电材料。外间隔件150由诸如氮氧化硅、氮化硅(Si3N4)、一氧化硅(SiO)、碳氮氧化硅(SiONC)、碳氧化硅(SiOC)、一氮化硅(SiN)、真空及其他介电质或其他合适材料的低K介电材料形成。外间隔件520可经由化学气相沉积(CVD)、高密度电浆CVD、旋涂、溅射或其他合适方法形成。
如图5A及图5B中所展示，纳米线条412、414各自在x轴方向上侧向延伸超过外间隔件520。
在牺牲栅极结构510及外间隔件520的形成之前或之后，绝缘层162经形成而邻接外间隔件520。绝缘层162可包括与绝缘层160相同的介电材料或可为不同介电材料。出于说明性目的而自图5A省略绝缘层162。
图6至图12展示在各种制造阶段中晶圆300的B平面图。
返回参看图2，亦参看图6，在实例操作240中，沟槽或孔620形成于绝缘层162内以通过外间隔件520的每一侧暴露纳米线堆叠410。在实施例中，亦暴露外间隔件520的与纳米线堆叠410重叠的部分622。图6展示孔620大体上在最顶部纳米线条(在此为硅锗的牺牲纳米线条412，此非作限定)的位准处停止。在其他实施例中，可移除顶部纳米线条412、414中的一或多者的部分。亦即，孔620可向下延伸超过纳米线堆叠410的上表面410U。
返回参看图2，亦参看图7，在实例操作250中，经由孔620进行选择性蚀刻，以选择性地移除自孔620暴露的硅锗的牺牲纳米线条412且剩下硅的半导体纳米线条414保留于孔620内。在实施例中，使用氢氧化铵(NH4OH)的氨溶液或其他合适蚀刻剂来选择性地蚀刻掉牺牲纳米线条412。在将硅的纳米线条414用作牺牲纳米线条的情形下，使用盐酸溶液(HCL)或其他蚀刻剂以选择性地蚀刻掉纳米线条414而同时将硅锗的纳米线条412留在原处。
在实施例中，执行选择性湿蚀刻以移除牺牲纳米线条412(或414)，以使得凹槽710形成于保留在牺牲栅极结构510及外间隔件150之下的牺牲纳米线条412的边缘部分712上，其出于描述性目的而在本文中称作“后退的牺牲条412R”。
在实施例中，蚀刻条件经控制以使得剩余牺牲条412R的边缘部分712向内后退超过外间隔件150的外表面720。在实施例中，边缘部分712的最外点714位于外间隔件150的外表面720及内表面722之间。
牺牲条412的后退不可避免地亦移除了半导体纳米线条414的小部分414S(以虚线展示)。因此，暴露于孔620内的纳米线条414的第一区段414(1)包括小于第二区段414(2)的直径，第二区段414(2)在牺牲栅极结构510之下且不暴露于孔620内。通过选择性地移除牺牲条412而同时半导体纳米线条414得以保留的制造过程的顺序致能晶圆的此阶段的此结构特性。如本文中所描述，区段414(1)包括小于第二区段414(2)的直径的此结构特性亦影响其他结构特征的形状，如图1D的内间隔件152A。
返回参看图2，亦参看图8，在实例操作260中，介电层810经形成而邻接后退的牺牲条412R的边缘部分712，其保持在牺牲栅极结构510之下。介电层810至少部分地填充邻接边缘部分712的凹槽710。在实例中，介电层810不完全填充凹槽710，且缝隙(气隙抑或真空缝隙)形成于介电层810与后退的牺牲条412R的边缘部分712之间。图8’以放大图展示缝隙812。
在实施例中，介电层810由介电常数比外间隔件520高的介电材料形成。用于内间隔件152的介电材料包括氮化硅Si3N4、碳化硅(SiC)、氧化铪(HfO2)或其他合适介电材料中的一或多者。在实施例中，介电层810材料的K值在约外间隔件520材料的K值三倍至四倍之间。
在实施例中，介电层810亦形成于半导体纳米线条414的第一区段414(1)之上。
返回参看图2，亦参看图9，在实例操作270中，通过经由各向异性蚀刻移除介电层810的外部部分而形成内间隔件152A。在实施例中，内间隔件152A的所得表面152S(其与后退的牺牲条412R相对)大体上与外间隔件520的外表面720铅垂。在另一实施例中，表面152S经形成而向外超过外间隔件520的外表面720。另外，在实施例中，介电层810的薄层152B保持邻接外间隔件520且可变成内间隔件结构152(152A+152B)的第二区段152B。注意，第二区段152B在技术上并非“内间隔件”且仅仅出于描述性目的而称作内间隔件结构152的第二区段。
在实施例中，内间隔件152的第一区段152A(内间隔件152A)归因于填充凹槽710而包括大体上圆顶形的轮廓。如在本揭露中所使用，圆顶形轮廓包括具有较大基底及较小顶尖的所有轮廓。锥形或金字塔形或其他类似形状皆包括于如本揭露中所使用的“圆顶形轮廓”中。内间隔件152或第一区段152A的其他替代或额外形状/轮廓亦为可能的。圆顶形内间隔件152A的顶尖指向后退的牺牲条412R。
在实施例中，因为半导体纳米线条414的第一区段414(1)具有小于半导体纳米线条414的第二区段414(2)的直径，所以内间隔件152A包括大体上帽形的轮廓。帽形轮廓包括圆顶形部分154及自圆顶形部分154突出的边沿形部分156。圆顶形部分154及边沿形部分156在界面158处相遇。在一些情况下，界面158与后退的牺牲条412R的最外点714重叠(亦参见图7)。在一些情况下，圆顶形部分154平滑地过渡进入边沿形部分156中且内间隔件152A因此总体上包括圆顶形轮廓。
半导体纳米线条414后退，借此第一区段414(1)的部分得以与移除介电层810的外部部分同时被移除或在移除介电层810的外部部分之后移除。亦即，多个半导体条的边缘表面122E是在与内间隔件152(或具体而言为第一区段152A)形成同时或在内间隔件152(或具体而言为第一区段152A)形成之后中的一者情形下而形成。因此，后退的半导体纳米线条414的边缘表面122E自内间隔件152A暴露。在实施例中，边缘表面122E大体上与内间隔件152A的表面154铅垂。在另一实施例中，边缘表面122E自内间隔件152A向外延伸。
返回参看图2，亦参看图10，在实例操作280中，使用磊晶制程使半导体区域130形成于孔620内。具体而言，半导体区域130经形成邻接内间隔件152A(及视情况亦邻接152B)，且接触后退的半导体纳米线条414的边缘表面122E，其自内间隔件152A暴露。
在半导体纳米线条414为硅的情况下，元件配置为nMOS，且半导体区域130为碳化硅(SiC)、碳磷化硅(SiCP)、磷化硅(SiP)或其他合适半导体材料。在硅锗的纳米线条412保留为半导体纳米线条的情况下，元件配置为pMOS，且半导体区域130为硅锗(SiGe)或硅锗硼(SiGeB)或其他合适半导体材料。半导体区域130可以具有各种掺杂剂/杂质(诸如砷、磷、硼、镓、铟、锑、氧、氮或其各种组合)的各种方法进行掺杂。
在实施例中，半导体区域130经形成以接触半导体纳米线条414的每一经暴露的边缘表面122E。
返回参看图2，亦参看图11，在实例操作290中，移除后退的牺牲纳米线条412R及牺牲栅极结构510，留下孔隙1110。进行选择性蚀刻程序以移除后退的牺牲条412R而保留后退的半导体纳米线条414。选择性蚀刻不可避免地亦自半导体纳米线条414的第二区段414(2)(图8)移除一部分414SS(以虚线展示)。归因于内间隔件152A的圆顶形部分154，部分414SS的移除形成了后退的半导体纳米线条414的环形区段414(3)及中心区段414(4)。中心区段414(4)包括比环形区段414(3)小的直径。因此，后退的半导体纳米线条414变成图1B的纳米线结构122，其各自包括边缘区段124、环形区段126及中心区段128(图1B)。
返回参看图2，亦参看图12，在实例操作295中，包括栅电极142及栅极介电质144的替代栅极结构140形成于孔隙1110内。替代栅极结构140缠绕纳米线堆叠120的半导体纳米线条122。
由于半导体纳米线结构122的边缘表面122E与内间隔件152A的形成同时或在内间隔件152A的形成之后暴露，所以边缘表面122不被内间隔件152A的介电层覆盖。因而，半导体纳米线结构122(经配置作为通道区域)及源极/漏极区域130之间的接合面为欧姆接触且接触电阻低。
图12展示结构110的一个实例实施例，其不限制本揭露的范畴。在不改变本揭露的原理的情况下，其他实施例可包括一些变体结构特征。举例而言，图13展示替代及/或额外结构100’。在结构100’中，半导体条122中的一些不自内间隔件152(或具体言之为第一区段152A)暴露。举例而言，在结构100’中，上方位准半导体条122U在形成内间隔件152形成之前后退且被内间隔件152覆盖。上方位准的半导体条122U可与牺牲条412中的一些一起后退或可与牺牲条412分开后退。上方位准的半导体条122U的后退可基于制造过程设计及/或产品/元件设计实施。
图14展示另一替代及/或额外结构100”。在结构100”中，半导体条122不后退以大体上与内间隔件152铅垂且保持向外延伸超过外间隔件150及/或内间隔件152。源极/漏极区域130经形成而环绕或缠绕半导体条122。
其他变体亦为可能的且包括于本揭露中。另外，实施例及其组件可以各种方式进行组合，其亦包括在本揭露中。
通过以下实施例的描述可进一步了解本揭露。
在元件实施例中，一种元件包括基板、通道区域、源极/漏极结构、栅极结构与内间隔件结构。通道区域包括在基板之上的纳米线结构的堆叠，纳米线结构的堆叠包括第一纳米线结构，纳米线结构包括在第一纳米线结构的边缘处的第一区段及邻接第一区段的第二区段，第二区段具有大于第一区段的一直径。源极/漏极结构邻接与接触第一纳米线结构的第一区段。栅极结构缠绕第一纳米线结构。内间隔件结构侧向上在源极/漏极结构及栅极结构之间。
在一些实施例中，源极/漏极结构侧向接触第一纳米线结构的边缘部分。
在一些实施例中，内间隔件结构大体上为圆顶形，且具有顶尖侧向指向该栅极结构。
在一些实施例中，内间隔件结构大体上为帽形，且具有凸起顶面指向栅极结构。
在一些实施例中，纳米线结构的堆叠还包括在第一纳米线结构之下的第二纳米线结构，第二纳米线结构包括第一区段及第二区段，其中第二区段具有大于第一区段的直径，且源极/漏极结构侧向接触第二纳米线结构的边缘部分。
在一些实施例中，基板包括在纳米线结构的该堆叠之下的鳍结构。
在一些实施例中，元件还包含邻接栅极结构且在纳米线结构的堆叠之上的外间隔件，且其中内间隔件结构延伸超过外间隔件的外表面。
在一些实施例中，外间隔件包括与内间隔件结构的介电材料不同的介电材料。
在一些实施例中，纳米线结构的堆叠为维硅或维硅锗中的一者。
在一些实施例中，源极/漏极结构包括碳化硅、碳磷化硅、磷化硅、硅锗或硅锗硼中的一者。
在另一实施例中，一种半导体结构包括基板、多个单独半导体纳米线条、半导体磊晶区域、栅极结构与第一介电结构。单独半导体纳米线条垂直堆叠于基板之上。半导体磊晶区域邻接且侧向接触多个单独半导体纳米线条中的每一者。栅极结构至少部分地在单独半导体纳米线条之上。第一介电结构侧向上在半导体磊晶区域及栅极结构之间，第一介电结构具有帽形轮廓。
在一些实施例中，第一介电结构具有指向栅极结构的顶尖。
在一些实施例中，第一介电结构及单独半导体纳米线条大体上彼此铅垂。
在一些实施例中，单独半导体纳米线条各自包括第一区段及第二区段，其中第一区段具有小于第二区段的直径。
在一些实施例中，半导体结构还包含在第一介电结构之上且邻接栅极结构的第二介电结构，第二介电结构包括与第一介电结构的介电材料不同的介电材料。
在一些实施例中，第一介电结构的介电材料具有高于第二介电结构的介电材料的介电常数。
在一些实施例中，第一介电结构的介电常数高于第二介电结构的介电常数的约三倍。
在另一实施例中，一种方法包括接纳晶圆，晶圆包括在基板之上的磊晶层的堆叠，磊晶层的堆叠包括以交替顺序堆叠的多个半导体磊晶层及多个牺牲磊晶层；通过图案化晶圆形成鳍结构，鳍结构包括多个半导体条及多个牺牲条的堆叠；在鳍结构之上形成牺牲栅极结构及外间隔件，牺牲栅极结构接触鳍结构的至少三个表面；通过移除侧向延伸超过外间隔件的牺牲条的部分形成后退的牺牲条，而半导体条保持侧向延伸超过外间隔件；形成在侧向上邻接后退的牺牲条的内间隔件；通过使半导体条后退而形成半导体条的经暴露的边缘表面；形成半导体层，其邻接内间隔件且接触半导体条的经暴露的边缘表面；通过移除牺牲栅极及后退的牺牲条而形成开放间隔；以及在开放间隔内形成替代栅极。
在一些实施例中，半导体条的经暴露的边缘表面在与形成内间隔件同时或在形成内间隔件之后中的一者情况下形成。
在一些实施例中，后退的牺牲条各自包括在其边缘部分上的凹槽。
前文概述了若干实施例的特征，使得熟悉此项技术者可较佳理解本揭露的态样。熟悉此项技术者应了解，其可容易地使用本揭露作为设计或修改用于实现相同目的及/或达成本文中所介绍的实施例的相同优势的其他制程及结构的基础。熟悉此项技术者亦应认识到，此等等效构造不脱离本揭露的精神及范畴，且其可在不脱离本揭露的精神及范畴的情况下于本文中进行各种改变、代替及替换。

Claims (20)

1.一种纳米线堆叠栅极全环绕元件，其特征在于，包含：
一基板；
一通道区域，包括在所述基板之上的纳米线结构的一堆叠，纳米线结构的该堆叠包括一第一纳米线结构，该纳米线结构包括在该第一纳米线结构的一边缘处的一第一区段、邻接该第一区段的一第二区段、及一中心区段，该第二区段位于该第一区段与该中心区段之间且具有大于该第一区段与该中心区段的一直径；
一源极/漏极结构，邻接与接触该第一纳米线结构的该第一区段；
一栅极结构，缠绕该第一纳米线结构；以及
一内间隔件结构，侧向上在该源极/漏极结构及该栅极结构之间。
2.如权利要求1所述的纳米线堆叠栅极全环绕元件，其特征在于，其中该源极/漏极结构侧向接触该第一纳米线结构的一边缘部分。
3.如权利要求1所述的纳米线堆叠栅极全环绕元件，其特征在于，其中该内间隔件结构大体上为圆顶形，且具有一顶尖侧向指向该栅极结构。
4.如权利要求1所述的纳米线堆叠栅极全环绕元件，其特征在于，其中该内间隔件结构大体上为帽形，且具有一凸起顶面指向该栅极结构。
5.如权利要求1所述的纳米线堆叠栅极全环绕元件，其特征在于，其中纳米线结构的该堆叠还包括在该第一纳米线结构之下的一第二纳米线结构，该第二纳米线结构包括一第一区段及一第二区段，其中该第二区段具有大于该第一区段的一直径，且该源极/漏极结构侧向接触该第二纳米线结构的一边缘部分。
6.如权利要求1所述的纳米线堆叠栅极全环绕元件，其特征在于，其中该基板包括在该纳米线结构的该堆叠之下的一鳍结构。
7.如权利要求1所述的纳米线堆叠栅极全环绕元件，其特征在于，还包含邻接该栅极结构且在该纳米线结构的该堆叠之上的一外间隔件，且其中该内间隔件结构延伸超过该外间隔件的一外表面。
8.如权利要求7所述的纳米线堆叠栅极全环绕元件，其特征在于，其中该外间隔件包括与该内间隔件结构的介电材料不同的一介电材料。
9.如权利要求1所述的纳米线堆叠栅极全环绕元件，其特征在于，其中该纳米线结构的该堆叠为一维硅或一维硅锗中的一者。
10.如权利要求1所述的纳米线堆叠栅极全环绕元件，其特征在于，其中该源极/漏极结构包括碳化硅、碳磷化硅、磷化硅、硅锗或硅锗硼中的一者。
11.一种半导体结构，其特征在于，包含：
一基板；
多个单独半导体纳米线条，垂直堆叠于该基板之上，该多个单独半导体纳米线条各包括一边缘区段、邻接该边缘区段的一环形区段、及一中心区段，该环形区段位于该边缘区段与该中心区段之间且具有大于该边缘区段与该中心区段的一直径；
一半导体磊晶区域，邻接且侧向接触该多个单独半导体纳米线条中的每一者；
一栅极结构，至少部分地在该多个单独半导体纳米线条之上；以及
一第一介电结构，侧向上在该半导体磊晶区域及该栅极结构之间，该第一介电结构具有一帽形轮廓。
12.如权利要求11所述的半导体结构，其特征在于，其中该第一介电结构具有指向该栅极结构的一顶尖。
13.如权利要求11所述的半导体结构，其特征在于，其中该第一介电结构及该多个单独半导体纳米线条大体上彼此铅垂。
14.如权利要求11所述的半导体结构，其特征在于，其中该多个单独半导体纳米线条各自包括一第一区段及一第二区段，其中该第一区段具有小于该第二区段的一直径。
15.如权利要求11所述的半导体结构，其特征在于，还包含在该第一介电结构之上且邻接该栅极结构的一第二介电结构，该第二介电结构包括与该第一介电结构的介电材料不同的一介电材料。
16.如权利要求15所述的半导体结构，其特征在于，其中该第一介电结构的该介电材料具有高于该第二介电结构的该介电材料的一介电常数。
17.如权利要求16所述的半导体结构，其特征在于，其中该第一介电结构的该介电常数高于该第二介电结构的该介电常数的三倍。
18.一种纳米线堆叠栅极全环绕的制造方法，其特征在于，包含：
接纳一晶圆，该晶圆包括在一基板之上的磊晶层的一堆叠，磊晶层的该堆叠包括以一交替顺序堆叠的多个半导体磊晶层及多个牺牲磊晶层；
通过图案化该晶圆形成一鳍结构，该鳍结构包括多个半导体条及多个牺牲条的一堆叠；
在该鳍结构之上形成一牺牲栅极结构及一外间隔件，该牺牲栅极结构接触该鳍结构的至少三个表面；
通过移除侧向延伸超过该外间隔件的该多个该牺牲条的部分形成后退的牺牲条，而该多个半导体条保持侧向延伸超过该外间隔件；
形成在侧向上邻接该后退的牺牲条的一内间隔件；
通过使该多个半导体条后退而形成该多个半导体条的经暴露的边缘表面；
形成一半导体层，其邻接该内间隔件且接触该多个半导体条的该经暴露的边缘表面；
通过移除该牺牲栅极及该后退的牺牲条而形成一开放间隔；以及
在该开放间隔内形成一替代栅极。
19.如权利要求18所述的纳米线堆叠栅极全环绕的制造方法，其特征在于，其中该多个半导体条的该经暴露的边缘表面在与形成该内间隔件同时或在形成该内间隔件之后中的一者情况下形成。
20.如权利要求18所述的纳米线堆叠栅极全环绕的制造方法，其特征在于，其中该后退的牺牲条各自包括在其一边缘部分上的一凹槽。
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