US20230387265A1 - Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same - Google Patents
Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same Download PDFInfo
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- US20230387265A1 US20230387265A1 US18/366,297 US202318366297A US2023387265A1 US 20230387265 A1 US20230387265 A1 US 20230387265A1 US 202318366297 A US202318366297 A US 202318366297A US 2023387265 A1 US2023387265 A1 US 2023387265A1
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Definitions
- CMOS transistors are building blocks for integrated circuits. Faster CMOS switching speed requires higher drive current, which drives the gate lengths of CMOS transistors down. Shorter gate lengths lead to undesirable “short-channel effects,” in which the current control functions of the gates are compromised. FinFET transistors have been developed to, among other things, overcome the short-channel effects. As a further step toward improving electrostatic control of the channels, transistors having wrapped-around gates have been developed, in which a gate portion may surround a semiconductor channel or channel strip from the upper surface and sidewalls thereof.
- FIGS. 1 A- 1 C are perspective views and cross-sectional views of an example device according to example embodiments of the disclosure.
- FIGS. 1 D- 1 E are cross-sectional views of embodiments of an inner spacer of the example device of FIGS. 1 A- 1 C ;
- FIG. 2 is a flow chart of an example fabrication process according to example embodiments of the disclosure.
- FIGS. 3 A- 12 are prospective views and cross-sectional views of various stages of making the example device of FIGS. 1 A- 1 C according to example embodiments of the disclosure.
- FIGS. 13 and 14 show alternative and/or additional embodiments of example devices according to example embodiments of the disclosure.
- the current disclosure describes techniques for a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device.
- a stack of nanowire strips are formed including silicon nanowire strips and silicon germanium nanowire strips stacked alternatively.
- a dummy gate structure is formed over and surrounding the stack of nanowire strips.
- the silicon germanium (or the silicon) nanowire strips are used as sacrificial strips and the silicon (or silicon germanium) nanowire strips are used as the semiconductor body or channel of the FET device, and is referred to as “semiconductor nanowire strips.”
- the sacrificial strips are selectively receded with the semiconductor nanowire strips remaining. Inner spacers are formed laterally adjacent to the receded sacrificial strips.
- the semiconductor nanowire strips are receded simultaneously with or after the inner spacers are formed such that it is ensured that edge surfaces of the receded semiconductor nanowire strips are exposed from the inner spacers.
- Source/drain regions are formed through epitaxy procedures, contact each of the exposed edge surfaces of the receded semiconductor nanowire strips. Ohmic junctions between the source/drain region and the channel region (i.e., the receded semiconductor nanowire strips) are ensured because the edge surfaces of the receded semiconductor nanowire strips are not covered by the dielectric material of the inner spacer.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- ordinals such as first, second and third does not necessarily imply a ranked sense of order, but rather may only distinguish between multiple instances of an act or structure.
- the gate all around (GAA) transistor structures may be patterned by any suitable method.
- the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes.
- double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.
- a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.
- FIG. 1 A is a perspective view of a device 100 .
- the device 100 includes a substrate 110 that includes a lower fin structure 112 .
- a stack 120 of discrete nanowire structures 122 (“nanowire stack 120 ”) are formed over the substrate no and more specifically, in an embodiment, over the lower fin structure 112 of the substrate 110 .
- the nanowire stack 120 includes multiple nanowire structures 122 , e.g., nanowire strips, that are stacked vertically, in the z direction, over one another.
- Two source/drain structures 130 are formed adjacent to and contacting at least some of the nanowire structures 122 by edge surfaces 122 E of the contacted nanowire structures 122 . Note that in FIG. 1 A , one of the source/drain structure 130 is omitted to show the nanowire stack 120 , for illustrative purposes. It should be appreciated that in the final device 100 , the nanowire stack 120 is not exposed.
- Agate structure 140 is formed over the substrate 110 .
- the gate structure 140 includes a gate electrode 142 and a gate dielectric layer 144 .
- the gate structure 140 is separated from the source/drain structure 130 by at least one of an outer spacer structure 150 and an inner spacer structure 152 .
- the inner spacer structure 152 is formed laterally between the source/drain structure 130 and the gate structure 140 in the x axis direction.
- One or more insulation layers 160 , 162 are formed adjacent to the source/drain structure 130 and/or the gate structure 140 .
- the insulation layers 160 , 162 include silicon oxide or other suitable dielectric materials. Note that in FIG. 1 A , some portions of the insulation layers 160 , 162 are omitted to show the source/drain structure 130 and/or the nanowire stack 120 , for illustrative purposes only.
- the insulation layers 160 , 162 may be a single layer of a dielectric material, two separately formed layers of a same dielectric material or two layers of different dielectric materials.
- FIG. 1 A shows, as an illustrative example, that the source/drain structure 130 is formed such that an upper surface 132 of the source/drain structure 130 is substantially at a same level as that of the gate structure 140 .
- This example is not limiting.
- the source/drain structure 130 is higher or lower than the gate structure 140 , which are all included in the disclosure.
- the nanowire structures 122 that contact the source/drain structure 130 are configured as a channel region(s) of the device 100 .
- the substrate 110 may include a silicon substrate in crystalline structure and/or other elementary semiconductors like germanium. Alternatively or additionally, the substrate 110 may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, and/or indium phosphide. Further, the substrate 110 may also include a silicon-on-insulator (SOI) structure. Substrate 110 may include an epitaxial layer and/or may be strained for performance enhancement. The substrate 110 may also include various doping configurations depending on design requirements such as P-type substrate and/or N-type substrate and various doped regions such as P-wells and/or N-wells.
- SOI silicon-on-insulator
- the gate structure 140 is formed as a replacement gate.
- the following description lists examples of materials for the gate structure 140 including the gate electrode 142 and the gate dielectric 144 , which are non-limiting.
- the gate electrode 142 includes a conductive material, e.g., a metal or a metal compound.
- Suitable metal materials for the gate electrode 142 include ruthenium, palladium, platinum, tungsten, cobalt, nickel, and/or conductive metal oxides and other suitable P-type metal materials and include hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), aluminides and/or conductive metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), and other suitable materials for N-type metal materials.
- the gate electrode 142 includes a work function layer tuned to have a proper work function for enhanced performance of the field effect transistor devices.
- suitable N-type work function metals include Ta, TiAl, TiAlN, TaCN, other N-type work function metal, or a combination thereof
- suitable P-type work function metal materials include TiN, TaN, other P-type work function metal, or combination thereof.
- a conductive layer such as an aluminum layer, a copper layer, a cobalt layer or a tungsten layer is formed over the work function layer such that the gate electrode 142 includes a work function layer disposed over the gate dielectric 144 and a conductive layer disposed over the work function layer and below a gate cap (not shown for simplicity).
- the gate electrode 142 has a thickness ranging from about 5 nm to about 40 nm depending on design requirements.
- the gate dielectric layer 144 includes an interfacial silicon oxide layer (not separately shown for simplicity), e.g., thermal or chemical oxide having a thickness ranging from about 5 to about 10 angstrom (A).
- the gate dielectric layer 144 further includes a high dielectric constant (high-K) dielectric material selected from one or more of hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), combinations thereof, and/or other suitable materials.
- hafnium oxide HfO 2
- hafnium silicon oxide HfSiO
- hafnium silicon oxynitride HfSiON
- hafTaO hafnium tantalum oxide
- HfTiO hafnium titanium oxide
- a high K dielectric material in some applications, includes a dielectric constant (K) value larger than 6. Depending on design requirements, a dielectric material of a dielectric contact (K) value of 7 or higher is used.
- the high-K dielectric layer may be formed by atomic layer deposition (ALD) or other suitable technique.
- the high-K dielectric layer of the gate dielectric layer 144 includes a thickness ranging from about 10 to about 30 angstrom (A) or other suitable thickness.
- the outer spacer 150 is formed of a low K dielectric material such as silicon oxynitride (SiO x N y ), silicon nitride (Si 3 N 4 ), silicon monoxide (SiO), silicon oxynitrocarbide (SiONC), silicon oxycarbide (SiOC), vacuum and other dielectrics or other suitable materials.
- the outer spacer 150 may be formed through chemical vapor deposition (CVD), high density plasma CVD, spin-on, sputtering, or other suitable approaches.
- the inner spacer 152 is formed of a high K dielectric material, e.g., higher dielectric constant than that of the outer spacer 150 .
- the high K material for the inner spacer 152 includes one or more of silicon nitride Si 3 N 4 , silicon carbide (SiC), hafnium oxide (HfO 2 ) or other suitable high K dielectric material.
- the K value of the inner spacer 152 material is between about three to four times of the K value of the outer spacer 150 material.
- the inner spacer 152 also includes one or more air gaps adjacent to one or more of the gate structure 140 or the source/drain structure 130 .
- the inner spacer 152 includes a first segment 152 A formed between the gate structure 140 and the source/drain structure 130 and adjacent to a channel region (nanowire strip) 122 .
- the inner spacer structure 152 also includes a second segment 152 B that extends upward adjacent the outer spacer 150 .
- the second segment 152 B of the inner spacer 152 is further away from the channel region 122 than the first segment 152 A.
- a portion of the source/drain structure 130 may be separated from the gate structure 140 by both the inner spacer 152 , specifically the second segment 152 B of the inner spacer 152 , and the outer spacer 150 .
- the first segment 152 A is hat-shaped with a convex top of the hat shape pointing to the gate structure 140 .
- FIG. 1 B is a cross-sectional view of the device 100 from cutting-line B-B.
- the gate structure 140 is adjacent to the nanowire stack 122 at least three surfaces of the nanowire stack 120 , i.e., the upper surface and the side surfaces.
- FIG. 1 B shows that the gate structure 140 wraps around one or more of the individual nanowire structures 122 .
- both the gate electrode 142 and the gate dielectric 144 wrap around an individual nanowire structure 122 , which is not limiting. It is possible that only the gate dielectric 144 wraps around an individual nanowire structure 122 and the gate electrode 142 is adjacent to three surfaces of the nanowire stack 120 as a whole.
- a nanowire structure 122 includes an edge segment (first segment) 124 and a ring portion 126 (second segment) adjacent to the edge segment 124 .
- the ring segment 126 has a larger diameter than the edge segment 124 .
- the nanowire structure 122 also includes a center segment 128 that has a diameter smaller than the diameter of the ring segment 126 .
- Other shapes or profiles of the nanowire structure 122 are also possible and included in the disclosure.
- the first segment 152 A of the inner spacer structure 152 “inner spacer 152 A” includes a substantially dome-shaped profile.
- a dome-shaped profile includes all profiles that have a larger base and a smaller apex.
- a cone shape or a pyramid shape or other similar shapes are all included in the “dome-shaped profile” as used in this disclosure.
- the apex of the dome-shaped inner spacer 152 A is oriented toward the gate structure 140 .
- the dome-shaped profile may include more than one apexes and include a concave portion between two apexes.
- FIG. 1 D shows an enlarged cross-sectional view of the inner spacer 152 A taken from FIG. 1 B .
- the inner spacer 152 A includes a substantially hat-shaped profile, with the convex top of the hat shape pointing to the gate structure 140 .
- the hat-shaped profile includes a convex portion, e.g., a dome-shaped portion, 154 and a brim-shaped portion 156 projecting from dome-shaped portion 154 .
- the dome-shaped portion 154 and the brim-shaped portion 156 meet at an interface 158 .
- the dome-shaped portion 154 smoothly transit into the brim-shaped portion 126 and the first segment 152 A thus overall includes a dome-shaped profile.
- FIG. 1 E includes alternative or additional profile embodiments of the inner spacer 152 A from a cross-sectional view.
- Example I shows that the inner spacer 152 A may include a cone-shaped head portion proximal to the gate structure 140 and a base portion distal to the gate structure 140 .
- Example II shows that the inner spacer 152 A may include a dome-shaped head portion proximal to the gate structure 140 and a distal base portion.
- Example III shows that the inner spacer 152 A may include a multidome-shaped head portion proximal to the gate structure 140 and a distal base portion.
- Example IV shows that the inner spacer 152 a may include a continuous shape from the proximal end (with respect to the gate structure 140 ) to the distal end.
- Example I-IV show various profiles of the head portion with the base portion extending from the head portion.
- the edge surface of the base portion is substantially plumb or vertical.
- Examples V-VIII show various examples where the edge surface of the base portion includes an indentation or recess toward the gate structure 140 .
- Examples V-VIII show that the base portion is minimized to become a recessed base surface, which is not limiting.
- the recessed base surface may also exists in a scenario that the base portion extends away from the head portion.
- the brim-shaped portion 156 of FIG. 1 D may also include a recess base surface.
- the source/drain structure 130 extends continuously downward from a nanowire structure 122 that is stacked higher in the nanowire stack 120 (“higher nanowire structure 122 ”) to a nanowire structure 122 that is stacked lower in the nanowire stack 120 (“lower nanowire structure 122 ”).
- the source/drain structure 130 contacts the higher nanowire structure 122 and the lower nanowire structure 122 by the edge surfaces 122 E thereof, respectively.
- all the nanowire structure 122 contacts the source/drain structure 130 , which is not limiting. In other scenarios, depending on fabrication process and product design, some of the nanowire structures 122 , e.g., those stacked on the top of the nanowire stack 120 , do not contact the source/drain structure 130 .
- the inner spacer structure 150 may be formed between a topmost nanowire structure 122 and the source/drain structure 130 .
- FIG. 1 C is a cross-sectional view of the device 100 from cutting-line C-C in FIG. 1 A .
- multiple nanowire structures 122 of the nanowire stack 120 are wrapped around or surround by the gate structure 140 .
- the nanowire structures 122 are each surrounded directly by the gate dielectric 144 , which is positioned between the gate electrode 142 and the nanowire structure 122 .
- the nanowire stack 120 is formed over the lower fin structure 112 of the substrate 110 and overlaps the lower fin structure 112 .
- FIG. 1 C shows, as an illustrative example, that the lowest nanowire structure 122 of the nanowire stack 120 is separated from the lower fin structure 112 of the substrate 110 , which is not limiting. In other embodiments, depending on the design requirements, the lowest nanowire structure 122 contacts the lower fin structure 112 . That is, the bottom surface (or lower surface) 129 of the lowest nanowire 122 in the nanowire stack 120 may not be adjacent to the gate structure 140 . For example, in the scenario that the nanowire structure 122 and the substrate 110 are formed of a same semiconductor material, e.g., silicon, it may meet some design requirements to have the lowest nanowire structure 122 contact the lower fin portion 112 .
- FIG. 2 is an example fabrication process 200 , which could be used to make the example device 100 sown in FIGS. 1 A- 1 D , and other devices.
- FIGS. 3 - 12 show stages of a wafer 300 in a process of making the example device 100 .
- one or more of three views of the wafer 300 are shown, i.e., the perspective view referenced with letter “A”, a sectional view from cutting line B-B, referenced with letter “B” and also referred to as “B” plane (X-Z plane), and a sectional view from cutting line C-C, referenced with letter “C” and also referred to as “C” plane.
- the reference letter of the respective view will be omitted for simplicity.
- FIGS. 3 A- 3 C illustrate the wafer 300 .
- the wafer 300 includes a substrate no, e.g., of silicon, silicon germanium, and/or other suitable semiconductor materials.
- the substrate no may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, and/or indium phosphide.
- the substrate no may also include a silicon-on-insulator (SOI) structure.
- SOI silicon-on-insulator
- a vertical stack of epitaxy layers 312 , 314 of different materials are formed over the substrate no and are stacked in an alternating sequence, i.e., each epitaxy layer 312 , 314 is immediately and vertically adjacent to a different one of the epitaxy layers 314 , 312 .
- FIGS. 3 A- 3 C show, as an illustrative example, that totally four epitaxy layers 312 and five epitaxy layers 314 are stacked over the substrate 110 , which is not limiting. Other numbers of the epitaxy layers 312 , 314 are also possible and included in the disclosure.
- the wafer 300 includes a same number of the epitaxy layers 312 as the epitaxy layers 314 .
- the wafer 300 includes a different number of the epitaxy layers 312 from that of the epitaxy layers 314
- the epitaxy layers 312 are formed of a first semiconductor material and the epitaxy layers 314 are formed of a second semiconductor material different from the first semiconductor material.
- the first semiconductor material and the second semiconductor material have different etching rates with respect to some etchants, i.e., having etching selectivity, such that a selective etching may be conducted to remove one of the epitaxy layers 312 , 314 with the other one remaining.
- the epitaxy layer 312 is silicon germanium of Si x Ge 1-x , with x being greater than 0 and smaller than 1, and in some embodiments between about 0.4 and about 0.9.
- the epitaxy layer 314 is silicon.
- the epitaxy layers 312 , 314 each may be doped in various approaches with various dopants/impurities, like arsenic, phosphorous, boron, gallium, indium, antimony, oxygen, nitrogen, or various combinations thereof.
- the epitaxy layers 312 , 314 each are sheets of nanowire silicon germanium or nanowire silicon, respectively, and are referred to as nanosheets 312 , 314 .
- Each of the nanosheets 312 , 314 may include a thickness between about 4 nm to about 20 nm.
- the nanosheets 312 , 314 each may include a thickness between about 5 nm to about 8 nm.
- the epitaxy layers 312 , 314 may also be other semiconductor materials.
- Epitaxy layers 312 , 314 may be formed using the vapor-liquid-solid (VLS) technique or other suitable growth procedures.
- VLS vapor-liquid-solid
- the nanosheets 314 , 312 of 1-D nanowire silicon or silicon germanium, respectively, are used as illustrative examples in the description of the disclosure.
- the nanosheets 312 , 314 may be globally formed over the substrate 110 or may be locally formed over the substrate 110 . In a local formation procedure, the nanosheets 312 , 314 are formed within an area defined by shallow trench insulation (STI) regions and/or is formed over a doped substrate region, e.g., a P-well or an N-well.
- STI shallow trench insulation
- a fin structures 402 are formed by patterning the wafer 300 . Any suitable patterning procedures may be used and all are included in the disclosure.
- the fin structure 402 includes two portions, an upper portion 410 and a lower portion 112 .
- the lower portion 112 is formed from patterning the substrate 110 , e.g., of silicon, and is also part of the substrate 110 and is referred to as the “substrate” or the “lower fin portion” or the “lower portion” of the fin, as scenarios apply.
- the upper portion 410 is formed from patterning the stacked epitaxy layers 312 , 314 .
- the upper fin portion 410 includes nanowires silicon germanium strips 412 , and nanowire silicon strips 414 vertically stacked in an alternating manner.
- the upper fin portion 410 including the stack of the nanowire strips 412 , 414 are also referred to as nanowire stack 410 .
- the nanowire stack 410 is different from the nanowire stack 120 of device 100 shown in FIGS. 1 A- 1 C because one group of the nanowire strips 412 , 414 will be removed as sacrificial strips, as described herein.
- the nanowire strips 412 or the nanowire strips 414 will be removed from the nanowire stack 410 and are referred to as the “sacrificial strips”.
- the nanowire strips 412 , 414 that remain on the nanowire stack 410 are referred to as the “semiconductor nanowire strips.”
- the silicon germanium nanowire strips 412 are removed as sacrificial strips and the silicon nanowire strips 414 remain to eventually become the nanowire structures 122 of the nanowire stack 120 of device 100 .
- An insulation layer 160 is formed over the substrate 110 and adjacent to the fin structures 402 , as shown in FIG. 4 A (in FIG. 4 A , a portion of the insulation layer 160 is omitted for illustrative purposes) and FIG. 4 C .
- the insulation layer 160 is silicon oxide or other suitable dielectric material.
- an etch stop layer 420 is formed between the insulation layer 160 and the substrate 110 including the lower portion 112 of the fin structure 402 .
- the etch stop layer 420 is a different dielectric material from the insulation layer 160 .
- the etch stop layer 420 is silicon nitride or other suitable dielectric materials.
- the insulation layer 160 and the etch stop layer 420 are adjacent only to the lower fin portion 112 , and the upper fin portion 410 is exposed from the insulation layer 160 and the etch stop layer 420 .
- a sacrificial or dummy gate structure 510 is formed over the substrate 110 and adjacent to or surround three surfaces of the upper fin portion 410 , i.e., two side surfaces 420 S and an upper surface 410 U.
- the sacrificial gate structure 510 may include a sacrificial polysilicon layer 512 , a sacrificial cap layer (not shown for simplicity), and a sacrificial liner layer (not shown for simplicity).
- the sacrificial cap layer and the sacrificial liner layer may be silicon oxide or other suitable dielectric materials.
- the total height of the sacrificial gate structure 510 may be higher or substantially equal to, but not lower than, the replacement gate that is to be made in the space occupied by the sacrificial gate structure 510 .
- An outer spacer 520 is formed adjacent to the sacrificial gate structure 510 .
- the outer spacer 520 may be silicon nitride or other suitable dielectric materials.
- the outer spacer 150 is formed of a low K dielectric material such as silicon oxynitride, silicon nitride (Si 3 N 4 ), silicon monoxide (SiO), silicon oxynitrocarbide (SiONC), silicon oxycarbide (SiOC), silicon mononitride (SiN), vacuum and other dielectrics or other suitable materials.
- the outer spacer 520 may be formed through chemical vapor deposition (CVD), high density plasma CVD, spin-on, sputtering, or other suitable approaches.
- the nanowire strips 412 , 414 each laterally extend beyond the outer spacer 520 in the x-axis direction.
- an insulation layer 162 is formed adjacent to the outer spacer 520 .
- the insulation layer 162 may include a same dielectric material as the insulation layer 160 or may be a different dielectric material.
- the insulation layer 162 is omitted from FIG. 5 A for illustrative purposes.
- FIGS. 6 - 12 show B plane view of the wafer 300 in the various fabrication stages.
- a trench or aperture 620 is formed within the insulation layer 162 to expose the nanowire stack 410 by each side of the outer spacer 520 .
- a portion 622 of the outer spacer 520 that overlaps the nanowire stack 410 is also exposed.
- FIG. 6 shows that the aperture 620 stops substantially at the level of the topmost nanowire strip, here the sacrificial nanowire strip 412 of silicon germanium, which is not limiting.
- a portion of one or more of the top nanowire strips 412 , 414 may be removed. That is, the aperture 620 may extend downward beyond the upper surface 410 U of the nanowire stack 410 .
- a selective etching is conducted through the apertures 620 to selectively remove the sacrificial nanowire strips 412 of silicon germanium exposed from the apertures 620 and to leave the semiconductor nanowire strip 414 of silicon remain within the aperture 620 .
- an ammonia solution of ammonium hydroxide “NH 4 OH” or other suitable etchants are used to selectively etch out the sacrificial nanowire strips 412 .
- a hydrochloric acid solution “HCL” or other etchants is used to selectively etch out the nanowire strips 414 and while leaving the nanowire strips 412 of silicon germanium in place.
- a selective wet etching is performed to remove the sacrificial nanowire strips 412 (or 414 ) such that a recess 710 is formed on the edge portions 712 of the sacrificial nanowire strips 412 that remain below the sacrificial gate structure 510 and the outer spacer 150 , which is referred to herein as “receded sacrificial strip 412 R” for descriptive purposes.
- the etching conditions are controlled such that the edge portions 712 of the remaining sacrificial strips 412 R recede inward beyond the outer surface 720 of the outer spacer 150 .
- the outermost points 714 of the edge portions 712 are positioned between the outer surface 720 and the inner surface 722 of the outer spacer 150 .
- the receding of the sacrificial strips 412 unavoidably also removes a small portion 414 S (shown in dotted line) of the semiconductor nanowire strips 414 .
- a first segment 414 ( 1 ) of the nanowire strip 414 that is exposed within the aperture 620 includes a smaller diameter than a second segment 414 ( 2 ) that is below the sacrificial gate structure 510 and is not exposed within the aperture 620 .
- This structural characteristic of this stage of the wafer is enabled by the sequence of the fabrication process that the sacrificial strips 412 are selectively removed while the semiconductor nanowire strips 414 remain.
- This structural characteristic that the segment 414 ( 1 ) includes a smaller diameter than the second segment 414 ( 2 ) also affects the shapes of the other structural features, like the inner spacer 152 A of FIG. 1 D , as described herein.
- a dielectric layer 810 is formed adjacent to the edge portions 712 of the receded sacrificial strips 412 R that remains below the sacrificial gate structure 510 .
- the dielectric layer 810 at least partially fills in the recesses 710 adjacent to the edge portions 712 .
- the dielectric layer 810 does not fully fill the recesses 710 and a gap, either air gap or vacuum gap, is formed between the dielectric layer 810 and the edge portion 712 of the receded sacrificial strip 412 R.
- FIG. 8 ′ shows the gap 812 in an enlarged view.
- the dielectric layer 810 is formed of a dielectric material that has a higher dielectric constant than the outer spacer 520 .
- the dielectric material for the inner spacer 152 includes one or more of silicon nitride Si 3 N 4 , silicon carbide (SiC), hafnium oxide (HfO 2 ) or other suitable dielectric material.
- the K value of the dielectric layer 810 material is between about three to four times of the K value of the outer spacer 520 material.
- the dielectric layer 810 is also formed over the first segment 414 ( 1 ) of the semiconductor nanowire strip 414 .
- inner spacers 152 A are formed by removing extra portions of the dielectric layer 810 through an anisotropic etching.
- a resultant surface 1525 of the inner spacer 152 A which is opposite to the receded sacrificial strip 412 R, is substantially plumb with the outer surface 720 of the outer spacer 520 .
- the surface 152 S is formed outwardly beyond the outer surface 720 of the outer spacer 520 .
- a thin layer 152 B of the dielectric layer 810 remains adjacent to the outer spacer 520 and may become a second segment 152 B of the inner spacer structure 152 ( 152 A+ 152 B).
- the second segment 152 B is technically not an “inner spacer” and is referred to as a second segment of the inner spacer structure 152 only for descriptive purposes.
- the first segment 152 A of the inner spacer 152 “inner spacer 152 A” includes a substantially dome-shaped profile due to filling the recesses 710 .
- a dome-shaped profile includes all profiles that have a larger base and a smaller apex.
- a cone shape or a pyramid shape or other similar shapes are all included in the “dome-shaped profile” as used in this disclosure.
- Other alternative or additional shapes/profiles of the inner spacer 152 or the first segment 152 A are also possible.
- the apex of the dome-shaped inner spacer 152 A is directed toward the receded sacrificial strips 412 R.
- the inner spacer 152 A includes a substantially hat-shaped profile.
- the hat-shaped profile includes a dome-shaped portion 154 and a brim-shaped portion 156 projecting from dome-shaped portion 154 .
- the dome-shaped portion 154 and the brim-shaped portion 156 meet at an interface 158 .
- the interface 158 overlaps with the outermost point 714 of the receded sacrificial strip 412 R (also see FIG. 7 ).
- the dome-shaped portion 154 smoothly transit into the brim-shaped portion 156 and the inner spacer 152 A thus overall includes a dome-shaped profile.
- the semiconductor nanowire strips 414 are receded, through which portions of the first segment 414 ( 1 ) are removed simultaneously with or after the extra portion of the dielectric layer 810 is removed. That is, the edge surfaces 122 E of the plurality of the semiconductor strips are formed one of simultaneously with or after the inner spacer 152 , or specifically the first segment 152 A, is formed. As a result, the edge surfaces 122 E of the receded semiconductor nanowire strips 414 are exposed from the inner spacers 152 A. In an embodiment, the edge surfaces 122 E are substantially plumb with the surfaces 154 of the inner spacers 152 A. In another embodiment, the edge surfaces 122 E extend out from the inner spacers 152 A.
- semiconductor regions 130 are formed within the apertures 620 using epitaxy processes. Specifically, the semiconductor regions 130 are formed adjacent to the inner spacer 152 A (and optionally also 152 B) and contacting the edge surfaces 122 E of the receded semiconductor nanowire strips 414 , which are exposed from the inner spacers 152 A.
- the device is configured as an nMOS and the semiconductor regions 130 are silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon phosphide (SiP) or other suitable semiconductor materials.
- the semiconductor regions 130 are silicon germanium (SiGe) or silicon-germanium-boron (SiGeB) or other suitable semiconductor materials.
- the semiconductor regions 130 may be doped in various approaches with various dopants/impurities, like arsenic, phosphorous, boron, gallium, indium, antimony, oxygen, nitrogen, or various combinations thereof.
- the semiconductor regions 130 are formed to contact each exposed edge surfaces 122 E of the semiconductor nanowire strips 414 .
- example operation 290 the receded sacrificial nanowire strips 412 R and the sacrificial gate structure 510 are removed, leaving a void 1110 .
- a selective etching procedure is done to remove the receded sacrificial strips 412 R with the receded semiconductor nanowire strips 414 remaining.
- the selective etching unavoidably removes also a portion 414 SS (shown in dotted line) from the second segment 414 ( 2 ) ( FIG. 8 ) of the semiconductor nanowire strips 414 .
- the removal of the portions 414 SS forms a ring segment 414 ( 3 ) and a center segment 414 ( 4 ) of the receded semiconductor nanowire strip 414 .
- the center segment 414 ( 4 ) includes a smaller diameter than the ring segment 414 ( 3 ).
- the receded semiconductor nanowire strips 414 become the nanowire structures 122 of FIG. 1 B , which each includes an edge segment 124 , a ring segment 126 , and a center segment 128 ( FIG. 1 B ).
- a replacement gate structure 140 including a gate electrode 142 and a gate dielectric 144 is formed within the void 1110 .
- the replacement gate structure 140 wraps around the semiconductor nanowire strips 122 of the nanowire stack 120 .
- the edge surfaces 122 E of the semiconductor nanowire structures 122 are exposed simultaneously with or after the formation of the inner spacer 152 A, the edge surfaces 122 are not covered by the dielectric layer of the inner spacer 152 A.
- the junction between the semiconductor nanowire structure 122 , configured as the channel region, and the source/drain region 130 is Ohmic and the contact resistance is low.
- FIG. 12 shows one example embodiment of the structure 110 , which does not limit the scope of the disclosure.
- Other embodiments may include some variant structure features without changing the principles of the disclosure.
- FIG. 13 shows an alternative and/or additional structure 100 ′.
- some of the semiconductor strips 122 are not exposed from the inner spacer 152 , or specifically the first segment 152 A.
- an upper level semiconductor strip 122 U is receded before the inner spacer 152 is formed and is covered by the inner spacer 152 .
- the upper level semiconductor strip 122 U may be receded together with some of the sacrificial strips 412 or may be receded separately from the sacrificial strips 412 .
- the receding of the upper level semiconductor strip 122 U may be implemented based on fabrication process design and/or product/device design.
- FIG. 14 shows another alternative and/or additional structure 100 ′′.
- the semiconductor strips 122 are not receded to be substantially plumb with the inner spacer 152 and remain extending outward beyond the outer spacer 150 and/or the inner spacer 152 .
- the source/drain regions 130 are formed surrounding, or wrapping around, the semiconductor strips 122 .
- a device in a device embodiment, includes a substrate, a channel region over the substrate, a source/drain structure adjacent to and contacting the channel region and a gate structure surrounds the channel region.
- the channel region includes a stack of nanowire structures over the substrate.
- the stack of nanowire structures includes a first nanowire structure that includes a first segment at an edge of the first nanowire structure and a second segment adjacent to the first segment with the second portion having a larger diameter than the first segment.
- the source/drain structure is adjacent to and contacts the first segment of the first nanowire structure.
- the gate structure wraps around the first nanowire structure.
- An inner spacer structure is positioned laterally between the source/drain structure and the gate structure.
- a semiconductor structure in another embodiment, includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, a first dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure.
- the first dielectric structure has a hat-shaped profile.
- a method includes receiving a wafer, the wafer including a stack of epitaxy layers over a substrate, the stack of epitaxy layers including a plurality of semiconductor epitaxy layers and a plurality of sacrificial epitaxy layers stacked in an alternating sequence; forming a fin structure by patterning the wafer, the fin structure including a stack of a plurality of semiconductor strips and a plurality of sacrificial strips; forming a sacrificial gate structure and an outer spacer over the fin structure, the sacrificial gate structure contacting at least three surfaces of the fin structure; forming receded sacrificial strips by selectively removing portions of the plurality of the sacrificial strips that extends laterally beyond the outer spacer and leaving the plurality of the semiconductor strips remain extending laterally beyond the outer spacer; forming an inner spacer laterally adjacent to the receded sacrificial strips; forming exposed edge surfaces of the plurality of the semiconductor strips by receding the plurality of
Abstract
The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
Description
- This application is a continuation of U.S. application Ser. No. 17/352,507, filed on Jun. 21, 2021, which is a divisional of U.S. application Ser. No. 16/118,143, filed on Aug. 30, 2018, now U.S. Pat. No. 11,043,578 issued Jun. 22, 2021, each application is hereby incorporated herein by reference.
- Complementary metal oxide semiconductor (CMOS) transistors are building blocks for integrated circuits. Faster CMOS switching speed requires higher drive current, which drives the gate lengths of CMOS transistors down. Shorter gate lengths lead to undesirable “short-channel effects,” in which the current control functions of the gates are compromised. FinFET transistors have been developed to, among other things, overcome the short-channel effects. As a further step toward improving electrostatic control of the channels, transistors having wrapped-around gates have been developed, in which a gate portion may surround a semiconductor channel or channel strip from the upper surface and sidewalls thereof.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. In the drawings, identical reference numbers identify similar elements or acts unless the context indicates otherwise. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIGS. 1A-1C are perspective views and cross-sectional views of an example device according to example embodiments of the disclosure; -
FIGS. 1D-1E are cross-sectional views of embodiments of an inner spacer of the example device ofFIGS. 1A-1C ; -
FIG. 2 is a flow chart of an example fabrication process according to example embodiments of the disclosure; -
FIGS. 3A-12 are prospective views and cross-sectional views of various stages of making the example device ofFIGS. 1A-1C according to example embodiments of the disclosure; and -
FIGS. 13 and 14 show alternative and/or additional embodiments of example devices according to example embodiments of the disclosure. - The current disclosure describes techniques for a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A stack of nanowire strips are formed including silicon nanowire strips and silicon germanium nanowire strips stacked alternatively. A dummy gate structure is formed over and surrounding the stack of nanowire strips. The silicon germanium (or the silicon) nanowire strips are used as sacrificial strips and the silicon (or silicon germanium) nanowire strips are used as the semiconductor body or channel of the FET device, and is referred to as “semiconductor nanowire strips.” The sacrificial strips are selectively receded with the semiconductor nanowire strips remaining. Inner spacers are formed laterally adjacent to the receded sacrificial strips. The semiconductor nanowire strips are receded simultaneously with or after the inner spacers are formed such that it is ensured that edge surfaces of the receded semiconductor nanowire strips are exposed from the inner spacers. Source/drain regions are formed through epitaxy procedures, contact each of the exposed edge surfaces of the receded semiconductor nanowire strips. Ohmic junctions between the source/drain region and the channel region (i.e., the receded semiconductor nanowire strips) are ensured because the edge surfaces of the receded semiconductor nanowire strips are not covered by the dielectric material of the inner spacer.
- The following disclosure provides many different embodiments, or examples, for implementing different features of the described subject matter. Specific examples of components and arrangements are described below to simplify the present description. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, one skilled in the art will understand that the disclosure may be practiced without these specific details. In other instances, well-known structures associated with electronic components and fabrication techniques have not been described in detail to avoid unnecessarily obscuring the descriptions of the embodiments of the present disclosure.
- Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprise” and variations thereof, such as “comprises” and “comprising,” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.”
- The use of ordinals such as first, second and third does not necessarily imply a ranked sense of order, but rather may only distinguish between multiple instances of an act or structure.
- Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
- As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the content clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its sense including “and/or” unless the content clearly dictates otherwise.
- The gate all around (GAA) transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.
-
FIG. 1A is a perspective view of adevice 100. Referring toFIG. 1A , thedevice 100 includes asubstrate 110 that includes alower fin structure 112. Astack 120 of discrete nanowire structures 122 (“nanowire stack 120”) are formed over the substrate no and more specifically, in an embodiment, over thelower fin structure 112 of thesubstrate 110. Thenanowire stack 120 includesmultiple nanowire structures 122, e.g., nanowire strips, that are stacked vertically, in the z direction, over one another. Two source/drain structures 130 are formed adjacent to and contacting at least some of thenanowire structures 122 byedge surfaces 122E of the contactednanowire structures 122. Note that inFIG. 1A , one of the source/drain structure 130 is omitted to show thenanowire stack 120, for illustrative purposes. It should be appreciated that in thefinal device 100, thenanowire stack 120 is not exposed. -
Agate structure 140 is formed over thesubstrate 110. Thegate structure 140 includes agate electrode 142 and agate dielectric layer 144. Thegate structure 140 is separated from the source/drain structure 130 by at least one of anouter spacer structure 150 and aninner spacer structure 152. Specifically, for example, theinner spacer structure 152 is formed laterally between the source/drain structure 130 and thegate structure 140 in the x axis direction. - One or more insulation layers 160, 162 are formed adjacent to the source/
drain structure 130 and/or thegate structure 140. The insulation layers 160, 162 include silicon oxide or other suitable dielectric materials. Note that inFIG. 1A , some portions of the insulation layers 160, 162 are omitted to show the source/drain structure 130 and/or thenanowire stack 120, for illustrative purposes only. The insulation layers 160, 162 may be a single layer of a dielectric material, two separately formed layers of a same dielectric material or two layers of different dielectric materials. -
FIG. 1A shows, as an illustrative example, that the source/drain structure 130 is formed such that anupper surface 132 of the source/drain structure 130 is substantially at a same level as that of thegate structure 140. This example is not limiting. Depending on design requirements, in other examples, the source/drain structure 130 is higher or lower than thegate structure 140, which are all included in the disclosure. - In an embodiment, the
nanowire structures 122 that contact the source/drain structure 130 are configured as a channel region(s) of thedevice 100. - The
substrate 110 may include a silicon substrate in crystalline structure and/or other elementary semiconductors like germanium. Alternatively or additionally, thesubstrate 110 may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, and/or indium phosphide. Further, thesubstrate 110 may also include a silicon-on-insulator (SOI) structure.Substrate 110 may include an epitaxial layer and/or may be strained for performance enhancement. Thesubstrate 110 may also include various doping configurations depending on design requirements such as P-type substrate and/or N-type substrate and various doped regions such as P-wells and/or N-wells. - The
gate structure 140 is formed as a replacement gate. The following description lists examples of materials for thegate structure 140 including thegate electrode 142 and thegate dielectric 144, which are non-limiting. Thegate electrode 142 includes a conductive material, e.g., a metal or a metal compound. Suitable metal materials for thegate electrode 142 include ruthenium, palladium, platinum, tungsten, cobalt, nickel, and/or conductive metal oxides and other suitable P-type metal materials and include hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), aluminides and/or conductive metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), and other suitable materials for N-type metal materials. In some examples, thegate electrode 142 includes a work function layer tuned to have a proper work function for enhanced performance of the field effect transistor devices. For example, suitable N-type work function metals include Ta, TiAl, TiAlN, TaCN, other N-type work function metal, or a combination thereof, and suitable P-type work function metal materials include TiN, TaN, other P-type work function metal, or combination thereof. In some examples, a conductive layer, such as an aluminum layer, a copper layer, a cobalt layer or a tungsten layer is formed over the work function layer such that thegate electrode 142 includes a work function layer disposed over thegate dielectric 144 and a conductive layer disposed over the work function layer and below a gate cap (not shown for simplicity). In an example, thegate electrode 142 has a thickness ranging from about 5 nm to about 40 nm depending on design requirements. - In example embodiments, the
gate dielectric layer 144 includes an interfacial silicon oxide layer (not separately shown for simplicity), e.g., thermal or chemical oxide having a thickness ranging from about 5 to about 10 angstrom (A). In example embodiments, thegate dielectric layer 144 further includes a high dielectric constant (high-K) dielectric material selected from one or more of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), combinations thereof, and/or other suitable materials. A high K dielectric material, in some applications, includes a dielectric constant (K) value larger than 6. Depending on design requirements, a dielectric material of a dielectric contact (K) value of 7 or higher is used. The high-K dielectric layer may be formed by atomic layer deposition (ALD) or other suitable technique. In accordance with embodiments described herein, the high-K dielectric layer of thegate dielectric layer 144 includes a thickness ranging from about 10 to about 30 angstrom (A) or other suitable thickness. - The
outer spacer 150 is formed of a low K dielectric material such as silicon oxynitride (SiOxNy), silicon nitride (Si3N4), silicon monoxide (SiO), silicon oxynitrocarbide (SiONC), silicon oxycarbide (SiOC), vacuum and other dielectrics or other suitable materials. Theouter spacer 150 may be formed through chemical vapor deposition (CVD), high density plasma CVD, spin-on, sputtering, or other suitable approaches. - The
inner spacer 152 is formed of a high K dielectric material, e.g., higher dielectric constant than that of theouter spacer 150. The high K material for theinner spacer 152 includes one or more of silicon nitride Si3N4, silicon carbide (SiC), hafnium oxide (HfO2) or other suitable high K dielectric material. In an embodiment, the K value of theinner spacer 152 material is between about three to four times of the K value of theouter spacer 150 material. In an example, theinner spacer 152 also includes one or more air gaps adjacent to one or more of thegate structure 140 or the source/drain structure 130. - The
inner spacer 152 includes afirst segment 152A formed between thegate structure 140 and the source/drain structure 130 and adjacent to a channel region (nanowire strip) 122. In an embodiment, theinner spacer structure 152 also includes asecond segment 152B that extends upward adjacent theouter spacer 150. Thesecond segment 152 B of theinner spacer 152 is further away from thechannel region 122 than thefirst segment 152A. In this embodiment, a portion of the source/drain structure 130 may be separated from thegate structure 140 by both theinner spacer 152, specifically thesecond segment 152B of theinner spacer 152, and theouter spacer 150. In an embodiment, thefirst segment 152A is hat-shaped with a convex top of the hat shape pointing to thegate structure 140. -
FIG. 1B is a cross-sectional view of thedevice 100 from cutting-line B-B. As shown inFIGS. 1A and 1B together, thegate structure 140 is adjacent to thenanowire stack 122 at least three surfaces of thenanowire stack 120, i.e., the upper surface and the side surfaces.FIG. 1B shows that thegate structure 140 wraps around one or more of theindividual nanowire structures 122. As shown inFIG. 1B , both thegate electrode 142 and thegate dielectric 144 wrap around anindividual nanowire structure 122, which is not limiting. It is possible that only thegate dielectric 144 wraps around anindividual nanowire structure 122 and thegate electrode 142 is adjacent to three surfaces of thenanowire stack 120 as a whole. - In an embodiment, as shown in
FIG. 1B , ananowire structure 122 includes an edge segment (first segment) 124 and a ring portion 126 (second segment) adjacent to theedge segment 124. Thering segment 126 has a larger diameter than theedge segment 124. In a further embodiment, thenanowire structure 122 also includes acenter segment 128 that has a diameter smaller than the diameter of thering segment 126. Other shapes or profiles of thenanowire structure 122 are also possible and included in the disclosure. - In an embodiment, the
first segment 152A of theinner spacer structure 152 “inner spacer 152A” includes a substantially dome-shaped profile. As used in this disclosure, a dome-shaped profile includes all profiles that have a larger base and a smaller apex. A cone shape or a pyramid shape or other similar shapes are all included in the “dome-shaped profile” as used in this disclosure. The apex of the dome-shapedinner spacer 152A is oriented toward thegate structure 140. Further, the dome-shaped profile may include more than one apexes and include a concave portion between two apexes. -
FIG. 1D shows an enlarged cross-sectional view of theinner spacer 152A taken fromFIG. 1B . As shown inFIG. 1D , theinner spacer 152A includes a substantially hat-shaped profile, with the convex top of the hat shape pointing to thegate structure 140. The hat-shaped profile includes a convex portion, e.g., a dome-shaped portion, 154 and a brim-shapedportion 156 projecting from dome-shapedportion 154. The dome-shapedportion 154 and the brim-shapedportion 156 meet at aninterface 158. In some scenarios, the dome-shapedportion 154 smoothly transit into the brim-shapedportion 126 and thefirst segment 152A thus overall includes a dome-shaped profile. -
FIG. 1E includes alternative or additional profile embodiments of theinner spacer 152A from a cross-sectional view. Example I shows that theinner spacer 152A may include a cone-shaped head portion proximal to thegate structure 140 and a base portion distal to thegate structure 140. Example II shows that theinner spacer 152A may include a dome-shaped head portion proximal to thegate structure 140 and a distal base portion. Example III shows that theinner spacer 152A may include a multidome-shaped head portion proximal to thegate structure 140 and a distal base portion. Example IV shows that the inner spacer 152 a may include a continuous shape from the proximal end (with respect to the gate structure 140) to the distal end. - Example I-IV show various profiles of the head portion with the base portion extending from the head portion. In examples I-IV, the edge surface of the base portion is substantially plumb or vertical. Examples V-VIII show various examples where the edge surface of the base portion includes an indentation or recess toward the
gate structure 140. Examples V-VIII show that the base portion is minimized to become a recessed base surface, which is not limiting. The recessed base surface may also exists in a scenario that the base portion extends away from the head portion. For example, the brim-shapedportion 156 ofFIG. 1D may also include a recess base surface. - In an embodiment, the source/
drain structure 130 extends continuously downward from ananowire structure 122 that is stacked higher in the nanowire stack 120 (“higher nanowire structure 122”) to ananowire structure 122 that is stacked lower in the nanowire stack 120 (“lower nanowire structure 122”). The source/drain structure 130 contacts thehigher nanowire structure 122 and thelower nanowire structure 122 by theedge surfaces 122E thereof, respectively. - In an embodiment, as shown in
FIG. 1B , all thenanowire structure 122 contacts the source/drain structure 130, which is not limiting. In other scenarios, depending on fabrication process and product design, some of thenanowire structures 122, e.g., those stacked on the top of thenanowire stack 120, do not contact the source/drain structure 130. For example, theinner spacer structure 150 may be formed between atopmost nanowire structure 122 and the source/drain structure 130. -
FIG. 1C is a cross-sectional view of thedevice 100 from cutting-line C-C inFIG. 1A . As shown inFIGS. 1A and 1C together,multiple nanowire structures 122 of thenanowire stack 120 are wrapped around or surround by thegate structure 140. Specifically, as shown inFIG. 1C , thenanowire structures 122 are each surrounded directly by thegate dielectric 144, which is positioned between thegate electrode 142 and thenanowire structure 122. - The
nanowire stack 120 is formed over thelower fin structure 112 of thesubstrate 110 and overlaps thelower fin structure 112.FIG. 1C shows, as an illustrative example, that thelowest nanowire structure 122 of thenanowire stack 120 is separated from thelower fin structure 112 of thesubstrate 110, which is not limiting. In other embodiments, depending on the design requirements, thelowest nanowire structure 122 contacts thelower fin structure 112. That is, the bottom surface (or lower surface) 129 of thelowest nanowire 122 in thenanowire stack 120 may not be adjacent to thegate structure 140. For example, in the scenario that thenanowire structure 122 and thesubstrate 110 are formed of a same semiconductor material, e.g., silicon, it may meet some design requirements to have thelowest nanowire structure 122 contact thelower fin portion 112. -
FIG. 2 is anexample fabrication process 200, which could be used to make theexample device 100 sown inFIGS. 1A-1D , and other devices.FIGS. 3-12 show stages of awafer 300 in a process of making theexample device 100. At each stage, one or more of three views of thewafer 300 are shown, i.e., the perspective view referenced with letter “A”, a sectional view from cutting line B-B, referenced with letter “B” and also referred to as “B” plane (X-Z plane), and a sectional view from cutting line C-C, referenced with letter “C” and also referred to as “C” plane. At some of the stages, only one view of thewafer 300 is shown and the reference letter of the respective view will be omitted for simplicity. - Referring to
FIG. 2 , with reference also toFIGS. 3A-3C , inexample operation 210, awafer 300 is received.FIGS. 3A-3C illustrate thewafer 300. - The
wafer 300 includes a substrate no, e.g., of silicon, silicon germanium, and/or other suitable semiconductor materials. For example, the substrate no may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, and/or indium phosphide. Further, the substrate no may also include a silicon-on-insulator (SOI) structure. - A vertical stack of
epitaxy layers epitaxy layer FIGS. 3A-3C show, as an illustrative example, that totally fourepitaxy layers 312 and fiveepitaxy layers 314 are stacked over thesubstrate 110, which is not limiting. Other numbers of the epitaxy layers 312, 314 are also possible and included in the disclosure. In an embodiment, thewafer 300 includes a same number of the epitaxy layers 312 as the epitaxy layers 314. In another embodiment, thewafer 300 includes a different number of the epitaxy layers 312 from that of the epitaxy layers 314 - The epitaxy layers 312 are formed of a first semiconductor material and the epitaxy layers 314 are formed of a second semiconductor material different from the first semiconductor material. In an embodiment, the first semiconductor material and the second semiconductor material have different etching rates with respect to some etchants, i.e., having etching selectivity, such that a selective etching may be conducted to remove one of the epitaxy layers 312, 314 with the other one remaining. In an embodiment, the
epitaxy layer 312 is silicon germanium of SixGe1-x, with x being greater than 0 and smaller than 1, and in some embodiments between about 0.4 and about 0.9. In an embodiment, theepitaxy layer 314 is silicon. - The epitaxy layers 312, 314 each may be doped in various approaches with various dopants/impurities, like arsenic, phosphorous, boron, gallium, indium, antimony, oxygen, nitrogen, or various combinations thereof.
- In an embodiment, the epitaxy layers 312, 314 each are sheets of nanowire silicon germanium or nanowire silicon, respectively, and are referred to as
nanosheets nanosheets nanosheets - The epitaxy layers 312, 314 may also be other semiconductor materials.
- Epitaxy layers 312, 314 may be formed using the vapor-liquid-solid (VLS) technique or other suitable growth procedures. In the description herein, the
nanosheets - The
nanosheets substrate 110 or may be locally formed over thesubstrate 110. In a local formation procedure, thenanosheets - Referring back to
FIG. 2 , with respect also toFIGS. 4A-4C , inexample operation 220, afin structures 402 are formed by patterning thewafer 300. Any suitable patterning procedures may be used and all are included in the disclosure. Thefin structure 402 includes two portions, anupper portion 410 and alower portion 112. Thelower portion 112 is formed from patterning thesubstrate 110, e.g., of silicon, and is also part of thesubstrate 110 and is referred to as the “substrate” or the “lower fin portion” or the “lower portion” of the fin, as scenarios apply. Theupper portion 410 is formed from patterning the stacked epitaxy layers 312, 314. In the example case that the epitaxy layers 312, 314 are nanosheets, theupper fin portion 410 includes nanowires silicon germanium strips 412, and nanowire silicon strips 414 vertically stacked in an alternating manner. Theupper fin portion 410 including the stack of the nanowire strips 412, 414 are also referred to asnanowire stack 410. Note that thenanowire stack 410 is different from thenanowire stack 120 ofdevice 100 shown inFIGS. 1A-1C because one group of the nanowire strips 412, 414 will be removed as sacrificial strips, as described herein. - In the following fabrication stages, either the nanowire strips 412 or the nanowire strips 414 will be removed from the
nanowire stack 410 and are referred to as the “sacrificial strips”. The nanowire strips 412, 414 that remain on thenanowire stack 410 are referred to as the “semiconductor nanowire strips.” As illustrative examples, the silicon germanium nanowire strips 412 are removed as sacrificial strips and the silicon nanowire strips 414 remain to eventually become thenanowire structures 122 of thenanowire stack 120 ofdevice 100. - An
insulation layer 160 is formed over thesubstrate 110 and adjacent to thefin structures 402, as shown inFIG. 4A (inFIG. 4A , a portion of theinsulation layer 160 is omitted for illustrative purposes) andFIG. 4C . In an embodiment, theinsulation layer 160 is silicon oxide or other suitable dielectric material. In some embodiments, anetch stop layer 420 is formed between theinsulation layer 160 and thesubstrate 110 including thelower portion 112 of thefin structure 402. Theetch stop layer 420 is a different dielectric material from theinsulation layer 160. In an embodiment, theetch stop layer 420 is silicon nitride or other suitable dielectric materials. In an embodiment, theinsulation layer 160 and theetch stop layer 420 are adjacent only to thelower fin portion 112, and theupper fin portion 410 is exposed from theinsulation layer 160 and theetch stop layer 420. - Referring back to
FIG. 2 , with reference also toFIG. 5A-5C , inexample operation 230, a sacrificial ordummy gate structure 510 is formed over thesubstrate 110 and adjacent to or surround three surfaces of theupper fin portion 410, i.e., two side surfaces 420S and anupper surface 410U. In an embodiment, thesacrificial gate structure 510 may include asacrificial polysilicon layer 512, a sacrificial cap layer (not shown for simplicity), and a sacrificial liner layer (not shown for simplicity). The sacrificial cap layer and the sacrificial liner layer may be silicon oxide or other suitable dielectric materials. The total height of thesacrificial gate structure 510 may be higher or substantially equal to, but not lower than, the replacement gate that is to be made in the space occupied by thesacrificial gate structure 510. - An
outer spacer 520 is formed adjacent to thesacrificial gate structure 510. Theouter spacer 520 may be silicon nitride or other suitable dielectric materials. Theouter spacer 150 is formed of a low K dielectric material such as silicon oxynitride, silicon nitride (Si3N4), silicon monoxide (SiO), silicon oxynitrocarbide (SiONC), silicon oxycarbide (SiOC), silicon mononitride (SiN), vacuum and other dielectrics or other suitable materials. Theouter spacer 520 may be formed through chemical vapor deposition (CVD), high density plasma CVD, spin-on, sputtering, or other suitable approaches. - As shown in
FIGS. 5A and 5B , the nanowire strips 412, 414 each laterally extend beyond theouter spacer 520 in the x-axis direction. - Before or after the formation of the
sacrificial gate structure 510 and theouter spacer 520, aninsulation layer 162 is formed adjacent to theouter spacer 520. Theinsulation layer 162 may include a same dielectric material as theinsulation layer 160 or may be a different dielectric material. Theinsulation layer 162 is omitted fromFIG. 5A for illustrative purposes. -
FIGS. 6-12 show B plane view of thewafer 300 in the various fabrication stages. - Referring back to
FIG. 2 , with reference also toFIG. 6 , inexample operation 240, a trench oraperture 620 is formed within theinsulation layer 162 to expose thenanowire stack 410 by each side of theouter spacer 520. In an embodiment, aportion 622 of theouter spacer 520 that overlaps thenanowire stack 410 is also exposed.FIG. 6 shows that theaperture 620 stops substantially at the level of the topmost nanowire strip, here thesacrificial nanowire strip 412 of silicon germanium, which is not limiting. In other embodiments, a portion of one or more of the top nanowire strips 412, 414 may be removed. That is, theaperture 620 may extend downward beyond theupper surface 410U of thenanowire stack 410. - Referring back to
FIG. 2 , with reference also toFIG. 7 , inexample operation 250, a selective etching is conducted through theapertures 620 to selectively remove the sacrificial nanowire strips 412 of silicon germanium exposed from theapertures 620 and to leave thesemiconductor nanowire strip 414 of silicon remain within theaperture 620. In an embodiment, an ammonia solution of ammonium hydroxide “NH4OH” or other suitable etchants are used to selectively etch out the sacrificial nanowire strips 412. In the case that the nanowire strips 414 of silicon are used as the sacrificial nanowire strips, a hydrochloric acid solution “HCL” or other etchants is used to selectively etch out the nanowire strips 414 and while leaving the nanowire strips 412 of silicon germanium in place. - In an embodiment, a selective wet etching is performed to remove the sacrificial nanowire strips 412 (or 414) such that a
recess 710 is formed on theedge portions 712 of the sacrificial nanowire strips 412 that remain below thesacrificial gate structure 510 and theouter spacer 150, which is referred to herein as “recededsacrificial strip 412R” for descriptive purposes. - In an embodiment, the etching conditions are controlled such that the
edge portions 712 of the remainingsacrificial strips 412R recede inward beyond theouter surface 720 of theouter spacer 150. In an embodiment, theoutermost points 714 of theedge portions 712 are positioned between theouter surface 720 and theinner surface 722 of theouter spacer 150. - The receding of the
sacrificial strips 412 unavoidably also removes asmall portion 414S (shown in dotted line) of the semiconductor nanowire strips 414. As a result, a first segment 414(1) of thenanowire strip 414 that is exposed within theaperture 620 includes a smaller diameter than a second segment 414(2) that is below thesacrificial gate structure 510 and is not exposed within theaperture 620. This structural characteristic of this stage of the wafer is enabled by the sequence of the fabrication process that thesacrificial strips 412 are selectively removed while the semiconductor nanowire strips 414 remain. This structural characteristic that the segment 414(1) includes a smaller diameter than the second segment 414(2) also affects the shapes of the other structural features, like theinner spacer 152A ofFIG. 1D , as described herein. - Referring back to
FIG. 2 , with reference also toFIG. 8 , inexample operation 260, adielectric layer 810 is formed adjacent to theedge portions 712 of the recededsacrificial strips 412R that remains below thesacrificial gate structure 510. Thedielectric layer 810 at least partially fills in therecesses 710 adjacent to theedge portions 712. In an example, thedielectric layer 810 does not fully fill therecesses 710 and a gap, either air gap or vacuum gap, is formed between thedielectric layer 810 and theedge portion 712 of the recededsacrificial strip 412R.FIG. 8 ′ shows thegap 812 in an enlarged view. - In an embodiment, the
dielectric layer 810 is formed of a dielectric material that has a higher dielectric constant than theouter spacer 520. The dielectric material for theinner spacer 152 includes one or more of silicon nitride Si3N4, silicon carbide (SiC), hafnium oxide (HfO2) or other suitable dielectric material. In an embodiment, the K value of thedielectric layer 810 material is between about three to four times of the K value of theouter spacer 520 material. - In an embodiment, the
dielectric layer 810 is also formed over the first segment 414(1) of thesemiconductor nanowire strip 414. - Referring back to
FIG. 2 , with reference also toFIG. 9 , inexample operation 270,inner spacers 152A are formed by removing extra portions of thedielectric layer 810 through an anisotropic etching. In an embodiment, a resultant surface 1525 of theinner spacer 152A, which is opposite to the recededsacrificial strip 412R, is substantially plumb with theouter surface 720 of theouter spacer 520. In another embodiment, thesurface 152S is formed outwardly beyond theouter surface 720 of theouter spacer 520. Further, in an embodiment, athin layer 152B of thedielectric layer 810 remains adjacent to theouter spacer 520 and may become asecond segment 152B of the inner spacer structure 152 (152A+152B). Note that thesecond segment 152B is technically not an “inner spacer” and is referred to as a second segment of theinner spacer structure 152 only for descriptive purposes. - In an embodiment, the
first segment 152A of theinner spacer 152, “inner spacer 152A” includes a substantially dome-shaped profile due to filling therecesses 710. As used in this disclosure, a dome-shaped profile includes all profiles that have a larger base and a smaller apex. A cone shape or a pyramid shape or other similar shapes are all included in the “dome-shaped profile” as used in this disclosure. Other alternative or additional shapes/profiles of theinner spacer 152 or thefirst segment 152A are also possible. The apex of the dome-shapedinner spacer 152A is directed toward the recededsacrificial strips 412R. - In an embodiment, as the first segment 414(1) of the
semiconductor nanowire strip 414 has a smaller diameter than the second segment 414(2) of thesemiconductor nanowire strip 414, theinner spacer 152A includes a substantially hat-shaped profile. The hat-shaped profile includes a dome-shapedportion 154 and a brim-shapedportion 156 projecting from dome-shapedportion 154. The dome-shapedportion 154 and the brim-shapedportion 156 meet at aninterface 158. In some scenarios, theinterface 158 overlaps with theoutermost point 714 of the recededsacrificial strip 412R (also seeFIG. 7 ). In some scenarios, the dome-shapedportion 154 smoothly transit into the brim-shapedportion 156 and theinner spacer 152A thus overall includes a dome-shaped profile. - The semiconductor nanowire strips 414 are receded, through which portions of the first segment 414(1) are removed simultaneously with or after the extra portion of the
dielectric layer 810 is removed. That is, the edge surfaces 122E of the plurality of the semiconductor strips are formed one of simultaneously with or after theinner spacer 152, or specifically thefirst segment 152A, is formed. As a result, the edge surfaces 122E of the receded semiconductor nanowire strips 414 are exposed from theinner spacers 152A. In an embodiment, theedge surfaces 122E are substantially plumb with thesurfaces 154 of theinner spacers 152A. In another embodiment, theedge surfaces 122E extend out from theinner spacers 152A. - Referring back to
FIG. 2 , with reference also toFIG. 10 , inexample operation 280,semiconductor regions 130 are formed within theapertures 620 using epitaxy processes. Specifically, thesemiconductor regions 130 are formed adjacent to theinner spacer 152A (and optionally also 152B) and contacting the edge surfaces 122E of the receded semiconductor nanowire strips 414, which are exposed from theinner spacers 152A. - In the scenario that the semiconductor nanowire strips 414 are silicon, the device is configured as an nMOS and the
semiconductor regions 130 are silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon phosphide (SiP) or other suitable semiconductor materials. In the scenario that the nanowire strips 412 of silicon germanium remain as the semiconductor nanowire strips, the device is configured as a pMOS, and thesemiconductor regions 130 are silicon germanium (SiGe) or silicon-germanium-boron (SiGeB) or other suitable semiconductor materials. Thesemiconductor regions 130 may be doped in various approaches with various dopants/impurities, like arsenic, phosphorous, boron, gallium, indium, antimony, oxygen, nitrogen, or various combinations thereof. - In an embodiment, the
semiconductor regions 130 are formed to contact each exposed edge surfaces 122E of the semiconductor nanowire strips 414. - Referring back to
FIG. 2 , with reference also toFIG. 11 , inexample operation 290, the receded sacrificial nanowire strips 412R and thesacrificial gate structure 510 are removed, leaving avoid 1110. A selective etching procedure is done to remove the recededsacrificial strips 412R with the receded semiconductor nanowire strips 414 remaining. The selective etching unavoidably removes also a portion 414SS (shown in dotted line) from the second segment 414(2) (FIG. 8 ) of the semiconductor nanowire strips 414. Due to the dome-shapedportions 154 of theinner spacers 152A, the removal of the portions 414SS forms a ring segment 414(3) and a center segment 414(4) of the recededsemiconductor nanowire strip 414. The center segment 414(4) includes a smaller diameter than the ring segment 414(3). As a result, the receded semiconductor nanowire strips 414 become thenanowire structures 122 ofFIG. 1B , which each includes anedge segment 124, aring segment 126, and a center segment 128 (FIG. 1B ). - Referring back to
FIG. 2 , with reference also toFIG. 12 , inexample operation 295, areplacement gate structure 140 including agate electrode 142 and agate dielectric 144 is formed within thevoid 1110. Thereplacement gate structure 140 wraps around the semiconductor nanowire strips 122 of thenanowire stack 120. - As the edge surfaces 122E of the
semiconductor nanowire structures 122 are exposed simultaneously with or after the formation of theinner spacer 152A, the edge surfaces 122 are not covered by the dielectric layer of theinner spacer 152A. As such, the junction between thesemiconductor nanowire structure 122, configured as the channel region, and the source/drain region 130 is Ohmic and the contact resistance is low. -
FIG. 12 shows one example embodiment of thestructure 110, which does not limit the scope of the disclosure. Other embodiments may include some variant structure features without changing the principles of the disclosure. For example,FIG. 13 shows an alternative and/oradditional structure 100′. In thestructure 100′, some of the semiconductor strips 122 are not exposed from theinner spacer 152, or specifically thefirst segment 152A. For example, in thestructure 100′, an upperlevel semiconductor strip 122U is receded before theinner spacer 152 is formed and is covered by theinner spacer 152. The upperlevel semiconductor strip 122U may be receded together with some of thesacrificial strips 412 or may be receded separately from the sacrificial strips 412. The receding of the upperlevel semiconductor strip 122U may be implemented based on fabrication process design and/or product/device design. -
FIG. 14 shows another alternative and/oradditional structure 100″. In thestructure 100″, the semiconductor strips 122 are not receded to be substantially plumb with theinner spacer 152 and remain extending outward beyond theouter spacer 150 and/or theinner spacer 152. The source/drain regions 130 are formed surrounding, or wrapping around, the semiconductor strips 122. - Other variants are also possible and included in the disclosure. Further, the embodiments and the components thereof may be combined in various ways, which are also included in the disclosure.
- The present disclosure may be further appreciated with the description of the following embodiments:
- In a device embodiment, a device includes a substrate, a channel region over the substrate, a source/drain structure adjacent to and contacting the channel region and a gate structure surrounds the channel region. The channel region includes a stack of nanowire structures over the substrate. The stack of nanowire structures includes a first nanowire structure that includes a first segment at an edge of the first nanowire structure and a second segment adjacent to the first segment with the second portion having a larger diameter than the first segment. The source/drain structure is adjacent to and contacts the first segment of the first nanowire structure. The gate structure wraps around the first nanowire structure. An inner spacer structure is positioned laterally between the source/drain structure and the gate structure.
- In another embodiment, a semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, a first dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
- In further embodiments, a method includes receiving a wafer, the wafer including a stack of epitaxy layers over a substrate, the stack of epitaxy layers including a plurality of semiconductor epitaxy layers and a plurality of sacrificial epitaxy layers stacked in an alternating sequence; forming a fin structure by patterning the wafer, the fin structure including a stack of a plurality of semiconductor strips and a plurality of sacrificial strips; forming a sacrificial gate structure and an outer spacer over the fin structure, the sacrificial gate structure contacting at least three surfaces of the fin structure; forming receded sacrificial strips by selectively removing portions of the plurality of the sacrificial strips that extends laterally beyond the outer spacer and leaving the plurality of the semiconductor strips remain extending laterally beyond the outer spacer; forming an inner spacer laterally adjacent to the receded sacrificial strips; forming exposed edge surfaces of the plurality of the semiconductor strips by receding the plurality of the semiconductor strips; forming a semiconductor layer adjacent to the inner spacer and contacting the exposed edge surfaces of the plurality of the semiconductor strips; forming an open space by removing the sacrificial gate and the receded sacrificial strips; and forming a replacement gate within the open space.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
1. A semiconductor structure, comprising:
a substrate;
a plurality of nano structures vertically stacked over the substrate, the plurality of nano structures comprises an upper nano structure and one or more lower nano structures between the upper nano structure and the substrate;
a semiconductor region adjacent to and laterally contacting each of the one or more lower nano structures;
a gate structure over the plurality of nano structures; and
a first dielectric structure laterally between the semiconductor region and the gate structure, the first dielectric structure being between the upper nano structure and the semiconductor region, the first dielectric structure having a hat-shaped profile between the semiconductor region and the gate structure.
2. The semiconductor structure of claim 1 , wherein the hat-shaped profile includes a dome-shaped portion and a brim-shaped portion.
3. The semiconductor structure of claim 1 , wherein the first dielectric structure extends between the upper nano structure and the semiconductor region.
4. The semiconductor structure of claim 1 , wherein the hat-shaped profile has an apex pointing to the gate structure.
5. The semiconductor structure of claim 1 , wherein each of the lower nano structures has a first segment and a second segment, the first segment having a diameter smaller than a diameter of the second segment.
6. The semiconductor structure of claim 5 , wherein the first segment is between the second segment and the semiconductor region.
7. The semiconductor structure of claim 1 , further comprising a gate spacer over and contacting the first dielectric structure and adjacent to the gate structure, the gate spacer including a dielectric material different than that of the first dielectric structure.
8. The semiconductor structure of claim 7 , wherein the dielectric material of the first dielectric structure has a dielectric constant higher than the dielectric material of the gate spacer.
9. The semiconductor structure of claim 7 , wherein the first dielectric structure extends along sidewalls of the gate spacer.
10. A semiconductor device comprising:
a substrate;
a plurality of nano structures over the substrate, the plurality of nano structures comprising an upper nano structure and lower nano structures between the upper nano structure and the substrate;
a gate structure over the plurality of nano structures, the gate structure comprising a gate dielectric and a gate electrode, the gate structure being between adjacent ones of the lower nano structures and between the upper nano structure and an upper one of the lower nano structures;
an outer spacer laterally adjacent the gate structure;
an inner spacer structure adjacent the gate structure, the inner spacer structure having portions being between adjacent ones of the lower nano structures, the inner spacer structure extending below the outer spacers; and
a first source/drain region contacting an end of the lower nano structures, wherein the inner spacer structure extends between the upper nano structure and the first source/drain region.
11. The semiconductor device of claim 10 , wherein the inner spacer structure extends along a vertical sidewall of the outer spacer.
12. The semiconductor device of claim 10 , wherein the inner spacer structure has a hat-shaped profile between the gate structure and the first source/drain region.
13. The semiconductor device of claim 12 , wherein a crown of the hat-shaped profile faces toward the gate structure.
14. The semiconductor device of claim 10 , wherein the gate electrode has a concave surface facing the first source/drain region.
15. The semiconductor device of claim 10 , wherein each of lower nano structures comprises a first segment and a second segment with the second segment having a larger diameter than the first segment, and the first source/drain region laterally contacts an edge portion of first segment, wherein the first segment is between the first source/drain region and the second segment.
16. A semiconductor device comprising:
a substrate;
a channel region including a plurality of nano structures over the substrate, the plurality of nano structures comprising one or more lower nano structures and an upper nano structure over the one or more lower nano structures;
a gate structure over the channel region, the gate structure comprising a gate dielectric and a gate electrode, the gate structure being interposed between adjacent ones of the plurality of nano structures;
an outer spacer laterally adjacent the gate structure;
an inner spacer structure adjacent the gate structure, the inner spacer structure comprising a plurality of inner spacers, each of the inner spacers being interposed between adjacent ones of the one or more lower nano structures, the inner spacer structure extending below the channel region; and
a first source/drain region adjacent the channel region, the inner spacer structure extending between the upper nano structure and the first source/drain region.
17. The semiconductor device of claim 16 , wherein the one or more lower nano structures extend past a lateral boundary of the outer spacer toward the first source/drain region.
18. The semiconductor device of claim 16 , further comprising a second source/drain region adjacent the channel region, wherein the channel region is between the first source/drain region and the second source/drain region, wherein each of the one or more lower nano structures comprises:
a first segment at an edge closest to the first source/drain region, the first segment having a first thickness;
a second segment adjacent to the first segment, the second segment having a second thickness greater than the first thickness; and
a third segment at an edge closest to the second source/drain region, the second segment being between the first segment and the third segment, the third segment having a third thickness less than the second thickness.
19. The semiconductor device of claim 16 , wherein each inner spacer of the plurality of inner spacers have a hat-shaped profile.
20. The semiconductor device of claim 16 , wherein the inner spacer structure extends along a sidewall of the outer spacer.
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US18/366,297 US20230387265A1 (en) | 2018-08-30 | 2023-08-07 | Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same |
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