CN110858591A - 互补金属氧化物半导体器件 - Google Patents

互补金属氧化物半导体器件 Download PDF

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CN110858591A
CN110858591A CN201910547268.XA CN201910547268A CN110858591A CN 110858591 A CN110858591 A CN 110858591A CN 201910547268 A CN201910547268 A CN 201910547268A CN 110858591 A CN110858591 A CN 110858591A
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金钟明
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Samsung Electro Mechanics Co Ltd
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Abstract

本发明提供一种互补金属氧化物半导体器件，所述互补金属氧化物半导体(CMOS)器件包括：高电阻率基板；第一CMOS结构，设置在所述高电阻率基板的第一区域中；以及第二CMOS结构，与所述第一CMOS结构的半导体类型相同，并且设置在所述高电阻率基板的与所述第一区域分开的第二区域中。所述高电阻率基板设置在所述第一CMOS结构和所述第二CMOS结构之间，以将所述第一CMOS结构与所述第二CMOS结构分开。

Description

互补金属氧化物半导体器件
本申请要求于2018年8月24日在韩国知识产权局提交的第10-2018-0098965号韩国专利申请的优先权的权益，所述韩国专利申请的全部公开内容出于所有目的通过引用被包含于此。
技术领域
以下描述涉及一种具有改善的插入损耗的互补金属氧化物半导体(CMOS)晶体管的布局结构。
背景技术
最近开发的移动Wi-Fi模块被配置为执行2.4GHz/5GHz双频段多输入多输出(MIMO)通信，并且需要Wi-Fi模块的小型化和集成设计以适配移动装置。
此外，需要在一个芯片中包括功率放大器(PA)、内部耦合器、射频(RF)开关和低噪声放大器(LNA)的前端集成电路(FEIC)。为此，最近已经使用单片工艺将通过分离传统发送和接收而被配置为两个芯片的前端电路配置为单个芯片。
在如上所述的前端集成电路(FEIC)形成为单个芯片的情况下，尽管可使用绝缘体上硅(SOI：Silicon-on-Insulator)工艺以最大化嵌入其中的射频开关的特性，但当使用SOI工艺时，设计功率放大器非常困难。因此，可使用BiCMOS工艺来将发送器和接收器配置为单个芯片。
然而，BiCMOS工艺的开关损耗大于SOI工艺的开关损耗，这会直接影响接收器的接收性能和发送器的输出功率。因此，为了解决这样的问题，需要能够降低开关损耗的结构。
发明内容
提供本发明内容以按照简化的形式介绍下面在具体实施方式中进一步描述的选择的构思。本发明内容不意在确定所要求保护的主题的关键特征或必要特征，也不意在用于帮助确定所要求保护的主题的范围。
在一个总体方面，一种CMOS器件包括：高电阻率基板；第一CMOS结构，设置在所述高电阻率基板的第一区域中；以及第二CMOS结构，与所述第一CMOS结构的半导体类型相同，并且设置在所述高电阻率基板的与所述第一区域分开的第二区域中。所述高电阻率基板设置在所述第一CMOS结构和所述第二CMOS结构之间，以将所述第一CMOS结构与所述第二CMOS结构分开。
所述第一CMOS结构和所述第二CMOS结构中的每个可以是三阱结构。
所述第一CMOS结构可包括堆叠为第一三阱结构的第一低电阻率层、第一深N阱层和第一P阱层。
所述第二CMOS结构可包括堆叠为第二三阱结构的第二低电阻率层、第二深N阱层和第二P阱层。
所述第一CMOS结构可包括：第一低电阻率层，堆叠在所述高电阻率基板的所述第一区域中；第一深N阱层，设置在所述第一低电阻率层上并且被所述第一低电阻率层围绕；第一P阱层，设置在所述第一深N阱层上并且被所述第一深N阱层围绕；以及第一源极区域、第一漏极区域和第一栅极区域，设置在所述第一P阱层中以分别形成所述第一CMOS结构的源极、漏极和栅极。
所述第二CMOS结构可包括：第二低电阻率层，堆叠在所述高电阻率基板的所述第二区域中；第二深N阱层，设置在所述第二低电阻率层上并且被所述第二低电阻率层围绕；第二P阱层，设置在所述第二深N阱层上并且被所述第二深N阱层围绕；以及第二源极区域、第二漏极区域和第二栅极区域，设置在所述第二P阱层中以分别形成所述第二CMOS结构的源极、漏极和栅极。
所述高电阻率基板的电阻率值可大于所述第一低电阻率层的电阻率值和所述第二低电阻率层的电阻率值二者。
所述高电阻率基板的在所述第一CMOS结构和所述第二CMOS结构之间的区域的厚度可比所述第一低电阻率层的厚度和所述第二低电阻率层的厚度二者厚，并且可比所述第一低电阻率层和所述第一深N阱层的总厚度以及所述第二低电阻率层和所述第二深N阱层的总厚度二者薄。
在另一总体方面，一种CMOS器件包括：高电阻率基板；第一三阱结构的第一CMOS结构，设置在所述高电阻率基板的第一区域中；以及第二三阱结构的第二CMOS结构，设置在所述高电阻率基板的与所述第一区域分开的第二区域中。所述高电阻率基板设置在所述第一三阱结构和所述第二三阱结构之间，以将所述第一三阱结构与所述第二三阱结构分开。
所述第一CMOS结构可与所述第二CMOS结构的半导体类型相同。
所述第一CMOS结构的所述第一三阱结构可包括堆叠的第一低电阻率层、第一深N阱层和第一P阱层。
所述第二CMOS结构的所述第二三阱结构可包括堆叠的第二低电阻率层、第二深N阱层和第二P阱层。
所述第一CMOS结构可包括：第一低电阻率层，堆叠在所述高电阻率基板的所述第一区域中；第一深N阱层，设置在所述第一低电阻率层上并且被所述第一低电阻率层围绕；第一P阱层，设置在所述第一深N阱层上并且被所述第一深N阱层围绕；以及第一源极区域、第一漏极区域和第一栅极区域，设置在所述第一P阱层中以分别形成所述第一CMOS结构的源极、漏极和栅极。
所述第二CMOS结构可包括：第二低电阻率层，堆叠在所述高电阻率基板的所述第二区域中；第二深N阱层，设置在所述第二低电阻率层上并且被所述第二低电阻率层围绕；第二P阱层，设置在所述第二深N阱层上并且被所述第二深N阱层围绕；以及第二源极区域、第二漏极区域和第二栅极区域，设置在所述第二P阱层中以分别形成所述第二CMOS结构的源极、漏极和栅极。
所述高电阻率基板的电阻率值可大于所述第一低电阻率层的电阻率值和所述第二低电阻率层的电阻率值二者。
所述高电阻率基板的在所述第一CMOS结构和所述第二CMOS结构之间的区域的厚度可比所述第一低电阻率层的厚度和所述第二低电阻率层的厚度二者厚，并且可比所述第一低电阻率层和所述第一深N阱层的总厚度以及所述第二低电阻率层和所述第二深N阱层的总厚度二者薄。
一种互补金属氧化物半导体(CMOS)器件包括：基板；第一CMOS结构，设置在所述基板中并包括第一层；以及第二CMOS结构，设置在所述基板中并且包括第二层，所述第二层通过所述基板的设置在所述第一层和所述第二层之间的部分与所述第一层分开，所述基板的所述部分的电阻率高于所述第一层的电阻率和所述第二层的电阻率二者。
所述基板的设置在所述第一层和所述第二层之间的所述部分的厚度可大于所述基板的除了所述基板的设置在所述第一层和所述第二层之间的所述部分之外的部分的厚度。
根据以下具体实施方式和附图，其他特征和方面将是显而易见的。
附图说明
图1是示出根据示例的互补金属氧化物半导体(CMOS)晶体管的布局结构的截面图。
图2是示出根据示例的CMOS晶体管的布局结构的截面图。
图3是根据示例的CMOS晶体管的电路图。
图4是示出根据示例的高电阻率基板的厚度的示图。
图5是示出根据示例的应用CMOS晶体管的开关电路的插入损耗特性的曲线图。
图6是示出根据示例的CMOS晶体管的应用的示图。
在整个附图和具体实施方式中，相同的附图标记指示相同的元件。附图可不按照比例绘制，并且为了清楚、说明和方便起见，可夸大附图中的元件的相对尺寸、比例和描绘。
具体实施方式
提供以下具体实施方式来帮助读者获得对这里描述的方法、设备和/或系统的全面理解。然而，在理解本申请的公开内容之后，这里描述的方法、设备和/或系统的各种改变、变型和等同物将是显而易见的。例如，这里描述的操作顺序仅仅是示例，并且不限于这里阐述的那些操作顺序，而是除了必须以特定顺序发生的操作之外，可做出在理解本申请的公开内容之后将是显而易见的改变。另外，为了提高清楚性和简洁性，可省略本领域中已知的特征的描述。
在此描述的特征可以以不同的形式实施，并且不应被解释为局限于在此描述的示例。更确切地，提供了在此描述的示例仅仅是为了说明在理解本申请的公开内容之后将是显而易见的实现这里描述的方法、设备和/或系统的许多可行方式中的一些可行方式。
在此，要注意的是，关于示例或实施例的术语“可”的使用(例如，关于示例或实施例可包括什么或实现什么)意味着存在包括或实现这样的特征的至少一个示例或实施例，而全部示例和实施例不限于此。
在整个说明书中，当诸如层、区域或基板的元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时，该元件可直接“在”所述另一元件“上”、直接“连接到”所述另一元件或直接“结合到”所述另一元件，或者可存在介于它们之间的一个或更多个其他元件。相比之下，当元件被描述为“直接在”另一元件“上”、“直接连接到”另一元件或“直接结合到”另一元件时，可不存在介于它们之间的其他元件。
如在此所使用的，术语“和/或”包括相关所列项中的任意一个以及任意两个或更多个的任意组合。
尽管在此可使用诸如“第一”、“第二”和“第三”的术语来描述各种构件、组件、区域、层或部分，但是这些构件、组件、区域、层或部分不应被这些术语限制。更确切地，这些术语仅用于将一个构件、组件、区域、层或部分与另一构件、组件、区域、层或部分区分开。因此，在不脱离示例的教导的情况下，这里描述的示例中所称的第一构件、第一组件、第一区域、第一层或第一部分可被称为第二构件、第二组件、第二区域、第二层或第二部分。
为了易于描述，在此可使用空间相对术语(诸如“在……之上”、“上方”、“在……之下”和“下方”)来描述附图中所示的一个元件与另一元件的关系。这样的空间相对术语意图除了包含附图中所描绘的方位之外，还包含装置在使用或操作中的不同方位。例如，如果附图中的装置被翻转，则被描述为相对于另一元件位于“之上”或“上方”的元件随后将相对于所述另一元件位于“之下”或“下方”。因此，术语“在……之上”根据装置的空间方位而包括“在……之上”和“在……之下”两种方位。装置还可以以其他方式定位(例如，旋转90度或处于其他方位)，并且对在此使用的空间相对术语进行相应地解释。
在此使用的术语仅是为了描述各种示例，而不用于限制本公开。除非上下文另外清楚地指出，否则单数形式也意图包括复数形式。术语“包含”、“包括”和“具有”列举存在所陈述的特征、数量、操作、构件、元件和/或它们的组合，但是不排除存在或添加一个或更多个其他特征、数量、操作、构件、元件和/或它们的组合。
由于制造技术和/或公差，可能发生附图中示出的形状的变化。因此，在此描述的示例不限于附图中示出的特定形状，而是包括在制造期间发生的形状变化。
在此描述的示例的特征可以以在理解本申请的公开内容之后将是显而易见的各种方式进行组合。此外，尽管在此描述的示例具有各种构造，但是在理解本申请的公开内容之后将是显而易见的其他构造也是可行的。
在下文中，将参照附图详细描述示例。
图1是示出根据示例的互补金属氧化物半导体(CMOS)晶体管的布局结构的截面图。
参照图1，CMOS晶体管的布局结构包括在包括多个CMOS结构的CMOS晶体管的布局结构中的至少两个CMOS结构，例如，第一CMOS结构120和第二CMOS结构130。
CMOS晶体管的布局结构可包括高电阻率基板110、第一CMOS结构120和第二CMOS结构130。
高电阻率基板110包括高电阻率区域。
第一CMOS结构120可形成在多个CMOS结构中的高电阻率基板110的上部的第一区域A1中，并且形成为具有三个阱层的第一三阱结构120-TW。
第二CMOS结构130可形成在多个CMOS结构中的高电阻率基板110的上部的第二区域A2中。第二区域A2与第一区域A1分开。第二CMOS结构130可形成为具有三个阱层的第二三阱结构130-TW。
高电阻率基板110可形成在第一CMOS结构120和第二CMOS结构130之间，以将第一CMOS结构120和第二CMOS结构130彼此分开。高电阻率基板110可形成在第一三阱结构120-TW和第二三阱结构130-TW之间，以将第一三阱结构120-TW和第二三阱结构130-TW分开。
在图1中，S1、G1和D1分别是与第一晶体管对应的第一CMOS结构120的第一源极区域、第一栅极区域和第一漏极区域，并且S2、G2和D2分别是与第二晶体管对应的第二CMOS结构130的第二源极区域、第二栅极区域和第二漏极区域。
对于每个附图，对于具有相同附图标记和相同功能的组件可省略不必要的冗余说明，并且可解释针对每个附图的不同之处。
图2是示出根据示例的CMOS晶体管的布局结构的截面图。
参照图2，第一CMOS结构120的第一三阱结构120-TW可包括堆叠的第一低电阻率层121、第一深N阱层122、第一P阱层123。
第一低电阻率层121可具有堆叠在多个CMOS结构中的高电阻率基板110的上部的第一区域A1中的阱结构。第一低电阻率层121的电阻率值可相对地小于高电阻率基板110的电阻率值。例如，第一低电阻率层121的电阻率值可以是50欧姆·米(Ω·m)。
第一深N阱层122可形成在第一低电阻率层121的上部上，并且可具有被第一低电阻率层121围绕的阱结构。例如，第一深N阱层122是N型掺杂区域。通过在水平地进行N型掺杂之后在两侧垂直地形成N型掺杂柱(N-typedopedcolumn)，第一深N阱层122的阱结构整体上具有阱形状。这是形成阱结构的一个示例，并且第一深N阱层122的形成不限于这种方法。
第一P阱层123可形成在第一深N阱层122的上部上，并且可具有被第一深N阱层122围绕的阱结构。例如，第一P阱层123是作为CMOS结构的主体区域的P型掺杂区域。
第一低电阻率层121、第一深N阱层122和第一P阱层123中的每个形成为阱结构并且依次堆叠以最终形成三阱结构。
分别形成第一CMOS结构120的源极、漏极和栅极的第一源极区域SA1、第一漏极区域DA1和第一栅极区域GA1可形成在第一P阱层123的上部上。
例如，高电阻率基板110的电阻率值大于第一低电阻率层121的电阻率值。例如，高电阻率基板110可以是1千欧姆·米(KΩ·m)。
第二CMOS结构130的第二三阱结构130-TW可包括堆叠的第二低电阻率层131、第二深N阱层132和第二P阱层133。
第二低电阻率层131可具有堆叠在多个CMOS结构中的高电阻率基板110的上部的第二区域A2中的阱结构。第二低电阻率层131的电阻率值可相对地小于高电阻率基板110的电阻率值。例如，第二低电阻率层131的电阻率值可以是50欧姆·米(Ω·m)。
第二深N阱层132可形成在第二低电阻率层131的上部上，并且可具有被第二低电阻率层131围绕的阱结构。例如，第二深N阱层132是N型掺杂区域。通过在水平地进行N型掺杂之后，在两侧垂直地形成N型掺杂柱，第二深N阱层132的阱结构整体上具有阱形状。这是形成阱结构的一个示例，并且第二深N阱层132的形成不限于这种方法。
第二P阱层133可形成在第二深N阱层132的上部上，并且可具有被第二深N阱层132围绕的阱结构。例如，第二P阱层133是作为CMOS结构的主体区域的P型掺杂区域。
第二低电阻率层131、第二深N阱层132和第二P阱层133中的每个形成为阱结构并且依次堆叠以最终形成三阱结构。
分别形成第二CMOS结构130的源极、漏极和栅极的第二源极区域SA2、第二漏极区域DA2和第二栅极区域GA2可形成在第二P阱层133的上部上。
例如，高电阻率基板110的电阻率值大于第二低电阻率层131的电阻率值。
参照图1和图2，使用包括高电阻率基板110和第一低电阻率层121以及高电阻率基板110和第二低电阻率层131的BiCMOS工艺的CMOS晶体管可主要形成为N型MOS。
在BiCMOS工艺中，存在使用高电阻率基板110来改善性能的工艺。当使用这种工艺时，高电阻率基板110的大部分区域为高电阻率区域，并且可用作开关的第一CMOS结构120和第二CMOS结构130分别包括具有形成在高电阻率基板110上的低电阻率区域的第一低电阻率层121和第二低电阻率层131，并且第一CMOS结构120和第二CMOS结构130的晶体管端子分别形成在第一低电阻率层121和第二低电阻率层131上。
此外，参照图1和图2，因为当其中形成端子区域的P阱层被共用时信号通过P阱层泄漏，并且噪声也可通过P阱层进出，所以CMOS结构的相邻的第一CMOS结构120和第二CMOS结构130通常不共用P阱层，使得用于RF信号的晶体管可形成为包括双层围绕P阱层的深N阱层和低电阻率层的三阱结构。
在具有三阱结构的CMOS晶体管中，三阱结构的深N阱层还可减少信号泄漏和噪声进出，但是减少能力仍然会存在限制。也就是说，三阱结构的CMOS结构的晶体管电路仍然导致信号泄漏。
为了进一步防止这种信号泄漏并改善插入损耗，第一CMOS结构120和第二CMOS结构130分别独立地包括第一低电阻率层121和第二低电阻率层131，并且高电阻率基板110放置在第一低电阻率层121和第二低电阻率层131之间，并且因此成组布置的晶体管的低电阻率层可彼此分开，并且相应地，可减少成组或堆叠的晶体管之间的干扰，并且插入损耗可降低。
为了防止第一深N阱层122与第一P阱层123之间的PN结导通，可将操作电压VDD连接到第一深N阱层122并且可将地电位连接到第一P阱层123。
为了防止第二深N阱层132和第二P阱层133之间的PN结导通，可将操作电压VDD连接到第二深N阱层132并且可将地电位连接到第二P阱层133。
图3是根据示例的CMOS晶体管的电路图。
参照图3，第一CMOS结构120的晶体管和第二CMOS结构130的晶体管通过高电阻率基板110彼此物理分开，并且因此可通过高电阻率基板110减少它们之间的干扰，从而改善插入损耗。
图4是示出根据示例的高电阻率基板的厚度的示图。
参照图4，高电阻率基板110在第一低电阻率层121和第二低电阻率层131之间的区域中的厚度DT1可比第一低电阻率层121的厚度DT2薄、与第一低电阻率层121的厚度DT2相同或比第一低电阻率层121的厚度DT2厚。例如，当高电阻率基板110的厚度DT1比第一低电阻率层121的厚度DT2厚时，第一CMOS结构120和第二CMOS结构130之间的干扰消除性能可通过高电阻率基板110进一步改善。
例如，高电阻率基板110的厚度DT1可比第一低电阻率层121和第一深N阱层122的总厚度DT3薄。
例如，高电阻率基板110的厚度DT1可比第二低电阻率层131的厚度(例如，也可以为DT2)厚。
例如，高电阻率基板110的厚度DT1可比第二低电阻率层131和第二深N阱层132的总厚度薄。
尽管未在图中示出，但高电阻率基板110的设置在第一低电阻率层121和第二低电阻率层131之间的高电阻率区域的厚度DT1可比高电阻率基板110的除了在第一低电阻率层121和第二低电阻率层131之间以外的区域中的厚度薄、与其相同或比其厚。然而，例如，当厚度DT1比除了在第一低电阻率层121和第二低电阻率层131之间以外的区域中的厚度厚时，第一CMOS结构120和第二CMOS结构130之间的干扰消除性能可通过高电阻率基板110进一步改善。
图5是示出根据示例的应用CMOS晶体管的开关电路的插入损耗特性的曲线图。
在图5中，G10是示出应用传统CMOS晶体管的开关电路的插入损耗特性的曲线图，G20是示出应用根据在此描述的示例的CMOS晶体管的开关电路的插入损耗特性的曲线图。
参照G10和G20，可以看出，与应用传统CMOS晶体管的开关电路的插入损耗特性相比，应用根据示例的CMOS晶体管的开关电路的插入损耗特性得到改善。
图6是示出根据示例的CMOS晶体管的应用的示图。
参照图6，CMOS晶体管被应用于包括在前端电路(或模块)中的射频开关。
图6中示出的射频开关可包括：例如，连接在天线ANT和第一端口P1之间的第一串联开关SE1、连接在天线ANT和第二端口P2之间的第二串联开关SE2、连接在天线ANT和第三端口P3之间的第三串联开关SE3、连接在第一端口P1和地之间的第一分路开关SH1、连接在第二端口P2和地之间的第二分路开关SH2以及连接在第三端口P3和地之间的第三分路开关SH3。
CMOS结构的晶体管可应用于第一串联开关SE1、第二串联开关SE2、第三串联开关SE3以及第一分路开关SH1、第二分路开关SH2和第三分路开关SH3中的每个。
如上所述，在通过BiCMOS工艺(其中，通过将高电阻率区域设置在多个堆叠或成组的CMOS晶体管中的彼此相邻的两个CMOS晶体管之间，高电阻率区域和低电阻率区域彼此分开)的CMOS晶体管中，可通过减小CMOS晶体管之间的干扰来改善插入损耗。
虽然本公开包括具体示例，但是在理解本申请的公开内容之后将显而易见的是，在不脱离权利要求及其等同物的精神和范围的情况下，可在这些示例中进行形式和细节上的各种改变。在此描述的示例将仅被认为是描述性含义，而不是出于限制的目的。每个示例中的特征或方面的描述将被认为是可适用于其他示例中的相似的特征或方面。如果以不同的顺序执行描述的技术，和/或如果以不同的方式组合和/或用其他组件或其等同物替代或补充描述的系统、架构、装置或电路中的组件，则可获得合适的结果。因此，本公开的范围不是由具体实施方式限定，而是由权利要求及其等同物限定，并且在权利要求及其等同物的范围内的所有变型将被解释为包括在本公开中。

Claims (18)

1.一种互补金属氧化物半导体器件，包括：
高电阻率基板；
第一互补金属氧化物半导体结构，设置在所述高电阻率基板的第一区域中；以及
第二互补金属氧化物半导体结构，与所述第一互补金属氧化物半导体结构的半导体类型相同，并且设置在所述高电阻率基板的与所述第一区域分开的第二区域中，
其中，所述高电阻率基板设置在所述第一互补金属氧化物半导体结构和所述第二互补金属氧化物半导体结构之间，以将所述第一互补金属氧化物半导体结构与所述第二互补金属氧化物半导体结构分开。
2.根据权利要求1所述的互补金属氧化物半导体器件，其中，所述第一互补金属氧化物半导体结构和所述第二互补金属氧化物半导体结构中的每个是三阱结构。
3.根据权利要求1所述的互补金属氧化物半导体器件，其中，所述第一互补金属氧化物半导体结构包括堆叠为第一三阱结构的第一低电阻率层、第一深N阱层和第一P阱层。
4.根据权利要求1所述的互补金属氧化物半导体器件，其中，所述第二互补金属氧化物半导体结构包括堆叠为第二三阱结构的第二低电阻率层、第二深N阱层和第二P阱层。
5.根据权利要求2所述的互补金属氧化物半导体器件，其中，所述第一互补金属氧化物半导体结构包括：
第一低电阻率层，堆叠在所述高电阻率基板的所述第一区域中；
第一深N阱层，设置在所述第一低电阻率层上并且被所述第一低电阻率层围绕；
第一P阱层，设置在所述第一深N阱层上并且被所述第一深N阱层围绕；以及
第一源极区域、第一漏极区域和第一栅极区域，设置在所述第一P阱层中以分别形成所述第一互补金属氧化物半导体结构的源极、漏极和栅极。
6.根据权利要求5所述的互补金属氧化物半导体器件，其中，所述第二互补金属氧化物半导体结构包括：
第二低电阻率层，堆叠在所述高电阻率基板的所述第二区域中；
第二深N阱层，设置在所述第二低电阻率层上并且被所述第二低电阻率层围绕；
第二P阱层，设置在所述第二深N阱层上并且被所述第二深N阱层围绕；以及
第二源极区域、第二漏极区域和第二栅极区域，设置在所述第二P阱层中以分别形成所述第二互补金属氧化物半导体结构的源极、漏极和栅极。
7.根据权利要求6所述的互补金属氧化物半导体器件，其中，所述高电阻率基板的电阻率值大于所述第一低电阻率层的电阻率值和所述第二低电阻率层的电阻率值二者。
8.根据权利要求6所述的互补金属氧化物半导体器件，其中，所述高电阻率基板的在所述第一互补金属氧化物半导体结构和所述第二互补金属氧化物半导体结构之间的区域的厚度比所述第一低电阻率层的厚度和所述第二低电阻率层的厚度二者厚，并且所述高电阻率基板的所述厚度比所述第一低电阻率层和所述第一深N阱层的总厚度以及所述第二低电阻率层和所述第二深N阱层的总厚度二者薄。
9.一种互补金属氧化物半导体器件，包括：
高电阻率基板；
第一三阱结构的第一互补金属氧化物半导体结构，设置在所述高电阻率基板的第一区域中；以及
第二三阱结构的第二互补金属氧化物半导体结构，设置在所述高电阻率基板的与所述第一区域分开的第二区域中，
其中，所述高电阻率基板设置在所述第一三阱结构和所述第二三阱结构之间，以将所述第一三阱结构与所述第二三阱结构分开。
10.根据权利要求9所述的互补金属氧化物半导体器件，其中，所述第一互补金属氧化物半导体结构与所述第二互补金属氧化物半导体结构的半导体类型相同。
11.根据权利要求9所述的互补金属氧化物半导体器件，其中，所述第一互补金属氧化物半导体结构的所述第一三阱结构包括堆叠的第一低电阻率层、第一深N阱层和第一P阱层。
12.根据权利要求9所述的互补金属氧化物半导体器件，其中，所述第二互补金属氧化物半导体结构的所述第二三阱结构包括堆叠的第二低电阻率层、第二深N阱层和第二P阱层。
13.根据权利要求10所述的互补金属氧化物半导体器件，其中，所述第一互补金属氧化物半导体结构包括：
第一低电阻率层，堆叠在所述高电阻率基板的所述第一区域中；
第一深N阱层，设置在所述第一低电阻率层上并且被所述第一低电阻率层围绕；
第一P阱层，设置在所述第一深N阱层上并且被所述第一深N阱层围绕；以及
第一源极区域、第一漏极区域和第一栅极区域，设置在所述第一P阱层中以分别形成所述第一互补金属氧化物半导体结构的源极、漏极和栅极。
14.根据权利要求13所述的互补金属氧化物半导体器件，其中，所述第二互补金属氧化物半导体结构包括：
第二低电阻率层，堆叠在所述高电阻率基板的所述第二区域中；
第二深N阱层，设置在所述第二低电阻率层上并且被所述第二低电阻率层围绕；
第二P阱层，设置在所述第二深N阱层上并且被所述第二深N阱层围绕；以及
第二源极区域、第二漏极区域和第二栅极区域，设置在所述第二P阱层中以分别形成所述第二互补金属氧化物半导体结构的源极、漏极和栅极。
15.根据权利要求14所述的互补金属氧化物半导体器件，其中，所述高电阻率基板的电阻率值大于所述第一低电阻率层的电阻率值和所述第二低电阻率层的电阻率值二者。
16.根据权利要求14所述的互补金属氧化物半导体器件，其中，所述高电阻率基板的在所述第一互补金属氧化物半导体结构和所述第二互补金属氧化物半导体结构之间的区域的厚度比所述第一低电阻率层的厚度和所述第二低电阻率层的厚度二者厚，并且所述高电阻率基板的所述厚度比所述第一低电阻率层和所述第一深N阱层的总厚度以及所述第二低电阻率层和所述第二深N阱层的总厚度二者薄。
17.一种互补金属氧化物半导体器件，包括：
基板；
第一互补金属氧化物半导体结构，设置在所述基板中并包括第一层；以及
第二互补金属氧化物半导体结构，设置在所述基板中并且包括第二层，所述第二层通过所述基板的设置在所述第一层和所述第二层之间的部分与所述第一层分开，所述基板的所述部分的电阻率高于所述第一层的电阻率和所述第二层的电阻率二者。
18.根据权利要求17所述的互补金属氧化物半导体器件，其中，所述基板的设置在所述第一层和所述第二层之间的所述部分的厚度大于所述基板的除了所述基板的设置在所述第一层和所述第二层之间的所述部分之外的部分的厚度。
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