CN110855143A

CN110855143A - Charge pump circuit for driving high-side power switch

Info

Publication number: CN110855143A
Application number: CN201911210764.2A
Authority: CN
Inventors: 任立; 张国俊
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2019-12-02
Filing date: 2019-12-02
Publication date: 2020-02-28

Abstract

A charge pump circuit suitable for driving a high-side power switch belongs to the technical field of electronic circuits. The method comprises the steps that the on and off of a charge-discharge loop are controlled through two externally input square wave signals with the same frequency and opposite phases, capacitors C1 and C2 are charged when the charge-discharge loop is turned on, the voltage of a pole plate on one side of each capacitor suddenly rises when the charge-discharge loop is turned off, and the voltage on the other side of each capacitor rises along with the voltage of the corresponding capacitor by utilizing the principle that the voltage of the capacitor cannot suddenly change; the output voltage of the charge pump is quickly raised in the continuous on-off process of the charge loop, so that the output voltage is higher than the power supply voltage to form a predicted value, and the grid of the power switch tube is successfully driven to be smoothly conducted. Compared with the traditional charge pump circuit, the design is rapid in opening and closing, and the value higher than the power supply voltage can be preset during circuit design.

Description

Charge pump circuit for driving high-side power switch

Technical Field

The invention belongs to the technical field of electronic circuits, and particularly relates to a charge pump circuit for driving a high-side power switch.

Background

High-side power switches are one of the typical circuits of power integrated circuits. The driving circuit, the control circuit and the protection circuit can be integrated in one chip, so that an intelligent control function is realized to a certain extent, the design difficulty of the chip is greatly reduced, and the performance of the chip is improved. The charge pump circuit is an essential driving circuit. With the increasing consumption demand of people on portable electronic devices, the requirements on the performance of chips related to power switches are increasingly improved due to the requirements on high performance, low power consumption, light weight and the like of electronic products, and the requirements on the performance of charge pump circuits are also increasingly higher.

The intelligent power switch integrates the control circuit, the protection circuit, the drive circuit, some peripheral interfaces and the power switch into an integrated chip. Wherein the driving circuit is a charge pump circuit. The intelligent power switch is divided into a high-side power switch and a low-side power switch, and the difference between the high side and the low side is that the MOS tube used as the switch is connected with a power supply end or a ground end. Different power switches are selected according to different application environments. The charge pump circuit is used as a driving circuit of the high-side power switch and is used for raising the grid voltage of the power switch tube to be higher than the power supply voltage.

Disclosure of Invention

The invention provides a charge pump circuit aiming at the requirement that a high-side power switch needs to raise a driving voltage to be higher than a power supply voltage, so that the grid voltage of the high-side power switch can be quickly raised to a fixed value higher than the power supply voltage under the condition of different working power supply voltages, and therefore, the quick conduction of a power switch tube is realized, and the switch normally works.

The technical scheme of the invention is as follows:

a charge pump circuit for driving a high-side power switch comprises resistors R1, R2 and R3, capacitors C1 and C2, MOS transistors M1 and M2 … … M11, diodes D1 and D2 … … D9, wherein a PMOS transistor M10 and an NMOS transistor M11 form an inverter Inv, an overvoltage protection structure is formed by D3, D4 … … D8 and the MOS transistor M8, and M9 is a high-side power switch MOS transistor driven by the charge pump;

PMOS tubes M1 and M2 form a current mirror, M1 is a bias tube, sources of M1 and M2 are connected with a power supply VDD, M4 is a switch tube, a grid electrode is connected with a starting voltage Vlogic, a drain of M4 is connected with a drain of M1, a source of M4 is connected with the upper end of a resistor R1, and the lower end of the resistor R1 is grounded.

The PMOS transistor M3 is a current source, the grid is connected with the grid of M2, the source is connected with the power VDD, the grids of the NMOS transistors M5 and M6 are connected with square wave voltage input from the outside, the frequency is equal, the phase is opposite, the drain of M5 is connected with the drain of M2, the drain of M6 is connected with the drain of M3, and the sources of M5 and M6 are both grounded.

The left pole plate of the capacitor C1 is connected with the drain of the M2, the right pole plate is connected with the anode of the diode D2, the left pole plate of the capacitor C2 is connected with the drain of the M3, the right pole plate is connected with the anode of the diode D1, and the cathode of the diode D1 is connected with the anode of the diode D2; the negative electrode of D2 is connected with the upper end of a resistor R2, the lower end of R2 is connected with the upper end of a resistor R3, and the lower end of R3 is the output of a charge pump structure and is connected with the grid electrode Vgate of a power tube.

The input of the inverter Inv is connected with a starting voltage Vlogic, the output is connected with the grid electrode of an NMOS tube M7, the drain electrode of M7 is connected with the upper end of a resistor R3, and the source electrode of M7 is grounded. The anode of the diode D9 is grounded, and the cathode is connected with the output voltage Vgate of the charge pump.

The cathode of a diode D8 is connected with a power voltage VDD, the anode of the diode D8 is connected with the cathode of a diode D7, the anode of D7 is connected with the cathode of a diode D6, the anode of D6 is connected with the cathode of a diode D5, the anode of D5 is connected with the cathode of a diode D4, the anode of D4 is connected with the cathode of a diode D3, the anode of D3 is connected with the drain of an NMOS tube M8, the grid of M8 is connected with the drain of M8, and the source of M8 is connected with the output.

The mirror image ratio of the PMOS tubes M1, M2 and M3 is 1: 1: 1; the mirror ratio of the NMOS transistors M5 and M6 is 1: 1; the mirror ratio of the NMOS transistors M4 and M7 is 1: 1; the proportion of a PMOS tube M10 to an NMOS tube M11 in the inverter Inv is 2: 1.

under the condition of different working voltages, the invention can quickly raise the output voltage to a fixed value higher than the power voltage and stabilize the output voltage at the fixed value until the starting voltage is closed. The grid electrode of the high-side power switch tube can be well driven to be rapidly controlled by the 5V starting voltage, and the method is simple and easy to implement.

Drawings

Fig. 1 is a circuit diagram of a charge pump circuit for driving a high-side power switch according to the present invention;

FIG. 2 is a waveform diagram of a simulation with varying turn-on voltage Vlogic;

FIG. 3 is an enlarged view of the front end of the voltage rise portion of the simulated waveform when the turn-on voltage Vlogic varies;

Detailed Description

In order to make the aforementioned and other features and advantages of the invention more apparent, a detailed description of the embodiments of the invention will be given below with reference to the accompanying drawings.

Fig. 1 shows a charge pump circuit for driving a high-side power switch, wherein M1, M2, and M3 form a current mirror circuit, when Vlogic is high, the branches M1 and M4 are turned on, and the same gate voltage is provided for M2 and M3, so that the currents of the branches M2 and M5 and the branches M3 and M6 are equal when turned on.

The square waves with the same frequency and opposite phases are input into ports Vp and Vn, when Vp is high level, Vn is low level, NMOS tube M5 is conducted, M6 is turned off, at this time, a charging loop composed of M3, C2, D1, C1 and M5 is conducted, capacitors C1 and C2 are charged, if voltage drops on M3, D1 and M5 are neglected, only two capacitors C1 and C2 of voltage are shared between VDD and GND, and if the capacitor values of the two capacitors are equal, the voltage on the right plate of C1 is raised to 0.5VDD after charging.

After the half period of the square wave passes, when Vp is changed to be low level, Vn is changed to be high level, the NMOS transistor M6 is turned on, the NMOS transistor M5 is turned off, the original charging loop for charging the capacitors C1 and C2 is turned off, and meanwhile, the voltage of the M2 is ignored, the voltage of the left plate of the C1 is instantly raised to VDD, and because the voltage of the capacitor cannot be suddenly changed, the voltage of the right plate of the C1 is also raised to 1.5 times of VDD, so that the voltage raising effect is realized.

By analogy, then Vn and Vp are repeatedly turned on and off, and the voltage at the right plate of C1 will continuously rise. However, because the output Vgate end branch is connected with a reverse biased diode chain consisting of diodes D3-D8 and a diode-connected NMOS transistor M8, the maximum Vgate voltage at the output can only be higher than VDD by a fixed value, and when the reverse biased diodes are further raised, the reverse biased diodes are turned on, so that the voltage at the Vgate is not too high, and the gate of the main power transistor is not broken down by the too high voltage, and the main power transistor is in a linear region during normal operation. Because of the existence of such a protection circuit, after stepping up to a voltage higher than VDD by a certain value, Vgate will stabilize at a voltage slightly higher than the power voltage VDD, and drive the power MOS transistor M9. The difference between this final stable output voltage Vgate and the supply voltage VDD can be obtained by adjusting the parameters of each tube or the number of tubes in the diode chain.

The diode D9 is a reverse biased diode with higher voltage resistance, and is also an overvoltage protection tube at the Vgate terminal, when the Vgate terminal voltage is close to the highest voltage that the gate of the power tube can bear, the reverse biased diode D9 will break down, and the current of the Vgate will be discharged.

When the Vlogic voltage is low, the branch in which M1 is located is turned off, M2 and M3 cannot obtain the required gate voltage to turn off the branch in which M3578 is located, and the voltage connected to the gate of the NMOS transistor M7 after passing through the inverter is high, so that the gate is turned on to pull down the voltage at Vgate quickly.

Fig. 2 is a simulation waveform of the charge pump circuit when the input Vlogic changes. In this simulation, the input square wave frequency with the power supply voltage VDD of 40V, Vp and Vn of 500KHz is taken as an example. It can be seen that when Vlogic is high, the output Vgate will rise rapidly, and then its voltage value stabilizes at a value slightly higher than the power supply voltage and no longer changes, and when Vlogic is turned off, the output Vgate will also be pulled down rapidly to 0V and stabilize until the next Vlogic high level comes.

Fig. 3 is an enlarged view of the front end of the voltage rising portion of the simulation waveform when the turn-on voltage Vlogic changes. As mentioned above, after Vlogic exceeds the threshold voltage of the M4 transistor, the voltage at the output Vgate is pulled up rapidly, and starts to rise in a step shape along with the square wave signals input by Vp and Vn, and keeps rising after reaching the power voltage of 40V, until reaching 42V or more, the voltage value will not be stable.

It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims

1. A charge pump circuit for driving a high-side power switch is characterized by comprising resistors R1, R2 and R3, capacitors C1 and C2, MOS transistors M1 and M2 … … M11, and diodes D1 and D2 … … D9.

2. The charge pump circuit of claim 1, wherein the PMOS transistors M1 and M2 form a current mirror, M1 is a bias transistor, M1 and M2 are connected to VDD, M4 is a switch transistor, the gate is connected to the turn-on voltage Vlogic, M4 is connected to M1, M4 is connected to R1, and the lower end of R1 is grounded; the PMOS tube M3 is a current source, the grid electrode is connected with the grid electrode of M2, the source electrode is connected with a power supply VDD, the grid electrodes of the NMOS tubes M5 and M6 are connected with square wave voltage input from the outside, the frequency is equal, the phase is opposite, the drain electrode of M5 is connected with the drain electrode of M2, the drain electrode of M6 is connected with the drain electrode of M3, and the source electrodes of M5 and M6 are both grounded; the left pole plate of the capacitor C1 is connected with the drain of the M2, the right pole plate is connected with the anode of the diode D2, the left pole plate of the capacitor C2 is connected with the drain of the M3, the right pole plate is connected with the anode of the diode D1, and the cathode of the diode D1 is connected with the anode of the diode D2; the negative electrode of D2 is connected with the upper end of a resistor R2, the lower end of R2 is connected with the upper end of a resistor R3, the lower end of R3 is output by a charge pump structure and is connected with a grid electrode Vgate of a power tube; the DE inverter is composed of a PMOS tube M10 and an NMOS tube M11, the input of the DE inverter Inv is connected with a starting voltage Vlogic, the output of the DE inverter is connected with the grid electrode of the NMOS tube M7, the drain electrode of the M7 is connected with the upper end of a resistor R3, and the source electrode of the M7 is grounded; the anode of the diode D9 is grounded, and the cathode is connected with the output voltage Vgate of the charge pump; the cathode of a diode D8 is connected with a power voltage VDD, the anode of the diode D8 is connected with the cathode of a diode D7, the anode of D7 is connected with the cathode of a diode D6, the anode of D6 is connected with the cathode of a diode D5, the anode of D5 is connected with the cathode of a diode D4, the anode of D4 is connected with the cathode of a diode D3, the anode of D3 is connected with the drain of an NMOS tube M8, the grid of M8 is connected with the drain of M8, and the source of M8 is connected with the output.

3. The charge pump circuit of claim 1, wherein the capacitors C1 and C2 are charge/discharge capacitors, and when the capacitors are fully charged, if the voltage on one side suddenly changes, the voltage on the other side suddenly changes according to the principle that the voltage of the capacitors cannot change instantaneously, so as to raise the voltage.

4. The charge pump circuit of claim 1, wherein the mirror ratio of the PMOS transistors M1, M2, M3 is 1: 1: 1; the mirror ratio of the NMOS transistors M5 and M6 is 1: 1; the mirror ratio of the NMOS transistors M4 and M7 is 1: 1; the proportion of a PMOS tube M10 to an NMOS tube M11 in the inverter Inv is 2: 1.