CN110854235A - Integration method of surface electrode ion trap, silicon optical addressing and detector and framework - Google Patents

Abstract

The invention provides a method for integrating surface electrode ion traps with silicon photo-addressing and detectors, comprising the steps of: forming a silicon grating and a silicon structure on a wafer, implanting and annealing the silicon structure; Etching the epitaxial window above and epitaxial silicon or germanium, ion implantation and annealing to form a silicon-based photodetector; depositing a second dielectric layer and forming a first contact hole; depositing a third dielectric layer and forming several through-silicon holes; depositing a fourth A dielectric layer is formed and electrodes are formed, including a first electrode corresponding to a silicon-based photodetector and a second electrode of the surface electrode ion trap; a second contact hole and a third contact hole are formed downward from the first electrode; A third contact hole opposite to the TSV is formed at the bottom; the backside of the wafer is ground to expose the TSV; a passivation layer is deposited and a passivation layer is formed into a passivation layer window of the TSV, and a redistribution layer is formed at the passivation layer window and the first microbump under metal or the first microbump. The present invention also provides an integrated approach to the architecture.

Description

Method for integrating surface electrode ion traps with silicon photoaddressing and detectors, and architectures

technical field

The invention relates to the technical field of addressing and detection of ion trap quantum bits, in particular to a method for integrating surface electrode ion traps, silicon photonic addressing and detectors, and structures.

Background technique

Qubits are the basic operation units of quantum computers. Ion traps are one of the carriers for studying qubits because of their long coherence time and high fidelity of logic gates. The surface electrode ion trap of metal electrodes (RF electrodes and DC electrodes) is formed on the surface of the substrate by photolithography. Thanks to the mature semiconductor photolithography technology, various shapes of metal electrodes can be formed on the surface of the substrate. It is very convenient to prepare many identical metal electrodes and multiple silicon optical devices, that is, the expansion of the number of ion trapped regions and the expansion of addressing and detection can be easily realized.

At present, free-space multi-beam laser sources and photomultiplier tubes are mostly used for addressing/detection of surface electrode ion trap qubits. There are complex, expensive, bulky, large errors and low scalability of the optical path debugging system for addressing/detection. The problem has always restricted the research and development of quantum computing science.

SUMMARY OF THE INVENTION

In view of the above problems, the purpose of the present invention is to provide a method for integrating surface electrode ion traps, silicon photo-addressing and detectors, and structures with strong stability, miniaturization, versatility and scalability.

In order to achieve the above-mentioned purpose, the present invention adopts the following technical scheme, the integration method of surface electrode ion trap and silicon optical addressing and detector, comprising the following steps:

Provide a wafer, photolithography and etching on the top layer of the wafer to form a silicon grating and a silicon structure, and perform ion implantation and annealing on the silicon structure;

Depositing a first dielectric layer, etching the first dielectric layer above the silicon structure to form an epitaxial window, and epitaxial silicon or germanium from the top layer of the silicon structure through the epitaxial window, ion implantation and annealing to form a silicon single photon avalanche detector or silicon base germanium single photon avalanche detector;

A second dielectric layer is deposited, etched and chemically mechanically polished, and a first contact hole of a surface incident type silicon single photon avalanche detector or a silicon-based germanium single photon avalanche detector is formed downward from the top layer of the second dielectric layer;

depositing a third dielectric layer, and forming a plurality of through silicon vias downward from the top layer of the third dielectric layer;

A fourth dielectric layer is deposited, and an electrode is formed on the top layer of the fourth dielectric layer, and the electrode includes a first electrode corresponding to a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector, and a second electrode of the surface electrode ion trap; Each first electrode corresponds to a first contact hole and a through silicon hole, and a second contact hole and a third contact hole connected to the first contact hole and the through silicon hole are respectively formed downward from the bottom of each first electrode; Each of the second electrodes corresponds to a TSV, and a third contact hole connected to the TSV is formed downward from the bottom of each second electrode;

Grind the backside of the wafer to expose the TSVs;

deposit a passivation layer on the backside of the wafer;

Etching the passivation layer, forming a passivation layer window of the TSV, and forming a redistribution layer and a first micro-bump metal or a first micro-bump at the passivation layer window; or forming a passivation layer window The first microbump under metal or the first microbump.

Preferably, the step of forming the first contact hole downward from the top layer of the second dielectric layer includes:

Etching down from the top layer of the second dielectric layer to form a first hole;

depositing a first isolation layer on the sidewall and bottom of the first hole;

Electrochemically coating or depositing a first metal in the first hole;

chemical mechanical polishing or etching to remove the first metal and the first isolation layer on the surface of the second dielectric layer.

Preferably, the first metal is copper, and the first hole is filled with copper by an electrochemical coating process, followed by annealing and chemical mechanical polishing;

After forming the first contact hole and before depositing the third dielectric layer, a first stop layer is deposited.

Preferably, the step of forming through silicon vias downward from the top layer of the third dielectric layer includes:

Etching down from the top layer of the third dielectric layer to form a second hole;

depositing a second isolation layer on the sidewall and bottom of the second hole;

Electrochemically coating a second metal in the second hole;

chemical mechanical polishing to remove the second metal and the second isolation layer on the surface of the third dielectric layer.

Preferably, the second metal is copper, and the second hole is filled with copper by an electrochemical coating process, followed by annealing and chemical mechanical polishing;

After the TSV is formed and before the fourth dielectric layer is deposited, a second stop layer is deposited.

Preferably, the step of forming the electrode, the second contact hole and the third contact hole includes:

A plurality of electrode grooves are formed by etching on the top layer of the fourth dielectric layer, respectively, and are etched downward from the groove bottom of the electrode groove to form a third hole and a fourth hole;

depositing a third isolation layer on the sidewall and bottom of the electrode groove, the third hole and the fourth hole;

Electrochemically coating or depositing a third metal in the electrode tank, the third hole and the fourth hole;

chemical mechanical polishing or etching to remove the third metal and the third isolation layer on the surface of the fourth dielectric layer.

Preferably, the first isolation layer, the second isolation layer and the third isolation layer are any one of Ta, TaN or Ta+TaN.

Preferably, the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are all silicon dioxide dielectric layers.

Preferably, both the first stop layer and the second stop layer are silicon nitride.

Preferably, the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are formed by a plasma-enhanced chemical vapor deposition method.

Preferably, the first hole, the third hole, the fourth hole and the electrode groove are formed by dry etching.

Preferably, the second hole is formed using DRIE etching.

Preferably, the vertical distance between the TSV and the adjacent surface of the silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector is not less than 1.5 times the diameter of the TSV;

And the vertical distance between the central axes of two adjacent TSVs is not less than 3 times the diameter of the TSVs.

The present invention also provides another method for integrating surface electrode ion traps with silicon photo-addressing and detectors, comprising the following steps:

Provide a wafer, and photolithography and etching the top layer of the wafer to form a silicon structure, or a silicon structure and a silicon grating; perform ion implantation and annealing on the silicon structure;

depositing a first dielectric layer and a silicon nitride layer in sequence, and photolithography and etching on the top layer of the silicon nitride layer to form a silicon nitride grating;

depositing a second dielectric layer, etching the first dielectric layer and the second dielectric layer above the silicon structure to form an epitaxial window, and epitaxial silicon or germanium from the top layer of the silicon structure through the epitaxial window, ion implantation and annealing to form a silicon single photon avalanche detectors or silicon-based germanium single-photon avalanche detectors;

A third dielectric layer is deposited, etched and chemically mechanically polished, and a first contact hole of a surface incident type silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector is formed downward from the top layer of the third dielectric layer;

depositing a fourth dielectric layer; forming a plurality of through silicon vias downward from the top layer of the fourth dielectric layer;

depositing a fifth dielectric layer; forming electrodes on the top layer of the fifth dielectric layer, the electrodes comprising a first electrode corresponding to a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector, and a second electrode of the surface electrode ion trap; Each first electrode corresponds to a first contact hole and a through silicon hole, and a second contact hole and a third contact hole connected to the first contact hole and the through silicon hole are respectively formed downward from the bottom of each first electrode; Each of the second electrodes corresponds to a TSV, and a third contact hole opposite to the TSV is respectively formed downward from the bottom of each second electrode;

Grind the backside of the wafer to expose the TSVs;

deposit a passivation layer on the backside of the wafer;

Etching the passivation layer, forming a passivation layer window of the TSV, and forming a redistribution layer and a first micro-bump metal or a first micro-bump at the passivation layer window; or forming a passivation layer window The first microbump under metal or the first microbump.

The present invention also provides a method for integrating the architecture, comprising the following steps:

The redistribution layer of the integrated structure and the first micro-bump or the metal under the first micro-bump prepared by the integration method of the present invention are bonded to the silicon interposer, or the first micro-bump or the first micro-bump of the integrated structure is used. Metal-bonded silicon interposer under micro-bumps;

The silicon interposer is communicated with the packaging substrate through the second micro-bumps or the metal under the second micro-bumps disposed on the back of the silicon interposer, or communicated with the packaging substrate through leads;

Or, the redistribution layer of the integrated structure and the first micro-bump or the metal under the first micro-bump are directly communicated with the package substrate.

Preferably, the metal under the second micro-bump is Cu/Ni/Au and the second micro-bump is Cu/Ni/SnAg.

According to an exemplary embodiment of the present invention, the surface electrode ion trap is integrated with a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector, a silicon grating and/or a silicon nitride grating and a through silicon via, and after power-on, the surface electrode is used An ion trap traps ions and traps them within a certain range. The laser source is coupled to the silicon grating and/or silicon nitride grating by any coupling method such as end-face coupling, and the laser is emitted to the ions through the silicon grating and/or silicon nitride grating in three directions to complete the addressing. After the ion is excited by light, an energy level transition can occur. After the energy level transition, the ion radiates fluorescence, and the fluorescence is detected by a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector, and finally the detection of qubit information is completed. Compared with the traditional addressing and detection in the free space domain, the optical path debugging system is simplified, the space requirements for planning and debugging the optical path are reduced, the size of the integrated chip is reduced, and the integration degree is improved. Furthermore, when the addressing and detection methods of free space are adopted, the optical path of the optical path is easily disturbed by external factors such as vibrations, resulting in an unstable phenomenon, and the present invention can avoid the occurrence of the above-mentioned unstable phenomenon. In addition, the present invention can integrate silicon single photon avalanche detectors or silicon-based germanium single photon avalanche detectors, through-silicon vias and The number of silicon gratings and/or silicon nitride gratings has good versatility and scalability.

Description of drawings

1 is a flowchart of a method for integrating a surface electrode ion trap with a silicon photoaddressing and detector according to an embodiment of the present invention;

2 is a flow chart of a method for integrating surface electrode ion traps with silicon photoaddressing and detectors according to another embodiment of the present invention;

FIG. 3 is a flowchart of a method for integrating the architecture of an embodiment provided by the present invention.

Detailed ways

Specific embodiments according to the present invention will be described below with reference to the accompanying drawings.

Many specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can also be implemented in other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed below. limit.

In order to solve the technical problems of complex optical path debugging, weak stability and low scalability in the addressing/detection of existing qubits, the present invention provides a surface electrode ion trap, a silicon optical addressing and detector, and a structure of the integrated approach.

FIG. 1 shows an embodiment of a method for integrating a surface electrode ion trap with a silicon photoaddressing and detector provided by the present invention, which includes the following steps:

S10, providing a wafer, photolithography and etching on the top layer of the wafer to form a silicon grating and a silicon structure, and performing ion implantation and annealing on the silicon grating;

It should be further noted that the wafer is preferably an SOI (Silicon-On-Insulator, silicon on insulating substrate) wafer with a high-resistance substrate, which has a top layer silicon, a back substrate and a silicon-on-insulator wafer in between. Buried oxide layer.

Photolithography and etching are sequentially performed on the top layer silicon using any of the existing photolithography and etching methods to form a silicon grating. The silicon grating has the function of emitting a certain wavelength of laser light at an exit angle determined according to the design of the micro-nano structure. .

In the process of forming the silicon grating, a silicon structure is formed on the top layer silicon on one side of the silicon grating, that is, the process and process parameters for forming the silicon structure are the same as those for forming the silicon grating.

After the silicon structure is formed, any existing method is used for ion implantation and annealing, and the implanted ions are boron and phosphorus to form P-type doping and N-type doping.

S11, depositing to form a first dielectric layer, etching the first dielectric layer above the silicon structure to form an epitaxial window, and epitaxial silicon or germanium from the top layer of the silicon structure through the epitaxial window, ion implantation and annealing to form a silicon single-photon avalanche photodetector or silicon-based germanium single-photon avalanche photodetectors;

In this step, a first dielectric layer is formed on the top layer of the wafer with the silicon grating and the silicon structure, preferably by plasma-enhanced chemical vapor deposition (PECVD). The first dielectric layer is preferably a silicon dioxide dielectric layer. Of course, It can also be other first dielectric layers that can also play the role of isolation.

Preferably, low temperature annealing treatment and chemical mechanical polishing (CMP) treatment may be performed after depositing to form the first dielectric layer.

Optionally, the low-temperature annealing treatment and chemical mechanical polishing treatment may not be performed after the first dielectric layer is formed by deposition.

An epitaxial window is formed by etching on the first dielectric layer corresponding to the silicon structure, and epitaxial silicon or epitaxial germanium is formed on the top layer of the silicon structure through the epitaxial window, that is, silicon or germanium is formed in the space formed by the top layer of the silicon structure and the window. , and further ion implantation and annealing are performed to finally form a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector. The implanted ions are boron and phosphorus to form P-type doping and N-type doping. The silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector physically includes an absorption layer, a charge layer and a multiplication layer, and its function is to realize the detection of the fluorescence emitted by the ion energy level transition.

Preferably, the cross-sectional area of the structure corresponding to silicon or germanium is smaller than that of the silicon structure, and is distributed in the center of the silicon structure.

The silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector is integrated on the wafer by etching the top silicon of the wafer to form a silicon structure, epitaxial silicon or germanium, and ion implantation and annealing, which has a high degree of integration. , and the advantages of small size.

S12, depositing a second dielectric layer, etching, chemical mechanical polishing, and forming a first contact hole of a surface incident type silicon single photon avalanche detector or a silicon-based germanium single photon avalanche detector from the top layer of the second dielectric layer downward;

In this step, on the top layer of the structure having the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector, the silicon grating and the first dielectric layer, a second dielectric layer may be deposited by a vapor deposition method such as plasma enhanced chemistry, The second dielectric layer may be a silicon dioxide dielectric layer.

After depositing and forming the second dielectric layer, a first contact hole of the surface incident type silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector is formed downward on the top layer of the second dielectric layer.

For example, the first contact hole may be formed by any one of a copper process, a tungsten process, a gold process, an aluminum process, or an aluminum-copper process.

The following will take the single damascene copper process as an example to describe the method for forming the first contact hole in detail, as follows:

Any existing etching method can be used, such as dry etching to etch down from the top of the second dielectric layer to form a number of first holes. The diameter of the first holes is not specifically limited here, and can be determined according to actual process conditions. Choose an appropriate value.

A first isolation layer is deposited on the sidewall and bottom of the first hole. The first isolation layer can be Ta, TaN or Ta+TaN. It should be noted that the first isolation layer is deposited on the entire structure with the first hole. That is, while the first isolation layer is formed on the sidewall and bottom of the first hole, the first isolation layer is also deposited on the second dielectric layer.

Continue to deposit the first copper seed layer in the first hole with the first isolation layer, and similarly, the first copper seed layer is also deposited on the second dielectric layer, specifically, on the first isolation layer.

Continue to fill the first hole with the first isolation layer and the first copper seed layer using an electrochemical coating process (ECP). Similarly, copper will also be plated on the second dielectric layer, specifically on the first hole. a copper seed layer;

After that, the copper, the first copper seed layer and the first isolation layer on the surface of the second dielectric layer are removed by means of annealing and chemical mechanical polishing, and finally the first hole, the first isolation layer formed in the first hole, The first copper seed layer and copper form a first contact hole flush with the top surface of the second dielectric layer.

The first contact hole is in contact with the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector, and the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector can be communicated with the electrode, so that the silicon single-photon avalanche detector can be detected power on the detector or silicon-based germanium single-photon avalanche detector.

After the single damascene copper process is used to form the first contact hole, in order to avoid oxidation of copper in the subsequent process, a first stop layer needs to be deposited on the top layer of the formed structure, and the first stop layer may be silicon nitride.

It should be further explained that if the first contact hole is formed by a copper process or a gold process, it is necessary to form copper and gold in the first hole by means of electrochemical plating, and annealing and chemical mechanical polishing are performed for the copper process. The gold process is chemical mechanical polishing. If an aluminum process or an aluminum-copper process is used to form the first contact hole, the aluminum or aluminum-copper needs to be formed in the first hole by deposition, and then etched. If the tungsten process is used, tungsten needs to be formed in the first hole by means of deposition, and then chemical mechanical polishing is performed.

S13, depositing a third dielectric layer, and forming a plurality of through silicon vias downward from the top layer of the third dielectric layer;

In this step, on the top layer of the second dielectric layer with the first contact hole or the first stop layer, a third dielectric layer may be deposited by a vapor deposition method such as plasma enhanced chemistry, that is, the first contact hole is formed by the third dielectric layer. Or the first stop layer is completely covered, and the third dielectric layer may be a silicon dioxide dielectric layer.

After depositing and forming the third dielectric layer, several through-silicon vias are formed downward on the top layer of the third dielectric layer.

Through silicon vias can be formed using any of copper, tungsten, or gold processes, but copper is usually used.

The following will take the single damascene copper process as an example to describe the method of forming through silicon vias in detail, as follows:

The second hole may be formed by DRIE etching, and the diameter of the second hole is not specifically limited here, and an appropriate value may be selected according to actual application requirements and DRIE process conditions.

A second isolation layer is deposited on the sidewall and bottom of the second hole. The second isolation layer can be Ta, TaN or Ta+TaN. It should be noted that the second isolation layer is deposited on the entire structure with the second hole. That is, while the second isolation layer is formed on the sidewall and bottom of the second hole, the second isolation layer is also deposited on the third dielectric layer;

Continue to deposit a second copper seed layer in the second hole with the second isolation layer, and the second copper seed layer is also deposited on the third dielectric layer, specifically on the second isolation layer;

Continue to fill the second hole with the second isolation layer and the second copper seed layer by means of electrochemical plating, and copper will also be plated on the third dielectric layer, specifically on the second copper seed layer. ;

After that, the copper, the second copper seed layer and the second isolation layer on the surface of the third dielectric layer are removed by means of annealing and chemical mechanical polishing, and finally the second hole, the second isolation layer formed in the second hole, The second copper seed layer and copper form through silicon vias that are flush with the top surface of the third dielectric layer.

After the TSV is formed by the single damascene copper process, in order to avoid oxidation of copper in the subsequent process, a second stop layer needs to be deposited on the top layer of the formed structure, and the second stop layer may be silicon nitride.

TSVs enable vertical interconnections between electrodes in the ion trap chip and the underlying interposer.

The number of through-silicon vias is several, and the through-silicon vias are distributed on the side of the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector, and have a distance from the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector. a certain distance.

For example, the vertical distance between the through-silicon via and the adjacent surfaces of the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector is not less than 1.5 times the diameter of the through-silicon hole. The vertical distance between the central axes of two adjacent TSVs is not less than 3 times the diameter of the TSVs.

The through-silicon via has a preferred distance from the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector, as well as a preferred distance between adjacent through-silicon vias, which can avoid stress concentration at the through-silicon hole and affect the silicon single-photon. Adverse effects of avalanche detectors or silicon-based germanium single-photon avalanche detectors, or mutual adverse effects between TSVs.

It should be further explained that if the through-silicon via is formed by the copper process or the gold process, the copper and gold need to be formed in the second hole by electrochemical coating, and annealing and chemical mechanical polishing are performed for the copper process, while for the gold Process for chemical mechanical polishing. If the tungsten process is used, tungsten needs to be formed in the second hole by means of deposition, and then chemical mechanical polishing is performed.

S14, depositing a fourth dielectric layer, and forming an electrode on the top layer of the fourth dielectric layer, the electrode includes a first electrode corresponding to a silicon single photon avalanche detector or a silicon-based germanium single photon avalanche detector, and a second electrode of the surface electrode ion trap electrodes; each first electrode corresponds to a first contact hole and a through silicon hole, and a second contact hole and a third contact connected to the first contact hole and the through silicon hole are respectively formed downward from the bottom of each first electrode A hole; each second electrode corresponds to a through silicon hole, and a third contact hole opposite to the through silicon hole is respectively formed downward from the bottom of each second electrode.

In this step, on the top layer of the third dielectric layer or the second stop layer with the TSVs, a fourth dielectric layer may be deposited by a vapor deposition method such as plasma enhanced chemistry. The second stop layer is completely covered, and the fourth dielectric layer may be a silicon dioxide dielectric layer.

After depositing and forming the fourth dielectric layer, electrodes, second contact holes and third contact holes are formed downward on the top layer of the fourth dielectric layer.

The electrodes, the second contact holes, and the third contact holes may be formed using any one of a copper process, a tungsten process, a gold process, an aluminum process, and an aluminum-copper process.

The following will take the double damascene copper process as an example to describe the method of forming the electrode, the second contact hole and the third contact hole in detail, as follows:

In the fourth dielectric layer, any existing etching methods such as dry etching are used to form electrode grooves, and continue to etch downwards from the groove bottom of the electrode grooves to form third holes corresponding to the first contact holes and A fourth hole corresponding to the TSV.

A third isolation layer is deposited on the inside and bottom of the electrode groove, the third hole and the fourth hole at one time. The third isolation layer can be any one of Ta, TaN or Ta+TaN. It should be noted that the third isolation layer It is deposited on the entire structure with the electrode groove, the third hole and the fourth hole, that is, while the third isolation layer is formed on the sidewall and bottom of the electrode groove, the third hole and the fourth hole, the fourth dielectric layer is formed at the same time. There will also be a third isolation layer deposited on it;

Continue to deposit a third copper seed layer in the electrode groove with the third isolation layer, the third hole and the fourth hole, and the third copper seed layer is also deposited on the fourth dielectric layer, specifically on the third isolation layer ;

The electrode groove, the third hole and the fourth hole of the third copper seed layer with the third isolation layer and the third copper seed layer are filled with copper by means of electrochemical plating, and the copper will also be plated on the third dielectric layer , which is specifically plated on the second copper seed layer;

After that, the copper, the third copper seed layer and the third isolation layer on the fourth dielectric layer are removed by means of annealing and chemical mechanical polishing.

The electrode groove, the third isolation layer, the third copper seed layer and the copper constitute the first electrode and the second electrode of the electrode ion trap which can be opposite to the silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector; The three holes, the third isolation layer, the third copper seed layer and the copper form a second contact hole, and the second contact hole can connect the first electrode with the first contact hole, thereby connecting the first electrode with the silicon single photon avalanche detector or the silicon single photon avalanche detector. The silicon-based germanium single-photon avalanche detector is connected; the third contact hole is formed by the fourth hole, the third isolation layer, the third copper seed layer and the copper, and the third contact hole can connect the first electrode and the second electrode with the through silicon hole The first electrode is connected with the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector.

Annealing and mechanical polishing are performed after forming the first electrode, the second electrode, the second contact hole, and the third contact hole. Further, any existing passivation method is used to perform passivation treatment on the formed first electrode and the second electrode.

Moreover, when the first electrode and the second electrode are formed by the double damascene copper process, when the feature size of the first electrode and the second electrode is larger than 20 microns, a grid-type dielectric isolation structure needs to be provided to prevent subsequent chemical mechanical polishing, resulting in Depression on the copper surface.

It should be further explained that if the electrode, the second contact hole and the third contact hole are formed by the copper process or the gold process, it is necessary to form the copper and gold in the electrode groove, the third hole and the fourth hole by means of electrochemical plating Inside, annealing, chemical mechanical polishing is performed for copper processes, and chemical mechanical polishing is performed for gold processes. If the electrode, the second contact hole and the third contact hole are formed by the aluminum process or the aluminum-copper process, the aluminum or aluminum-copper needs to be formed in the electrode groove, the third hole and the fourth hole by deposition, and then the etching is performed. eclipse. If a tungsten process is used, tungsten needs to be deposited in the electrode groove, the third hole and the fourth hole, and then chemical mechanical polishing is performed.

S15, grinding the back of the wafer to expose the TSV;

In this step, a thermoplastic material can be used to temporarily bond the front side of the above-formed structure on a carrier wafer, and the carrier wafer can be a bulk silicon wafer.

The backside of the wafer is ground by any existing grinding process, so as to reduce the thickness of the wafer to expose the TSV.

S16, depositing a passivation layer on the backside of the wafer;

S17, etch the passivation layer to form the passivation layer window of the TSV, and form the redistribution layer and the metal under the first micro-bump or the first micro-bump at the passivation layer window, or at the passivation layer window The first microbump under metal or the first microbump is formed there.

In this step, the first micro-bumps are preferably formed at the passivation layer window by means of electrochemical coating;

Optionally, any one of the metals under the first micro-bumps is formed at the window of the passivation layer by means of electrochemical plating.

On the basis of the above embodiment, further, the metal under the first micro-bump is Cu/Ni/Au, and the first micro-bump is Cu/Ni/SnAg.

The present invention also provides a second embodiment of a method for integrating surface electrode ion traps with silicon photo-addressing and detectors, specifically referring to FIG. 2 :

S20, providing a wafer, photolithography and etching on the top layer of the wafer to form a silicon structure, or a silicon structure and a silicon grating; ion implantation and annealing of the silicon structure;

The structure of the wafer provided in this step may be the same as that of the wafer provided in step S10 of the first embodiment, and the difference from step S10 is that any existing photolithography and etching methods may be used on the top layer of the wafer Only the silicon structure is formed without forming the silicon grating, or, as in step S10, both the silicon structure and the silicon grating are formed.

S21, depositing a first dielectric layer and a silicon nitride layer in sequence, and photolithography and etching on the top layer of the silicon nitride layer to form a silicon nitride grating;

In this step, the method provided in step S11 may be used to deposit and form the first dielectric layer, which will not be repeated here.

Plasma-enhanced chemical vapor deposition (PECVD) deposition is preferably employed to form the silicon nitride layer.

On the top layer of the silicon nitride layer, any existing photolithography and etching methods are used to sequentially perform photolithography and etching to form a silicon nitride grating. The silicon nitride grating also has an output determined according to the design of the micro-nano structure. The effect of angularly emitting a certain wavelength of laser light.

S22, depositing a second dielectric layer, etching the first dielectric layer and the second dielectric layer above the silicon structure to form an epitaxial window, and epitaxial silicon or germanium from the top layer of the silicon structure through the epitaxial window, ion implantation and annealing to form silicon Single-photon avalanche detectors or silicon-based germanium single-photon avalanche detectors;

The second dielectric layer can be formed by deposition using the method provided in step S11 of the first embodiment, and the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector can also be formed by using the method provided in step S11. The difference is that the epitaxial window in step S11 penetrates the first dielectric layer, while the window in this step needs to penetrate the first dielectric layer and the second dielectric layer in this embodiment.

S23, depositing a third dielectric layer, etching and chemical mechanical polishing; forming a first contact hole of a surface incident type silicon single photon avalanche detector or a silicon-based germanium single photon avalanche detector from the top layer of the third dielectric layer downward;

The method for forming the first contact hole in this step is basically the same as the method for forming the first contact hole in step S12 of the first embodiment, and details are not repeated here.

S24, depositing a fourth dielectric layer; forming a plurality of through silicon vias downward from the top layer of the fourth dielectric layer;

The method for forming the TSV in this step is basically the same as the method for forming the TSV in step S13 of the first embodiment, and details are not repeated here.

S25, depositing a fifth dielectric layer, and forming an electrode on the top layer of the fifth dielectric layer. The electrode includes a first electrode corresponding to the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector, and a second electrode of the surface electrode ion trap. Electrodes; each first electrode corresponds to a first contact hole and a through silicon hole, and a second contact hole and a third contact that communicate with the first contact hole and the through silicon hole are respectively formed downward from the bottom of each first electrode A hole; each second electrode corresponds to a through silicon hole, and a third contact hole opposite to the through silicon hole is formed downward from the bottom of each of the second electrodes.

The method of forming the first electrode, the second electrode, the second contact hole and the third contact hole in this step is the same as the method of forming the first electrode, the second electrode, the second contact hole and the third contact in step S14 of the first embodiment The method of the hole is basically the same and will not be repeated here.

S26, grinding the back of the wafer to expose the TSV;

This step is the same as step S15 in the first embodiment, and is not repeated here.

S27, depositing a passivation layer on the backside of the wafer;

S28, etch the passivation layer to form the passivation layer window of the through silicon via, and form the redistribution layer and the metal under the first micro-bump or the first micro-bump at the passivation layer window, or form the passivation layer window The first microbump under metal or the first microbump is formed there.

This step is the same as step S17 in the first embodiment, and will not be repeated here.

On the basis of the above embodiment, further, the metal under the first micro-bump is Cu/Ni/Au, and the first micro-bump is Cu/Ni/SnAg.

To sum up, the present invention integrates surface electrode ion traps with silicon single-photon avalanche detectors or silicon-based germanium single-photon avalanche detectors, silicon gratings and/or silicon nitride gratings and through-silicon vias. An ion trap traps ions and traps them within a certain range. The laser source is coupled to the waveguide of the silicon grating and/or silicon nitride grating by any coupling method such as end-face coupling, or the method of integrating the laser source on-chip, and the laser passes through the silicon grating and/or silicon nitride grating in three directions. out onto the ions to complete the addressing. After the ion is excited by light, an energy level transition can occur. After the energy level transition, the ion radiates fluorescence, and the fluorescence is detected by a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector, and finally the detection of qubit information is completed. Compared with the traditional addressing and detection in the free space domain, the optical path debugging system is simplified, the space requirements for planning and debugging the optical path are reduced, the size of the integrated chip is reduced, and the integration degree is improved. Furthermore, when the addressing and detection methods of free space are adopted, the optical path of the optical path is easily disturbed by external factors such as vibrations, resulting in an unstable phenomenon, and the present invention can avoid the occurrence of the above-mentioned unstable phenomenon. In addition, the present invention can use the same integration method to integrate the number of silicon single-photon avalanche detectors, through-silicon holes and gratings that can satisfy the addressing and detection of the corresponding number of ions according to the number of ions to be captured, and has good versatility. and scalability.

The present invention also provides a method for integrating the architecture, comprising the following steps:

S30. The redistribution layer of the integrated structure prepared by the integration method of the surface electrode ion trap and the silicon photo-addressing and detector and the micro-bump or the metal under the micro-bump are bonded to the silicon interposer, or the first integrated structure is used. A micro-bump or a metal-bonded silicon interposer under the first micro-bump;

S31, the silicon interposer is communicated with the packaging substrate through the second micro-bumps or the metal under the second micro-bumps disposed on the back of the silicon interposer, or communicated with the packaging substrate through leads;

Or, the redistribution layer of the integrated structure and the first micro-bump or the metal under the first micro-bump are directly communicated with the package substrate.

On the basis of the above embodiment, further, the metal under the second micro-bump is Cu/Ni/Au, and the second micro-bump is Cu/Ni/SnAg.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (28)

1. The integration method of the surface electrode ion trap and the silicon optical addressing and detector is characterized by comprising the following steps of:

providing a wafer, photoetching and etching the top layer of the wafer to form a silicon grating and a silicon structure, and carrying out ion implantation and annealing on the silicon structure;

depositing a first medium layer, etching the first medium layer above the silicon structure to form an epitaxial window, and performing epitaxial growth on silicon or germanium from the top layer of the silicon structure through the epitaxial window to form a silicon single photon avalanche detector or a silicon germanium single photon avalanche detector after ion implantation and annealing;

depositing a second medium layer, etching, chemically and mechanically polishing, and forming a first contact hole of a surface incidence type silicon single photon avalanche detector or a silicon germanium single photon avalanche detector downwards from the top layer of the second medium layer;

depositing a third dielectric layer, and forming a plurality of through silicon vias downwards from the top layer of the third dielectric layer;

depositing a fourth dielectric layer, and forming an electrode on the top layer of the fourth dielectric layer, wherein the electrode comprises a first electrode corresponding to the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector and a second electrode of the surface electrode ion trap; each first electrode corresponds to the first contact hole and the silicon through hole, and a second contact hole and a third contact hole which are connected with the first contact hole and the silicon through hole are respectively formed downwards from the bottom of each first electrode; each second electrode corresponds to the through silicon via, and a third contact hole connected with the through silicon via is formed downwards from the bottom of each second electrode;

grinding the back surface of the wafer to expose the through silicon via;

depositing a passivation layer on the back side of the wafer;

etching the passivation layer to form a passivation layer window of the through silicon via, and forming a rewiring layer and a first micro-bump lower metal or a first micro-bump at the passivation layer window; or forming the first micro-bump under metal or the first micro-bump at the passivation layer window.

2. The method of claim 1, wherein the step of forming a first contact hole down from the top layer of the second dielectric layer comprises:

etching downwards from the top layer of the second dielectric layer to form a first hole;

depositing a first isolation layer on the side wall and the bottom of the first hole;

electrochemically plating or depositing a first metal in the first hole;

and chemically and mechanically polishing or etching to remove the first metal and the first isolating layer on the surface of the second dielectric layer.

3. The method of claim 2, wherein the first metal is copper, the first hole is filled with copper by an electrochemical plating process and annealed and chemically mechanically polished;

and depositing a first stop layer after the first contact hole is formed and before the third dielectric layer is deposited.

4. The method of claim 3, wherein the step of forming a through-silicon-via down from the top layer of the third dielectric layer comprises:

etching downwards from the top layer of the third dielectric layer to form a second hole;

depositing a second isolation layer on the side wall and the bottom of the second hole;

electrochemically plating a second metal in the second hole;

and chemically and mechanically polishing to remove the second metal and the second isolating layer on the surface of the third dielectric layer.

5. The method of claim 4, wherein the second metal is copper, the second hole is filled with copper by an electrochemical plating process and annealed and chemically mechanically polished;

and depositing a second stop layer after the silicon through hole is formed and before the fourth dielectric layer is deposited.

6. The method of claim 5, wherein the step of forming the electrode, the second contact hole, and the third contact hole comprises:

etching the top layer of the fourth dielectric layer respectively to form a plurality of electrode grooves, and etching downwards from the bottoms of the electrode grooves respectively to form a third hole and a fourth hole;

depositing a third isolating layer on the side walls and the bottoms of the electrode grooves, the third holes and the fourth holes;

electrochemically plating or depositing a third metal in the electrode groove, the third hole and the fourth hole;

and chemically and mechanically polishing or etching to remove the third metal and the third isolating layer on the surface of the fourth dielectric layer.

7. The method of claim 6, wherein the first, second and third spacers are any one of Ta, TaN or Ta + TaN.

8. The method of claim 1, wherein the first, second, third and fourth dielectric layers are silicon dioxide dielectric layers.

9. The method of claim 5, wherein the first and second stop layers are silicon nitride.

10. The method of claim 1, wherein the first, second, third and fourth dielectric layers are formed by plasma enhanced chemical vapor deposition.

11. The method of claim 6, wherein the first, third, fourth and electrode trenches are formed by dry etching.

12. The method of claim 4, wherein the second aperture is formed by DRIE etching.

13. The method of claim 1, wherein the surface electrode ion trap is integrated with a silicon photo-addressing and detection device,

the vertical distance between the through silicon via and the adjacent surface of the silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector is not less than 1.5 times of the diameter of the through silicon via;

and the vertical distance between the central axes of two adjacent through silicon holes is not less than 3 times of the diameter of the through silicon hole.

14. The integration method of the surface electrode ion trap and the silicon optical addressing and detector is characterized by comprising the following steps of:

providing a wafer, and photoetching and etching the top layer of the wafer to form a silicon structure, or the silicon structure and a silicon grating; performing ion implantation and annealing on the silicon structure;

depositing a first dielectric layer and a silicon nitride layer in sequence, and photoetching and etching the top layer of the silicon nitride layer to form a silicon nitride grating;

depositing a second medium layer, etching the first medium layer and the second medium layer above the silicon structure to form an epitaxial window, and performing ion implantation and annealing on silicon or germanium from the top layer of the silicon structure through the epitaxial window to form a silicon single photon avalanche detector or a silicon germanium single photon avalanche detector;

depositing a third medium layer, etching, chemically and mechanically polishing, and forming a first contact hole of the surface incidence type silicon single photon avalanche detector or silicon germanium single photon avalanche detector downwards from the top layer of the third medium layer;

depositing a fourth dielectric layer; forming a plurality of through silicon vias downwards from the top layer of the fourth dielectric layer;

depositing a fifth dielectric layer; forming an electrode on the top layer of the fifth dielectric layer, wherein the electrode comprises a first electrode corresponding to the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector and a second electrode of the surface electrode ion trap; each first electrode corresponds to the first contact hole and the silicon through hole, and a second contact hole and a third contact hole which are connected with the first contact hole and the silicon through hole are respectively formed downwards from the bottom of each first electrode; each second electrode corresponds to the silicon through hole, and a third contact hole opposite to the silicon through hole is formed downwards from the bottom of each second electrode;

grinding the back surface of the wafer to expose the through silicon via;

depositing a passivation layer on the back side of the wafer;

etching the passivation layer to form a passivation layer window of the through silicon via, and forming a rewiring layer and a first micro-bump lower metal or a first micro-bump at the passivation layer window; or forming the first micro-bump under metal or the first micro-bump at the passivation layer window.

15. The method of claim 14, wherein the step of forming a first contact hole down from the top layer of the third dielectric layer comprises:

etching downwards from the top layer of the third dielectric layer to form a first hole;

depositing a first isolation layer on the side wall and the bottom of the first hole;

electrochemically plating or depositing a first metal in the first hole;

and chemically and mechanically polishing or etching to remove the first metal and the first isolating layer on the surface of the third dielectric layer.

16. The method of claim 15, wherein the first metal is copper, the first hole is filled with copper using an electrochemical plating process and annealed and chemically mechanically polished; and depositing a first stop layer after the first contact hole is formed and before the fourth dielectric layer is deposited.

17. The method of claim 16, wherein the step of forming a through-silicon-via down the top layer of the fourth dielectric layer comprises:

etching downwards from the top layer of the fourth dielectric layer to form a second hole;

depositing a second isolation layer on the side wall and the bottom of the second hole;

electrochemically plating a second metal in the second hole;

and chemically and mechanically polishing to remove the second metal and the second isolating layer on the surface of the fourth dielectric layer.

18. The method of claim 17, wherein the second metal is copper, the second hole is filled with copper by an electrochemical plating process and annealed and chemically mechanically polished; and depositing a second stop layer after the silicon through hole is formed and before the fifth dielectric layer is deposited.

19. The method of claim 18, wherein the step of forming the electrode, the second contact hole, and the third contact hole comprises:

etching the top layer of the fifth dielectric layer respectively to form a plurality of electrode grooves, and etching downwards from the bottoms of the electrode grooves respectively to form a third hole and a fourth hole;

depositing a third isolating layer on the side walls and the bottoms of the electrode grooves, the third holes and the fourth holes;

electrochemically plating or depositing a third metal in the electrode groove, the third hole and the fourth hole;

and chemically and mechanically polishing or etching to remove the third metal and the third isolating layer on the surface of the fifth dielectric layer.

20. The method of claim 19, wherein the first, second and third spacers are any one of Ta, TaN or Ta + TaN.

21. The method of claim 14, wherein the first, second, third, fourth and fifth dielectric layers are silicon dioxide dielectric layers.

22. The method of claim 18, wherein the first stop layer and the second stop layer are both silicon nitride.

23. The method of claim 14, wherein the first, second, third, fourth, and fifth dielectric layers are formed by plasma enhanced chemical vapor deposition.

24. The method of claim 19, wherein the first, third, fourth and electrode trenches are formed by dry etching.

25. The method of claim 17, wherein the second aperture is formed by DRIE etching.

26. The method of claim 14, wherein the vertical distance between the through-silicon via and the adjacent surface of the silicon single photon avalanche detector or silicon-based germanium single photon avalanche detector is not less than 1.5 times the diameter of the through-silicon via;

and the vertical distance between the central axes of two adjacent through silicon holes is not less than 3 times of the diameter of the through silicon hole.

27. A method for integrating an architecture, comprising the steps of:

bonding a redistribution layer and a first micro-bump or first micro-under-bump metal of an integrated structure prepared using the integration method of any of claims 1-13 or 14-26 to a silicon interposer, or bonding the silicon interposer using the first micro-bump or first micro-under-bump metal of the integrated structure;

the silicon adapter plate is communicated with the packaging substrate through a second micro-bump or a second metal under the second micro-bump arranged on the back surface of the silicon adapter plate, or is communicated with the packaging substrate through a lead;

or the redistribution layer of the integrated structure and the first micro-bump or the first metal under the micro-bump are directly communicated with the packaging substrate.

28. The method of claim 27, wherein the second microbump under metal is Cu/Ni/Au; the second micro bump is Cu/Ni/SnAg.

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