CN110854235A - Integration method of surface electrode ion trap, silicon optical addressing and detector and framework - Google Patents
Integration method of surface electrode ion trap, silicon optical addressing and detector and framework Download PDFInfo
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
- H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0232—Optical elements or arrangements associated with the device
- H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
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- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
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Abstract
The invention provides an integration method of a surface electrode ion trap and a silicon optical addressing and detector, which comprises the following steps: forming a silicon grating and a silicon structure on a wafer, and implanting and annealing ions into the silicon structure; depositing a first dielectric layer, etching an epitaxial window above the silicon structure, extending silicon or germanium, and performing ion implantation and annealing to form a silicon-based photoelectric detector; depositing a second dielectric layer and forming a first contact hole; depositing a third dielectric layer and forming a plurality of silicon through holes; depositing a fourth dielectric layer and forming electrodes, wherein the electrodes comprise a first electrode corresponding to the silicon-based photoelectric detector and a second electrode of the surface electrode ion trap; forming a second contact hole and a third contact hole downward from the first electrode; forming a third contact hole opposite to the through-silicon via downward from the second electrode; grinding the back surface of the wafer to expose the through silicon via; depositing and passivating the layer to form a passivation layer window of the through silicon via, and forming a rewiring layer and a first micro-bump lower metal or a first micro-bump at the passivation layer window. The invention also provides an integration method of the architecture.
Description
Technical Field
The invention relates to the technical field of addressing and detection of ion trap qubits, in particular to a surface electrode ion trap, a silicon optical addressing and detector and an integration method of a framework.
Background
Qubits are the basic operation units of quantum computers, and ion traps are one of carriers for studying qubits because of the advantages of long coherence time, high fidelity of logic gates, and the like. The surface electrode ion trap of the metal electrode (radio frequency electrode and direct current electrode) is formed on the surface of the substrate through the photoetching technology, and the metal electrodes in various shapes can be formed on the surface of the substrate by benefiting from the mature semiconductor photoetching technology, and meanwhile, a plurality of same metal electrodes and a plurality of silicon optical devices can be conveniently prepared, so that the expansion of the number of the ion trapping areas and the expansion of addressing and detection can be easily realized.
At present, free space multi-beam laser sources and photomultiplier tubes are mostly adopted for addressing/detection of surface electrode ion well qubits, and the problems of complex, expensive, huge addressing/detection optical path debugging system, large error, low expandability and the like exist, so that research and development of quantum computing science are restricted all the time.
Disclosure of Invention
In view of the above problems, the present invention provides a method for integrating a surface electrode ion trap with a silicon optical addressing and detecting device and a structure, which has the advantages of high stability, miniaturization, versatility and expandability.
In order to achieve the purpose, the invention adopts the following technical scheme that the method for integrating the surface electrode ion trap and the silicon optical addressing and detector comprises the following steps:
providing a wafer, photoetching and etching the top layer of the wafer to form a silicon grating and a silicon structure, and carrying out ion implantation and annealing on the silicon structure;
depositing a first medium layer, etching the first medium layer above the silicon structure to form an epitaxial window, and extending silicon or germanium from the top layer of the silicon structure through the epitaxial window to form a silicon single photon avalanche detector or a silicon-based germanium single photon avalanche detector after ion implantation and annealing;
depositing a second medium layer, etching, chemically and mechanically polishing, and forming a first contact hole of a surface incidence type silicon single photon avalanche detector or a silicon germanium single photon avalanche detector downwards from the top layer of the second medium layer;
depositing a third dielectric layer, and forming a plurality of through silicon vias downwards from the top layer of the third dielectric layer;
depositing a fourth medium layer, and forming an electrode on the top layer of the fourth medium layer, wherein the electrode comprises a first electrode corresponding to a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector and a second electrode of a surface electrode ion trap; each first electrode corresponds to the first contact hole and the silicon through hole, and a second contact hole and a third contact hole which are connected with the first contact hole and the silicon through hole are respectively formed downwards from the bottom of each first electrode; each second electrode corresponds to the silicon through hole, and a third contact hole connected with the silicon through hole is formed downwards from the bottom of each second electrode;
grinding the back surface of the wafer to expose the through silicon via;
depositing a passivation layer on the back of the wafer;
etching the passivation layer to form a passivation layer window of the through silicon via, and forming a rewiring layer and a first microbump lower metal or a first microbump at the passivation layer window; or forming a first micro-bump under metal or a first micro-bump at the passivation layer window.
Preferably, the step of forming the first contact hole downward from the top layer of the second dielectric layer comprises:
etching downwards from the top layer of the second dielectric layer to form a first hole;
depositing a first isolation layer on the side wall and the bottom of the first hole;
electrochemically plating or depositing a first metal in the first hole;
and chemically and mechanically polishing or etching to remove the first metal and the first isolating layer on the surface of the second dielectric layer.
Preferably, the first metal is copper, the first hole is filled with copper by adopting an electrochemical plating process and is annealed and chemically and mechanically polished;
and depositing a first stop layer after the first contact hole is formed and before the third dielectric layer is deposited.
Preferably, the step of forming the through-silicon-via downward from the top layer of the third dielectric layer comprises:
etching downwards from the top layer of the third dielectric layer to form a second hole;
depositing a second isolation layer on the side wall and the bottom of the second hole;
electrochemically plating a second metal in the second hole;
and chemically and mechanically polishing to remove the second metal and the second isolating layer on the surface of the third dielectric layer.
Preferably, the second metal is copper, the second hole is filled with copper by adopting an electrochemical plating process and is annealed and chemically and mechanically polished;
and depositing a second stop layer after the silicon through hole is formed and before the fourth dielectric layer is deposited.
Preferably, the step of forming the electrode, the second contact hole and the third contact hole includes:
etching the top layer of the fourth dielectric layer respectively to form a plurality of electrode grooves, and etching downwards from the bottoms of the electrode grooves respectively to form a third hole and a fourth hole;
depositing a third isolating layer on the side walls and the bottoms of the electrode grooves, the third holes and the fourth holes;
electrochemically plating or depositing a third metal in the electrode groove, the third hole and the fourth hole;
and chemically and mechanically polishing or etching to remove the third metal and the third isolating layer on the surface of the fourth dielectric layer.
Preferably, the first isolation layer, the second isolation layer and the third isolation layer are all any one of Ta, TaN or Ta + TaN.
Preferably, the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are silicon dioxide dielectric layers.
Preferably, the first stop layer and the second stop layer are both silicon nitride.
Preferably, the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are formed by a plasma enhanced chemical vapor deposition method.
Preferably, the first hole, the third hole, the fourth hole, and the electrode groove are formed using dry etching.
Preferably, the second hole is formed using DRIE etching.
Preferably, the vertical distance between the through silicon via and the adjacent surface of the silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector is not less than 1.5 times of the diameter of the through silicon via;
and the vertical distance between the central axes of two adjacent through silicon vias is not less than 3 times of the diameter of the through silicon via.
The invention also provides another method for integrating the surface electrode ion trap with the silicon optical addressing and detector, which comprises the following steps:
providing a wafer, and photoetching and etching the top layer of the wafer to form a silicon structure, or the silicon structure and a silicon grating; carrying out ion implantation and annealing on the silicon structure;
depositing a first dielectric layer and a silicon nitride layer in sequence, and photoetching and etching the top layer of the silicon nitride layer to form a silicon nitride grating;
depositing a second medium layer, etching the first medium layer and the second medium layer above the silicon structure to form an epitaxial window, and extending silicon or germanium from the top layer of the silicon structure through the epitaxial window to form a silicon single photon avalanche detector or a silicon germanium single photon avalanche detector after ion implantation and annealing;
depositing a third medium layer, etching, chemically and mechanically polishing, and forming a first contact hole of a surface incidence type silicon single photon avalanche detector or a silicon germanium single photon avalanche detector downwards from the top layer of the third medium layer;
depositing a fourth dielectric layer; forming a plurality of through silicon vias downwards from the top layer of the fourth dielectric layer;
depositing a fifth dielectric layer; forming an electrode on the top layer of the fifth dielectric layer, wherein the electrode comprises a first electrode corresponding to a silicon single photon avalanche detector or a silicon germanium single photon avalanche detector and a second electrode of the surface electrode ion trap; each first electrode corresponds to the first contact hole and the silicon through hole, and a second contact hole and a third contact hole which are connected with the first contact hole and the silicon through hole are respectively formed downwards from the bottom of each first electrode; each second electrode corresponds to the silicon through hole, and a third contact hole opposite to the silicon through hole is formed downwards from the bottom of each second electrode;
grinding the back surface of the wafer to expose the through silicon via;
depositing a passivation layer on the back of the wafer;
etching the passivation layer to form a passivation layer window of the through silicon via, and forming a rewiring layer and a first microbump lower metal or a first microbump at the passivation layer window; or forming a first micro-bump under metal or a first micro-bump at the passivation layer window.
The invention also provides an integration method of the architecture, which comprises the following steps:
bonding a redistribution layer of the integrated structure and a first micro-bump or a first metal under the micro-bump to a silicon adapter plate, or bonding the first micro-bump or the first metal under the micro-bump to the silicon adapter plate;
the silicon adapter plate is communicated with the packaging substrate through a second micro-bump or a second metal under the second micro-bump arranged on the back surface of the silicon adapter plate, or is communicated with the packaging substrate through a lead;
or, the redistribution layer of the integrated structure and the first micro-bump or the first metal under the micro-bump are directly communicated with the packaging substrate.
Preferably, the second micro-bump under-metal is Cu/Ni/Au and the second micro-bump is Cu/Ni/SnAg.
According to the embodiment of the invention, the surface electrode ion trap is integrated with the silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector, the silicon grating and/or the silicon nitride grating and the silicon through hole, and after the surface electrode ion trap is electrified, ions are trapped and confined in a certain range. The laser source is coupled to the silicon grating and/or the silicon nitride grating by any coupling mode such as end face coupling, and the laser is emitted to ions through the silicon grating and/or the silicon nitride grating in three directions to complete addressing. After the ions are excited by light, energy level transition can occur, after the energy level transition, the ions can radiate fluorescence, and the fluorescence is detected by a silicon single photon avalanche detector or a silicon germanium single photon avalanche detector, so that the detection of quantum bit information is finally completed. Compared with the traditional addressing and detection of the free space domain, the method simplifies the light path debugging system, reduces the requirements of planning and debugging light paths on space, reduces the size of an integrated chip and improves the integration degree. Moreover, when the addressing and detecting mode of the free space is adopted, the light path of the optical fiber is easy to generate unstable phenomenon due to the interference of external factors such as vibration, and the like. Besides, the invention can integrate the number of silicon single photon avalanche detectors or silicon-based germanium single photon avalanche detectors, silicon through holes and silicon gratings and/or silicon nitride gratings which can meet the addressing and detection of the corresponding number of ions by adopting the same integration method according to the number of ions to be captured, and has better universality and expandability.
Drawings
FIG. 1 is a flow chart of a method of integrating a surface electrode ion trap with a silicon photo-addressing and detector according to one embodiment of the present invention;
FIG. 2 is a flow chart of a method of integrating a surface electrode ion trap with a silicon photo-addressing and detector according to another embodiment of the present invention;
FIG. 3 is a flow diagram of a method for integrating the architecture of one embodiment provided by the present invention.
Detailed Description
The following describes an embodiment according to the present invention with reference to the drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
The invention provides a surface electrode ion trap and silicon optical addressing and detector and an integration method of a framework, aiming at solving the technical problems of complex optical path debugging, weak stability, low expandability and the like of the existing addressing/detection of quantum bits.
Fig. 1 shows an embodiment of the integration method of the surface electrode ion trap and the silicon optical addressing and detecting device provided by the invention, which comprises the following steps:
s10, providing a wafer, photoetching and etching the top layer of the wafer to form a silicon grating and a silicon structure, and performing ion implantation and annealing on the silicon grating;
it needs to be further explained that: the wafer is preferably a SOI (Silicon-On-Insulator, Silicon On Insulator) wafer with a high impedance substrate having a top Silicon, a back substrate and a buried oxide layer therebetween.
And photoetching and etching are sequentially carried out on the top layer silicon by utilizing any one of the conventional photoetching and etching methods to form a silicon grating, and the silicon grating has the function of emitting laser with a certain wavelength at an emergent angle determined according to the design of a micro-nano structure.
In the process of forming the silicon grating, a silicon structure is formed on the top layer silicon on one side of the silicon grating, namely the process and the process parameters of the silicon structure are the same as those of the silicon grating.
After the silicon structure is formed, any one of the existing methods is adopted for ion implantation and annealing, and the implanted ions are boron and phosphorus to form P-type doping and N-type doping.
S11, depositing to form a first medium layer, etching the first medium layer above the silicon structure to form an epitaxial window, extending silicon or germanium from the top layer of the silicon structure through the epitaxial window, and performing ion injection and annealing to form a silicon single photon avalanche photodetector or a silicon germanium single photon avalanche photodetector;
in this step, a first dielectric layer is deposited on the top layer of the wafer having the silicon grating and the silicon structure, preferably by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, and the first dielectric layer is preferably a silicon dioxide dielectric layer, but may be other first dielectric layers that can also play a role in isolation.
Preferably, the deposition of the first dielectric layer may be followed by a low temperature annealing process and a Chemical Mechanical Polishing (CMP) process.
Optionally, after the first dielectric layer is deposited, low-temperature annealing and chemical mechanical polishing may not be performed.
And forming an epitaxial window on the first medium layer corresponding to the silicon structure by an etching method, and further performing ion implantation and annealing on the epitaxial window to form the silicon single photon avalanche detector or the silicon germanium single photon avalanche detector in a space formed by the top layer of the silicon structure and the window, wherein the epitaxial window is used for extending silicon or epitaxial germanium on the top layer of the silicon structure, namely silicon or germanium is formed in the space formed by the top layer of the silicon structure and the window. The implanted ions are boron and phosphorus to form P-type doping and N-type doping. The silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector comprises an absorption layer, a charge layer and a multiplication layer from a physical layer and is used for detecting fluorescence emitted by ion energy level transition.
Preferably, the cross-sectional area of the corresponding structure of silicon or germanium is smaller than that of the silicon structure, and is distributed in the central position of the silicon structure.
The silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector is integrated on the wafer by etching the top silicon of the wafer to form a silicon structure, extending silicon or germanium and carrying out ion implantation and annealing, and the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector has the advantages of high integration level, small size and the like.
S12, depositing a second medium layer, etching, chemically and mechanically polishing, and forming a first contact hole of a surface incidence type silicon single photon avalanche detector or a silicon germanium single photon avalanche detector downwards from the top layer of the second medium layer;
in this step, a second dielectric layer, which may be a silicon dioxide dielectric layer, may be deposited on the top layer of the structure having the silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector, the silicon grating, and the first dielectric layer by a vapor deposition method such as plasma enhanced chemical.
And after a second medium layer is formed by deposition, a first contact hole of a surface incidence type silicon single photon avalanche detector or a silicon germanium single photon avalanche detector is formed downwards on the top layer of the second medium layer.
For example, the first contact hole may be formed using any one of a copper process, a tungsten process, a gold process, an aluminum process, or an aluminum-copper process.
The method for forming the first contact hole will be described in detail below by taking a single damascene copper process as an example, specifically as follows:
any one of the existing etching methods, such as dry etching, may be used to etch downward from the top of the second dielectric layer to form a plurality of first holes, the aperture of the first holes is not specifically limited herein, and a suitable value may be selected according to actual process conditions.
Depositing a first isolation layer on the side wall and the bottom of the first hole, wherein the first isolation layer can be Ta, TaN or Ta + TaN, and it should be noted that the first isolation layer is deposited on the whole structure with the first hole, that is, the first isolation layer is deposited on the second dielectric layer while the first isolation layer is formed on the side wall and the bottom of the first hole.
The deposition of the first copper seed layer in the first hole with the first isolation layer is continued, and the first copper seed layer is deposited on the second dielectric layer, in particular on the first isolation layer.
Continuing to fill copper in the first hole with the first isolation layer and the first copper seed layer by using an electrochemical plating process (ECP), and similarly, plating the copper on the second dielectric layer, specifically on the first copper seed layer;
and finally, removing the copper, the first copper seed layer and the first isolating layer on the surface of the second dielectric layer by adopting an annealing and chemical mechanical polishing mode, and finally forming a first contact hole which is flush with the top surface of the second dielectric layer by the first hole, the first isolating layer formed in the first hole, the first copper seed layer and the copper.
The first contact hole is in contact with the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector, and the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector can be communicated with the electrode so as to electrify the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector.
After the first contact hole is formed by adopting a single damascene copper process, in order to avoid copper oxidation in subsequent processes, a first stop layer needs to be deposited on the top layer of the formed structure, and the first stop layer can be silicon nitride.
It should be further noted that, if the first contact hole is formed by using a copper process or a gold process, the copper and the gold are formed in the first contact hole by using an electrochemical plating method, and annealing and chemical mechanical polishing are performed for the copper process, while chemical mechanical polishing is performed for the gold process. If the first contact hole is formed by adopting an aluminum process or an aluminum-copper process, aluminum or aluminum-copper needs to be formed in the first hole by adopting a deposition mode, and then etching is carried out. If a tungsten process is used, tungsten is deposited into the first hole and then chemically mechanically polished.
S13, depositing a third dielectric layer, and forming a plurality of through silicon vias downwards from the top layer of the third dielectric layer;
in this step, a third dielectric layer may be deposited on the top layer of the second dielectric layer or the first stop layer having the first contact hole by a vapor deposition method such as plasma enhanced chemical, i.e., the third dielectric layer completely covers the first contact hole or the first stop layer, and the third dielectric layer may be a silicon dioxide dielectric layer.
And after a third dielectric layer is formed by deposition, a plurality of through silicon vias are formed downwards on the top layer of the third dielectric layer.
The through-silicon vias may be formed using any one of a copper process, a tungsten process, or a gold process, but copper is typically used.
The method for forming the through silicon via will be described in detail below by taking a single damascene copper process as an example, specifically as follows:
the second hole may be formed by DRIE etching, and the diameter of the second hole is not specifically limited herein, and may be selected to have a suitable value according to the actual application requirement and DRIE process conditions.
Depositing a second isolation layer on the side wall and the bottom of the second hole, wherein the second isolation layer can be Ta, TaN or Ta + TaN, and the second isolation layer is deposited on the whole structure with the second hole, namely the second isolation layer is formed on the side wall and the bottom of the second hole, and the second isolation layer is deposited on the third medium layer;
continuing to deposit a second copper seed layer in the second hole with the second isolation layer, wherein the second copper seed layer is also deposited on the third dielectric layer, particularly the second isolation layer;
continuously filling copper in a second hole with a second isolating layer and a second copper seed layer in an electrochemical plating mode, wherein the copper is plated on a third dielectric layer, particularly the second copper seed layer;
and finally, removing the copper, the second copper seed layer and the second isolating layer on the surface of the third medium layer by adopting an annealing and chemical mechanical polishing mode, and finally forming the silicon through hole which is flush with the top surface of the third medium layer by the second hole, the second isolating layer formed in the second hole, the second copper seed layer and the copper.
After the single damascene copper process is used to form the through-silicon via, in order to avoid oxidation of copper in subsequent processes, a second stop layer needs to be deposited on the top layer of the formed structure, and the second stop layer may be silicon nitride.
The silicon through hole can realize the vertical interconnection of the electrode in the ion trap chip and the lower adapter plate.
The number of the through silicon holes is a plurality, the through silicon holes are distributed on the side face of the silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector, and a certain distance is reserved between the through silicon holes and the silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector.
The method comprises the following steps: the vertical distance between the adjacent surfaces of the silicon through hole and the silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector is not less than 1.5 times of the diameter of the silicon through hole. The vertical distance between the central axes of two adjacent through silicon vias is not less than 3 times the diameter of the through silicon via.
The silicon through holes and the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector have the optimal distance, and the optimal distance is reserved between the adjacent silicon through holes, so that the adverse effect of stress concentration at the silicon through holes on the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector or the mutual adverse effect among the silicon through holes can be avoided.
It needs to be further explained that: if the through silicon via is formed by a copper process or a gold process, copper and gold are formed in the second hole by adopting an electrochemical plating mode, annealing and chemical mechanical polishing are carried out aiming at the copper process, and chemical mechanical polishing is carried out aiming at the gold process. If a tungsten process is used, tungsten is deposited into the second hole and then chemical mechanical polishing is performed.
S14, depositing a fourth medium layer, and forming an electrode on the top layer of the fourth medium layer, wherein the electrode comprises a first electrode corresponding to the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector and a second electrode of the surface electrode ion trap; each first electrode corresponds to the first contact hole and the silicon through hole, and a second contact hole and a third contact hole which are connected with the first contact hole and the silicon through hole are respectively formed downwards from the bottom of each first electrode; each second electrode corresponds to the silicon through hole, and a third contact hole opposite to the silicon through hole is formed downwards from the bottom of each second electrode.
In this step, a fourth dielectric layer may be deposited on the top layer of the third dielectric layer or the second stop layer having the through-silicon via by using a vapor deposition method such as plasma enhanced chemical, that is, the fourth dielectric layer completely covers the through-silicon via or the second stop layer, and the fourth dielectric layer may be a silicon dioxide dielectric layer.
And after a fourth dielectric layer is formed by deposition, an electrode, a second contact hole and a third contact hole are formed downwards on the top layer of the fourth dielectric layer.
The electrode, the second contact hole, and the third contact hole may be formed using any one of a copper process, a tungsten process, a gold process, an aluminum process, and an aluminum-copper process.
The method for forming the electrode, the second contact hole and the third contact hole will be described in detail below by taking the dual damascene copper process as an example, specifically as follows:
and forming an electrode groove on the fourth dielectric layer by adopting any one of the existing etching methods such as dry etching, and the like, and continuously etching downwards from the bottom of the electrode groove to form a third hole corresponding to the first contact hole and a fourth hole corresponding to the through silicon via.
Depositing a third isolating layer at one time on the inner sides and the bottoms of the electrode groove, the third hole and the fourth hole, wherein the third isolating layer can be any one of Ta, TaN or Ta + TaN, and the third isolating layer is deposited on the whole structure with the electrode groove, the third hole and the fourth hole, namely, the third isolating layer is deposited on the fourth dielectric layer while the third isolating layer is formed on the side walls and the bottoms of the electrode groove, the third hole and the fourth hole;
continuously depositing a third copper seed layer in the electrode groove with the third isolation layer, the third hole and the fourth hole, wherein the third copper seed layer is also deposited on the fourth dielectric layer, particularly the third isolation layer;
filling copper into the electrode groove, the third hole and the fourth hole of the third copper seed layer with the third isolating layer and the third copper seed layer in an electrochemical coating mode, wherein the copper is also plated on the third dielectric layer, specifically the second copper seed layer;
and removing the copper on the fourth dielectric layer, the third copper seed layer and the third isolating layer by adopting an annealing and chemical mechanical polishing mode.
A first electrode and a second electrode of an electrode ion trap which can be opposite to the silicon single photon avalanche detector or the silicon germanium single photon avalanche detector are formed by an electrode groove, a third isolating layer, a third copper seed layer and copper; a second contact hole is formed by the third hole, the third isolating layer, the third copper seed layer and copper, the second contact hole can communicate the first electrode with the first contact hole, and further communicate the first electrode with the silicon single photon avalanche detector or the silicon germanium single photon avalanche detector; and a third contact hole is formed by a fourth hole, a third isolating layer, a third copper seed layer and copper, and the third contact hole can communicate the first electrode and the second electrode with the through silicon via, so that the first electrode is communicated with the silicon single photon avalanche detector or the silicon germanium single photon avalanche detector.
Annealing and mechanical polishing are performed after the first electrode, the second contact hole, and the third contact hole are formed. Further, the formed first electrode and the second electrode are passivated by any one of the existing passivation methods.
Moreover, when the first electrode and the second electrode are formed by adopting a dual damascene copper process, when the characteristic size of the first electrode and the characteristic size of the second electrode are larger than 20 micrometers, a grid type dielectric isolation structure is required to be arranged to prevent the copper surface from being sunken when the subsequent chemical mechanical polishing is carried out.
It needs to be further explained that: if the electrode, the second contact hole and the third contact hole are formed by a copper process or a gold process, copper and gold are formed in the electrode groove, the third hole and the fourth hole by adopting an electrochemical plating mode, annealing and chemical mechanical polishing are carried out aiming at the copper process, and chemical mechanical polishing is carried out aiming at the gold process. If the electrode, the second contact hole and the third contact hole are formed by adopting an aluminum process or an aluminum-copper process, aluminum or aluminum-copper is formed in the electrode groove, the third hole and the fourth hole by adopting a deposition mode, and then etching is carried out. If the tungsten process is adopted, tungsten is formed in the electrode groove, the third hole and the fourth hole in a deposition mode, and then chemical mechanical polishing is carried out.
S15, grinding the back surface of the wafer to expose the through silicon via;
in this step, the front side of the formed structure may be temporarily bonded to a carrier wafer, which may be a bulk silicon wafer, using a thermoplastic material.
And grinding the back surface of the wafer by adopting any conventional grinding process so as to reduce the thickness of the wafer until the through silicon via is exposed.
S16, depositing a passivation layer on the back of the wafer;
and S17, etching the passivation layer to form a passivation layer window of the through silicon via, and forming a redistribution layer and a first micro-bump lower metal or a first micro-bump at the passivation layer window, or forming the first micro-bump lower metal or the first micro-bump at the passivation layer window.
In the step, a first micro-bump is formed at the window of the passivation layer preferably in an electrochemical coating mode;
optionally, any one of the first micro under bump metals is formed at the passivation layer window by electrochemical plating.
Based on the above embodiments, the first micro-bump under-metal is Cu/Ni/Au, and the first micro-bump is Cu/Ni/SnAg.
The present invention also provides a second embodiment of a method for integrating a surface electrode ion trap with a silicon photo-addressing and detecting device, specifically referring to fig. 2:
s20, providing a wafer, and photoetching and etching the top layer of the wafer to form a silicon structure, or the silicon structure and a silicon grating; carrying out ion implantation and annealing on the silicon structure;
the structure of the wafer provided in this step may be the same as that of the wafer provided in step S10 of the first embodiment, and different from step S10, only a silicon structure may be formed on the top layer of the wafer by any conventional photolithography and etching method, and no silicon grating is formed, or both a silicon structure and a silicon grating may be formed in the same manner as in step S10.
S21, depositing a first dielectric layer and a silicon nitride layer in sequence, and photoetching and etching the top layer of the silicon nitride layer to form a silicon nitride grating;
in this step, the first dielectric layer may be deposited by the method provided in step S11, which is not described herein again.
Preferably by Plasma Enhanced Chemical Vapor Deposition (PECVD) to form the silicon nitride layer.
And photoetching and etching are sequentially carried out on the top layer of the silicon nitride layer by utilizing any conventional photoetching and etching method to form the silicon nitride grating, and the silicon nitride grating also has the function of emitting laser with a certain wavelength at an emergent angle determined according to the design of a micro-nano structure.
S22, depositing a second medium layer, etching the first medium layer and the second medium layer above the silicon structure to form an epitaxial window, extending silicon or germanium from the top layer of the silicon structure through the epitaxial window, and forming a silicon single photon avalanche detector or a silicon germanium single photon avalanche detector after ion injection and annealing;
the second dielectric layer may be deposited using the method provided in step S11 of the first embodiment and the silicon single photon avalanche detector or the silicon germanium single photon avalanche detector may be formed using the method provided in step S11 as well. The difference is that the epitaxial window in step S11 penetrates through the first dielectric layer, whereas the window in this step needs to penetrate through the first dielectric layer and the second dielectric layer in this embodiment.
S23, depositing a third dielectric layer, etching and chemically and mechanically polishing; a first contact hole of a surface incidence type silicon single photon avalanche detector or a silicon germanium single photon avalanche detector is formed downwards from the top layer of the third medium layer;
the method for forming the first contact hole in this step is substantially the same as the method for forming the first contact hole in step S12 of the first embodiment, and is not repeated here.
S24, depositing a fourth dielectric layer; forming a plurality of through silicon vias downwards from the top layer of the fourth dielectric layer;
the method for forming the through silicon via in this step is substantially the same as the method for forming the through silicon via in step S13 of the first embodiment, and is not described herein again.
S25, depositing a fifth dielectric layer, and forming an electrode on the top layer of the fifth dielectric layer, wherein the electrode comprises a first electrode corresponding to the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector and a second electrode of the surface electrode ion trap; each first electrode corresponds to the first contact hole and the silicon through hole, and a second contact hole and a third contact hole which are communicated with the first contact hole and the silicon through hole are respectively formed downwards from the bottom of each first electrode; each second electrode corresponds to a through silicon via, and a third contact hole opposite to the through silicon via is formed downwards from the bottom of each second electrode.
The method for forming the first electrode, the second contact hole, and the third contact hole in this step is substantially the same as the method for forming the first electrode, the second contact hole, and the third contact hole in step S14 of the first embodiment, and thus, the description thereof is omitted.
S26, grinding the back surface of the wafer to expose the through silicon via;
this step is the same as step S15 in the first embodiment, and is not described again here.
S27, depositing a passivation layer on the back of the wafer;
and S28, etching the passivation layer to form a passivation layer window of the through silicon via, and forming a redistribution layer and a first micro-bump lower metal or a first micro-bump at the passivation layer window, or forming the first micro-bump lower metal or the first micro-bump at the passivation layer window.
This step is the same as step S17 in the first embodiment, and is not described again here.
Based on the above embodiments, the first micro-bump under-metal is Cu/Ni/Au, and the first micro-bump is Cu/Ni/SnAg.
In summary, the surface electrode ion trap is integrated with the silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector, the silicon grating and/or the silicon nitride grating and the silicon through hole, and after the surface electrode ion trap is electrified, ions are trapped and confined within a certain range. The laser source is coupled to the waveguide of the silicon grating and/or the silicon nitride grating by using any one of coupling modes such as end face coupling and the like or a mode of integrating the laser source on the chip, and the laser is emitted to ions through the silicon grating and/or the silicon nitride grating in three directions to complete addressing. After the ions are excited by light, energy level transition can occur, after the energy level transition, the ions can radiate fluorescence, and the fluorescence is detected by a silicon single photon avalanche detector or a silicon germanium single photon avalanche detector, so that the detection of quantum bit information is finally completed. Compared with the traditional addressing and detection of the free space domain, the method simplifies the light path debugging system, reduces the requirements of planning and debugging light paths on space, reduces the size of an integrated chip and improves the integration degree. Moreover, when the addressing and detecting mode of the free space is adopted, the light path of the optical fiber is easy to generate unstable phenomenon due to the interference of external factors such as vibration, and the like. In addition, the invention can integrate the silicon single photon avalanche detector, the silicon through hole and the grating number which can meet the addressing and detection of the corresponding number of ions by adopting the same integration method according to the number of the ions to be captured, and has better universality and expandability.
The invention also provides an integration method of the architecture, which comprises the following steps:
s30, bonding a redistribution layer and a micro-bump or a metal under the micro-bump of the integrated structure prepared by the integration method of the surface electrode ion trap and the silicon optical addressing and detector with a silicon adapter plate, or bonding the first micro-bump or the metal under the first micro-bump of the integrated structure with the silicon adapter plate;
s31, the silicon adapter plate is communicated with the packaging substrate through a second micro-bump or a second metal under the second micro-bump arranged on the back surface of the silicon adapter plate, or is communicated with the packaging substrate through a lead;
or, the redistribution layer of the integrated structure and the first micro-bump or the first metal under the micro-bump are directly communicated with the packaging substrate.
Based on the above embodiments, the second micro-bump under-metal is Cu/Ni/Au, and the second micro-bump is Cu/Ni/SnAg.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (28)
1. The integration method of the surface electrode ion trap and the silicon optical addressing and detector is characterized by comprising the following steps of:
providing a wafer, photoetching and etching the top layer of the wafer to form a silicon grating and a silicon structure, and carrying out ion implantation and annealing on the silicon structure;
depositing a first medium layer, etching the first medium layer above the silicon structure to form an epitaxial window, and performing epitaxial growth on silicon or germanium from the top layer of the silicon structure through the epitaxial window to form a silicon single photon avalanche detector or a silicon germanium single photon avalanche detector after ion implantation and annealing;
depositing a second medium layer, etching, chemically and mechanically polishing, and forming a first contact hole of a surface incidence type silicon single photon avalanche detector or a silicon germanium single photon avalanche detector downwards from the top layer of the second medium layer;
depositing a third dielectric layer, and forming a plurality of through silicon vias downwards from the top layer of the third dielectric layer;
depositing a fourth dielectric layer, and forming an electrode on the top layer of the fourth dielectric layer, wherein the electrode comprises a first electrode corresponding to the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector and a second electrode of the surface electrode ion trap; each first electrode corresponds to the first contact hole and the silicon through hole, and a second contact hole and a third contact hole which are connected with the first contact hole and the silicon through hole are respectively formed downwards from the bottom of each first electrode; each second electrode corresponds to the through silicon via, and a third contact hole connected with the through silicon via is formed downwards from the bottom of each second electrode;
grinding the back surface of the wafer to expose the through silicon via;
depositing a passivation layer on the back side of the wafer;
etching the passivation layer to form a passivation layer window of the through silicon via, and forming a rewiring layer and a first micro-bump lower metal or a first micro-bump at the passivation layer window; or forming the first micro-bump under metal or the first micro-bump at the passivation layer window.
2. The method of claim 1, wherein the step of forming a first contact hole down from the top layer of the second dielectric layer comprises:
etching downwards from the top layer of the second dielectric layer to form a first hole;
depositing a first isolation layer on the side wall and the bottom of the first hole;
electrochemically plating or depositing a first metal in the first hole;
and chemically and mechanically polishing or etching to remove the first metal and the first isolating layer on the surface of the second dielectric layer.
3. The method of claim 2, wherein the first metal is copper, the first hole is filled with copper by an electrochemical plating process and annealed and chemically mechanically polished;
and depositing a first stop layer after the first contact hole is formed and before the third dielectric layer is deposited.
4. The method of claim 3, wherein the step of forming a through-silicon-via down from the top layer of the third dielectric layer comprises:
etching downwards from the top layer of the third dielectric layer to form a second hole;
depositing a second isolation layer on the side wall and the bottom of the second hole;
electrochemically plating a second metal in the second hole;
and chemically and mechanically polishing to remove the second metal and the second isolating layer on the surface of the third dielectric layer.
5. The method of claim 4, wherein the second metal is copper, the second hole is filled with copper by an electrochemical plating process and annealed and chemically mechanically polished;
and depositing a second stop layer after the silicon through hole is formed and before the fourth dielectric layer is deposited.
6. The method of claim 5, wherein the step of forming the electrode, the second contact hole, and the third contact hole comprises:
etching the top layer of the fourth dielectric layer respectively to form a plurality of electrode grooves, and etching downwards from the bottoms of the electrode grooves respectively to form a third hole and a fourth hole;
depositing a third isolating layer on the side walls and the bottoms of the electrode grooves, the third holes and the fourth holes;
electrochemically plating or depositing a third metal in the electrode groove, the third hole and the fourth hole;
and chemically and mechanically polishing or etching to remove the third metal and the third isolating layer on the surface of the fourth dielectric layer.
7. The method of claim 6, wherein the first, second and third spacers are any one of Ta, TaN or Ta + TaN.
8. The method of claim 1, wherein the first, second, third and fourth dielectric layers are silicon dioxide dielectric layers.
9. The method of claim 5, wherein the first and second stop layers are silicon nitride.
10. The method of claim 1, wherein the first, second, third and fourth dielectric layers are formed by plasma enhanced chemical vapor deposition.
11. The method of claim 6, wherein the first, third, fourth and electrode trenches are formed by dry etching.
12. The method of claim 4, wherein the second aperture is formed by DRIE etching.
13. The method of claim 1, wherein the surface electrode ion trap is integrated with a silicon photo-addressing and detection device,
the vertical distance between the through silicon via and the adjacent surface of the silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector is not less than 1.5 times of the diameter of the through silicon via;
and the vertical distance between the central axes of two adjacent through silicon holes is not less than 3 times of the diameter of the through silicon hole.
14. The integration method of the surface electrode ion trap and the silicon optical addressing and detector is characterized by comprising the following steps of:
providing a wafer, and photoetching and etching the top layer of the wafer to form a silicon structure, or the silicon structure and a silicon grating; performing ion implantation and annealing on the silicon structure;
depositing a first dielectric layer and a silicon nitride layer in sequence, and photoetching and etching the top layer of the silicon nitride layer to form a silicon nitride grating;
depositing a second medium layer, etching the first medium layer and the second medium layer above the silicon structure to form an epitaxial window, and performing ion implantation and annealing on silicon or germanium from the top layer of the silicon structure through the epitaxial window to form a silicon single photon avalanche detector or a silicon germanium single photon avalanche detector;
depositing a third medium layer, etching, chemically and mechanically polishing, and forming a first contact hole of the surface incidence type silicon single photon avalanche detector or silicon germanium single photon avalanche detector downwards from the top layer of the third medium layer;
depositing a fourth dielectric layer; forming a plurality of through silicon vias downwards from the top layer of the fourth dielectric layer;
depositing a fifth dielectric layer; forming an electrode on the top layer of the fifth dielectric layer, wherein the electrode comprises a first electrode corresponding to the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector and a second electrode of the surface electrode ion trap; each first electrode corresponds to the first contact hole and the silicon through hole, and a second contact hole and a third contact hole which are connected with the first contact hole and the silicon through hole are respectively formed downwards from the bottom of each first electrode; each second electrode corresponds to the silicon through hole, and a third contact hole opposite to the silicon through hole is formed downwards from the bottom of each second electrode;
grinding the back surface of the wafer to expose the through silicon via;
depositing a passivation layer on the back side of the wafer;
etching the passivation layer to form a passivation layer window of the through silicon via, and forming a rewiring layer and a first micro-bump lower metal or a first micro-bump at the passivation layer window; or forming the first micro-bump under metal or the first micro-bump at the passivation layer window.
15. The method of claim 14, wherein the step of forming a first contact hole down from the top layer of the third dielectric layer comprises:
etching downwards from the top layer of the third dielectric layer to form a first hole;
depositing a first isolation layer on the side wall and the bottom of the first hole;
electrochemically plating or depositing a first metal in the first hole;
and chemically and mechanically polishing or etching to remove the first metal and the first isolating layer on the surface of the third dielectric layer.
16. The method of claim 15, wherein the first metal is copper, the first hole is filled with copper using an electrochemical plating process and annealed and chemically mechanically polished; and depositing a first stop layer after the first contact hole is formed and before the fourth dielectric layer is deposited.
17. The method of claim 16, wherein the step of forming a through-silicon-via down the top layer of the fourth dielectric layer comprises:
etching downwards from the top layer of the fourth dielectric layer to form a second hole;
depositing a second isolation layer on the side wall and the bottom of the second hole;
electrochemically plating a second metal in the second hole;
and chemically and mechanically polishing to remove the second metal and the second isolating layer on the surface of the fourth dielectric layer.
18. The method of claim 17, wherein the second metal is copper, the second hole is filled with copper by an electrochemical plating process and annealed and chemically mechanically polished; and depositing a second stop layer after the silicon through hole is formed and before the fifth dielectric layer is deposited.
19. The method of claim 18, wherein the step of forming the electrode, the second contact hole, and the third contact hole comprises:
etching the top layer of the fifth dielectric layer respectively to form a plurality of electrode grooves, and etching downwards from the bottoms of the electrode grooves respectively to form a third hole and a fourth hole;
depositing a third isolating layer on the side walls and the bottoms of the electrode grooves, the third holes and the fourth holes;
electrochemically plating or depositing a third metal in the electrode groove, the third hole and the fourth hole;
and chemically and mechanically polishing or etching to remove the third metal and the third isolating layer on the surface of the fifth dielectric layer.
20. The method of claim 19, wherein the first, second and third spacers are any one of Ta, TaN or Ta + TaN.
21. The method of claim 14, wherein the first, second, third, fourth and fifth dielectric layers are silicon dioxide dielectric layers.
22. The method of claim 18, wherein the first stop layer and the second stop layer are both silicon nitride.
23. The method of claim 14, wherein the first, second, third, fourth, and fifth dielectric layers are formed by plasma enhanced chemical vapor deposition.
24. The method of claim 19, wherein the first, third, fourth and electrode trenches are formed by dry etching.
25. The method of claim 17, wherein the second aperture is formed by DRIE etching.
26. The method of claim 14, wherein the vertical distance between the through-silicon via and the adjacent surface of the silicon single photon avalanche detector or silicon-based germanium single photon avalanche detector is not less than 1.5 times the diameter of the through-silicon via;
and the vertical distance between the central axes of two adjacent through silicon holes is not less than 3 times of the diameter of the through silicon hole.
27. A method for integrating an architecture, comprising the steps of:
bonding a redistribution layer and a first micro-bump or first micro-under-bump metal of an integrated structure prepared using the integration method of any of claims 1-13 or 14-26 to a silicon interposer, or bonding the silicon interposer using the first micro-bump or first micro-under-bump metal of the integrated structure;
the silicon adapter plate is communicated with the packaging substrate through a second micro-bump or a second metal under the second micro-bump arranged on the back surface of the silicon adapter plate, or is communicated with the packaging substrate through a lead;
or the redistribution layer of the integrated structure and the first micro-bump or the first metal under the micro-bump are directly communicated with the packaging substrate.
28. The method of claim 27, wherein the second microbump under metal is Cu/Ni/Au; the second micro bump is Cu/Ni/SnAg.
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| SG11202012334SA SG11202012334SA (en) | 2019-11-15 | 2019-11-21 | Method for manufacturing silicon optical interposer, method for manufacturing three-dimensional structure, method for integrating surface-electrode ion trap and silicon photoelectronic device, integrated structure, and three-dimensional structure |
| PCT/CN2019/119912 WO2021092991A1 (en) | 2019-11-15 | 2019-11-21 | Integrated method for silicon optical adapter plate and three-dimensional architecture and for surface electrode ion trap, silicon optical device and three-dimensional architecture, integrated structure and three-dimensional architecture |
| US17/121,396 US11810986B2 (en) | 2019-11-15 | 2020-12-14 | Method for integrating surface-electrode ion trap and silicon photoelectronic device, integrated structure, and three-dimensional structure |
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| CN113433615B (en) * | 2021-05-18 | 2022-09-16 | 中国科学院微电子研究所 | Chip |
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| CN110854235B (en) | 2022-04-29 |
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