CN110854235A - Integration method of surface electrode ion trap, silicon optical addressing and detector and framework - Google Patents
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Abstract
本发明提供表面电极离子阱与硅光寻址及探测器的集成方法,包括步骤:在晶圆上形成硅光栅和硅结构并对硅结构离子注入及退火;沉积第一介质层于硅结构的上方刻蚀外延窗口并外延硅或锗,离子注入及退火后形成硅基光电探测器;沉积第二介质层并形成第一接触孔;沉积第三介质层并形成若干硅通孔;沉积第四介质层并形成电极,包括与硅基光电探测器对应的第一电极以及表面电极离子阱的第二电极;自第一电极向下形成第二接触孔和第三接触孔;自第二电极向下形成与硅通孔相对的第三接触孔;研磨晶圆的背面使硅通孔露出;沉积并钝化层成硅通孔的钝化层窗口,并在钝化层窗口处形成重布线层和第一微凸块下金属或第一微凸块。本发明还提供架构的集成方法。
The invention provides a method for integrating surface electrode ion traps with silicon photo-addressing and detectors, comprising the steps of: forming a silicon grating and a silicon structure on a wafer, implanting and annealing the silicon structure; Etching the epitaxial window above and epitaxial silicon or germanium, ion implantation and annealing to form a silicon-based photodetector; depositing a second dielectric layer and forming a first contact hole; depositing a third dielectric layer and forming several through-silicon holes; depositing a fourth A dielectric layer is formed and electrodes are formed, including a first electrode corresponding to a silicon-based photodetector and a second electrode of the surface electrode ion trap; a second contact hole and a third contact hole are formed downward from the first electrode; A third contact hole opposite to the TSV is formed at the bottom; the backside of the wafer is ground to expose the TSV; a passivation layer is deposited and a passivation layer is formed into a passivation layer window of the TSV, and a redistribution layer is formed at the passivation layer window and the first microbump under metal or the first microbump. The present invention also provides an integrated approach to the architecture.
Description
技术领域technical field
本发明涉及离子阱量子比特的寻址与探测技术领域,特别是涉及一种表面电极离子阱与硅光寻址及探测器、及架构的集成方法。The invention relates to the technical field of addressing and detection of ion trap quantum bits, in particular to a method for integrating surface electrode ion traps, silicon photonic addressing and detectors, and structures.
背景技术Background technique
量子比特是量子计算机的基本操作单元,离子阱因为具有相干时间长、逻辑门保真度高等优势,是研究量子比特的载体之一。在衬底表面通过光刻技术形成金属电极(射频电极和直流电极)的表面电极离子阱,得益于成熟的半导体光刻技术,能够在衬底的表面形成各种形状的金属电极,同时也很方便制备很多个相同的金属电极和多个硅光器件,即能够很容易地实现离子囚禁区域数量的扩展和寻址与探测的扩展。Qubits are the basic operation units of quantum computers. Ion traps are one of the carriers for studying qubits because of their long coherence time and high fidelity of logic gates. The surface electrode ion trap of metal electrodes (RF electrodes and DC electrodes) is formed on the surface of the substrate by photolithography. Thanks to the mature semiconductor photolithography technology, various shapes of metal electrodes can be formed on the surface of the substrate. It is very convenient to prepare many identical metal electrodes and multiple silicon optical devices, that is, the expansion of the number of ion trapped regions and the expansion of addressing and detection can be easily realized.
目前,对于表面电极离子阱量子比特的寻址/探测多采用自由空间多束激光源和光电倍增管,存在寻址/探测用光路调试系统复杂、昂贵、庞大、误差大及可扩展性低等问题,一直制约着量子计算科学的研究和发展。At present, free-space multi-beam laser sources and photomultiplier tubes are mostly used for addressing/detection of surface electrode ion trap qubits. There are complex, expensive, bulky, large errors and low scalability of the optical path debugging system for addressing/detection. The problem has always restricted the research and development of quantum computing science.
发明内容SUMMARY OF THE INVENTION
针对上述问题,本发明的目的是提供一种稳定性强、小型化、通用性且可扩展性强的表面电极离子阱与硅光寻址及探测器、及架构的集成方法。In view of the above problems, the purpose of the present invention is to provide a method for integrating surface electrode ion traps, silicon photo-addressing and detectors, and structures with strong stability, miniaturization, versatility and scalability.
为了实现上述目的,本发明采用以下技术方案,表面电极离子阱与硅光寻址及探测器的集成方法,包括以下步骤:In order to achieve the above-mentioned purpose, the present invention adopts the following technical scheme, the integration method of surface electrode ion trap and silicon optical addressing and detector, comprising the following steps:
提供晶圆,在晶圆的顶层光刻、刻蚀形成硅光栅和硅结构,对硅结构进行离子注入及退火;Provide a wafer, photolithography and etching on the top layer of the wafer to form a silicon grating and a silicon structure, and perform ion implantation and annealing on the silicon structure;
沉积第一介质层,刻蚀硅结构上方的第一介质层以形成外延窗口,并通过外延窗口自硅结构的顶层外延硅或锗,离子注入及退火后形成硅单光子雪崩探测器或硅基锗单光子雪崩探测器;Depositing a first dielectric layer, etching the first dielectric layer above the silicon structure to form an epitaxial window, and epitaxial silicon or germanium from the top layer of the silicon structure through the epitaxial window, ion implantation and annealing to form a silicon single photon avalanche detector or silicon base germanium single photon avalanche detector;
沉积第二介质层并刻蚀、化学机械抛光,自第二介质层的顶层向下形成面入射型硅单光子雪崩探测器或硅基锗单光子雪崩探测器的第一接触孔;A second dielectric layer is deposited, etched and chemically mechanically polished, and a first contact hole of a surface incident type silicon single photon avalanche detector or a silicon-based germanium single photon avalanche detector is formed downward from the top layer of the second dielectric layer;
沉积第三介质层,自第三介质层的顶层向下形成若干硅通孔;depositing a third dielectric layer, and forming a plurality of through silicon vias downward from the top layer of the third dielectric layer;
沉积第四介质层,在第四介质层的顶层形成电极,电极包括与硅单光子雪崩探测器或硅基锗单光子雪崩探测器对应的第一电极,以及表面电极离子阱的第二电极;每一个第一电极均对应第一接触孔和硅通孔,且自每一个第一电极的底部分别向下形成与第一接触孔和硅通孔连接的第二接触孔和第三接触孔;每一个第二电极均对应硅通孔,且自每一个第二电极的底部向下形成与硅通孔连接的第三接触孔;A fourth dielectric layer is deposited, and an electrode is formed on the top layer of the fourth dielectric layer, and the electrode includes a first electrode corresponding to a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector, and a second electrode of the surface electrode ion trap; Each first electrode corresponds to a first contact hole and a through silicon hole, and a second contact hole and a third contact hole connected to the first contact hole and the through silicon hole are respectively formed downward from the bottom of each first electrode; Each of the second electrodes corresponds to a TSV, and a third contact hole connected to the TSV is formed downward from the bottom of each second electrode;
研磨晶圆的背面,使硅通孔露出;Grind the backside of the wafer to expose the TSVs;
在晶圆的背面沉积钝化层;deposit a passivation layer on the backside of the wafer;
刻蚀钝化层,形成硅通孔的钝化层窗口,并在钝化层窗口处形成重布线层和第一微凸块下金属或第一微凸块;或在钝化层窗口处形成第一微凸块下金属或第一微凸块。Etching the passivation layer, forming a passivation layer window of the TSV, and forming a redistribution layer and a first micro-bump metal or a first micro-bump at the passivation layer window; or forming a passivation layer window The first microbump under metal or the first microbump.
优选地,自第二介质层的顶层向下形成第一接触孔的步骤包括:Preferably, the step of forming the first contact hole downward from the top layer of the second dielectric layer includes:
自第二介质层的顶层向下刻蚀以形成第一孔;Etching down from the top layer of the second dielectric layer to form a first hole;
在第一孔的侧壁和底部沉积第一隔离层;depositing a first isolation layer on the sidewall and bottom of the first hole;
在第一孔内电化学镀膜或沉积第一金属;Electrochemically coating or depositing a first metal in the first hole;
化学机械抛光或刻蚀,以去除第二介质层表面的第一金属和第一隔离层。chemical mechanical polishing or etching to remove the first metal and the first isolation layer on the surface of the second dielectric layer.
优选地,第一金属为铜,在第一孔内采用电化学镀膜工艺填充铜且退火及化学机械抛光;Preferably, the first metal is copper, and the first hole is filled with copper by an electrochemical coating process, followed by annealing and chemical mechanical polishing;
形成第一接触孔后且沉积第三介质层前,沉积第一停止层。After forming the first contact hole and before depositing the third dielectric layer, a first stop layer is deposited.
优选地,自第三介质层的顶层向下形成硅通孔的步骤包括:Preferably, the step of forming through silicon vias downward from the top layer of the third dielectric layer includes:
自第三介质层的顶层向下刻蚀以形成第二孔;Etching down from the top layer of the third dielectric layer to form a second hole;
在第二孔的侧壁和底部沉积第二隔离层;depositing a second isolation layer on the sidewall and bottom of the second hole;
在第二孔内电化学镀膜第二金属;Electrochemically coating a second metal in the second hole;
化学机械抛光,以去除第三介质层表面的第二金属和第二隔离层。chemical mechanical polishing to remove the second metal and the second isolation layer on the surface of the third dielectric layer.
优选地,第二金属为铜,在第二孔内采用电化学镀膜工艺填充铜且退火及化学机械抛光;Preferably, the second metal is copper, and the second hole is filled with copper by an electrochemical coating process, followed by annealing and chemical mechanical polishing;
形成硅通孔后且沉积第四介质层前,沉积第二停止层。After the TSV is formed and before the fourth dielectric layer is deposited, a second stop layer is deposited.
优选地,形成电极、第二接触孔和第三接触孔的步骤包括:Preferably, the step of forming the electrode, the second contact hole and the third contact hole includes:
在第四介质层的顶层分别刻蚀形成若干电极槽,并自电极槽的槽底分别向下刻蚀以形成第三孔和第四孔;A plurality of electrode grooves are formed by etching on the top layer of the fourth dielectric layer, respectively, and are etched downward from the groove bottom of the electrode groove to form a third hole and a fourth hole;
在电极槽、第三孔和第四孔的侧壁和底部均沉积第三隔离层;depositing a third isolation layer on the sidewall and bottom of the electrode groove, the third hole and the fourth hole;
在电极槽、第三孔和第四孔内电化学镀膜或沉积第三金属;Electrochemically coating or depositing a third metal in the electrode tank, the third hole and the fourth hole;
化学机械抛光或刻蚀,以去除第四介质层表面的第三金属和第三隔离层。chemical mechanical polishing or etching to remove the third metal and the third isolation layer on the surface of the fourth dielectric layer.
优选地,第一隔离层、第二隔离层、第三隔离层均为Ta、TaN或Ta+TaN中的任意一种。Preferably, the first isolation layer, the second isolation layer and the third isolation layer are any one of Ta, TaN or Ta+TaN.
优选地,第一介质层、第二介质层、第三介质层和第四介质层均为二氧化硅介质层。Preferably, the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are all silicon dioxide dielectric layers.
优选地,第一停止层和第二停止层均为氮化硅。Preferably, both the first stop layer and the second stop layer are silicon nitride.
优选地,采用等离子增强化学的气相沉积法形成第一介质层、第二介质层、第三介质层和第四介质层。Preferably, the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are formed by a plasma-enhanced chemical vapor deposition method.
优选地,采用干法刻蚀形成第一孔、第三孔、第四孔和电极槽。Preferably, the first hole, the third hole, the fourth hole and the electrode groove are formed by dry etching.
优选地,采用DRIE刻蚀形成第二孔。Preferably, the second hole is formed using DRIE etching.
优选地,硅通孔与硅单光子雪崩探测器或硅基锗单光子雪崩探测器的相邻面的垂直距离不小于硅通孔直径的1.5倍;Preferably, the vertical distance between the TSV and the adjacent surface of the silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector is not less than 1.5 times the diameter of the TSV;
且相邻两硅通孔的中心轴线之间的垂直距离不小于硅通孔直径的3倍。And the vertical distance between the central axes of two adjacent TSVs is not less than 3 times the diameter of the TSVs.
本发明还提供另外一种表面电极离子阱与硅光寻址及探测器的集成方法,包括以下步骤:The present invention also provides another method for integrating surface electrode ion traps with silicon photo-addressing and detectors, comprising the following steps:
提供晶圆,在晶圆的顶层光刻、刻蚀形成硅结构,或,硅结构和硅光栅;对硅结构进行离子注入及退火;Provide a wafer, and photolithography and etching the top layer of the wafer to form a silicon structure, or a silicon structure and a silicon grating; perform ion implantation and annealing on the silicon structure;
依次沉积第一介质层和氮化硅层,并在氮化硅层的顶层光刻、刻蚀形成氮化硅光栅;depositing a first dielectric layer and a silicon nitride layer in sequence, and photolithography and etching on the top layer of the silicon nitride layer to form a silicon nitride grating;
沉积第二介质层,刻蚀硅结构上方的第一介质层和第二介质层以形成外延窗口,并通过外延窗口自硅结构的顶层外延硅或锗,离子注入及退火后形成硅单光子雪崩探测器或硅基锗单光子雪崩探测器;depositing a second dielectric layer, etching the first dielectric layer and the second dielectric layer above the silicon structure to form an epitaxial window, and epitaxial silicon or germanium from the top layer of the silicon structure through the epitaxial window, ion implantation and annealing to form a silicon single photon avalanche detectors or silicon-based germanium single-photon avalanche detectors;
沉积第三介质层并刻蚀、化学机械抛光,自第三介质层的顶层向下形成面入射型硅单光子雪崩探测器或硅基锗单光子雪崩探测器的第一接触孔;A third dielectric layer is deposited, etched and chemically mechanically polished, and a first contact hole of a surface incident type silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector is formed downward from the top layer of the third dielectric layer;
沉积第四介质层;自第四介质层的顶层向下形成若干硅通孔;depositing a fourth dielectric layer; forming a plurality of through silicon vias downward from the top layer of the fourth dielectric layer;
沉积第五介质层;在第五介质层的顶层形成电极,电极包括与硅单光子雪崩探测器或硅基锗单光子雪崩探测器对应的第一电极,以及表面电极离子阱的第二电极;每一个第一电极均对应第一接触孔和硅通孔,且自每一个第一电极的底部分别向下形成与第一接触孔和硅通孔连接的第二接触孔和第三接触孔;每一个第二电极均对应硅通孔,且自每一个第二电极的底部分别向下形成与硅通孔相对的第三接触孔;depositing a fifth dielectric layer; forming electrodes on the top layer of the fifth dielectric layer, the electrodes comprising a first electrode corresponding to a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector, and a second electrode of the surface electrode ion trap; Each first electrode corresponds to a first contact hole and a through silicon hole, and a second contact hole and a third contact hole connected to the first contact hole and the through silicon hole are respectively formed downward from the bottom of each first electrode; Each of the second electrodes corresponds to a TSV, and a third contact hole opposite to the TSV is respectively formed downward from the bottom of each second electrode;
研磨晶圆的背面,使硅通孔露出;Grind the backside of the wafer to expose the TSVs;
在晶圆的背面沉积钝化层;deposit a passivation layer on the backside of the wafer;
刻蚀钝化层,形成硅通孔的钝化层窗口,并在钝化层窗口处形成重布线层和第一微凸块下金属或第一微凸块;或在钝化层窗口处形成第一微凸块下金属或第一微凸块。Etching the passivation layer, forming a passivation layer window of the TSV, and forming a redistribution layer and a first micro-bump metal or a first micro-bump at the passivation layer window; or forming a passivation layer window The first microbump under metal or the first microbump.
本发明还提供一种架构的集成方法,包括以下步骤:The present invention also provides a method for integrating the architecture, comprising the following steps:
将利用本发明涉及的集成方法制备的集成结构的重布线层和第一微凸块或第一微凸块下金属键合硅转接板,或者利用集成结构的第一微凸块或第一微凸块下金属键合硅转接板;The redistribution layer of the integrated structure and the first micro-bump or the metal under the first micro-bump prepared by the integration method of the present invention are bonded to the silicon interposer, or the first micro-bump or the first micro-bump of the integrated structure is used. Metal-bonded silicon interposer under micro-bumps;
硅转接板通过设置在其背面的第二微凸块或第二微凸块下金属与封装基板连通,或通过引线与封基板连通;The silicon interposer is communicated with the packaging substrate through the second micro-bumps or the metal under the second micro-bumps disposed on the back of the silicon interposer, or communicated with the packaging substrate through leads;
或,利用集成结构的重布线层和第一微凸块或第一微凸块下金属直接与封装基板连通。Or, the redistribution layer of the integrated structure and the first micro-bump or the metal under the first micro-bump are directly communicated with the package substrate.
优选地,第二微凸块下金属为Cu/Ni/Au第二微凸块为Cu/Ni/SnAg。Preferably, the metal under the second micro-bump is Cu/Ni/Au and the second micro-bump is Cu/Ni/SnAg.
根据本发明示例性实施例,表面电极离子阱与硅单光子雪崩探测器或硅基锗单光子雪崩探测器、硅光栅和/或氮化硅光栅和硅通孔集成,通电后,利用表面电极离子阱俘获离子并将其囚禁在一定的范围内。利用端面耦合等任意一种耦合方式将激光源耦合至硅光栅和/或氮化硅光栅上,激光经三个方位的硅光栅和/或氮化硅光栅出射至离子上,以完成寻址。离子受光激发后能够发生能级跃迁,能级跃迁后,离子会辐射出荧光,荧光被硅单光子雪崩探测器或硅基锗单光子雪崩探测器探测到,最终完成量子比特信息的探测。相对于传统的自由空间域的寻址和探测,简化了光路调试系统,而且降低了规划、调试光路对空间的要求,降低了集成芯片的尺寸,提高了集成化程度。再者,采用自由空间的寻址和探测方式时,其光路容易因震动等外界因素的干扰而产生不稳定的现象,本发明能够避免上述不稳定现象的发生。除此,本发明可以根据需要俘获的离子数量,采用相同的集成方法,集成能够满足对应数量离子寻址和探测的硅单光子雪崩探测器或硅基锗单光子雪崩探测器、硅通孔和硅光栅和/或氮化硅光栅数量,具有较好的通用性和可扩展性。According to an exemplary embodiment of the present invention, the surface electrode ion trap is integrated with a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector, a silicon grating and/or a silicon nitride grating and a through silicon via, and after power-on, the surface electrode is used An ion trap traps ions and traps them within a certain range. The laser source is coupled to the silicon grating and/or silicon nitride grating by any coupling method such as end-face coupling, and the laser is emitted to the ions through the silicon grating and/or silicon nitride grating in three directions to complete the addressing. After the ion is excited by light, an energy level transition can occur. After the energy level transition, the ion radiates fluorescence, and the fluorescence is detected by a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector, and finally the detection of qubit information is completed. Compared with the traditional addressing and detection in the free space domain, the optical path debugging system is simplified, the space requirements for planning and debugging the optical path are reduced, the size of the integrated chip is reduced, and the integration degree is improved. Furthermore, when the addressing and detection methods of free space are adopted, the optical path of the optical path is easily disturbed by external factors such as vibrations, resulting in an unstable phenomenon, and the present invention can avoid the occurrence of the above-mentioned unstable phenomenon. In addition, the present invention can integrate silicon single photon avalanche detectors or silicon-based germanium single photon avalanche detectors, through-silicon vias and The number of silicon gratings and/or silicon nitride gratings has good versatility and scalability.
附图说明Description of drawings
图1是本发明提供的一个实施例的表面电极离子阱与硅光寻址及探测器的集成方法的流程图;1 is a flowchart of a method for integrating a surface electrode ion trap with a silicon photoaddressing and detector according to an embodiment of the present invention;
图2是本发明提供的另一个实施例的表面电极离子阱与硅光寻址及探测器的集成方法的流程图;2 is a flow chart of a method for integrating surface electrode ion traps with silicon photoaddressing and detectors according to another embodiment of the present invention;
图3是本发明提供的一个实施例的架构的集成方法流程图。FIG. 3 is a flowchart of a method for integrating the architecture of an embodiment provided by the present invention.
具体实施方式Detailed ways
下面结合附图说明根据本发明的具体实施方式。Specific embodiments according to the present invention will be described below with reference to the accompanying drawings.
在下面的描述中阐述了很多具体细节以便于充分理解本发明,但是,本发明还可以采用其他不同于在此描述的其他方式来实施,因此,本发明并不限于下面公开的具体实施例的限制。Many specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can also be implemented in other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed below. limit.
为了解决现有量子比特的寻址/探测存在的光路调试复杂、稳定性弱和可扩展性低等技术问题,本发明提供一种表面电极离子阱与硅光寻址及探测器、及架构的集成方法。In order to solve the technical problems of complex optical path debugging, weak stability and low scalability in the addressing/detection of existing qubits, the present invention provides a surface electrode ion trap, a silicon optical addressing and detector, and a structure of the integrated approach.
图1示出了本发明提供的一种表面电极离子阱与硅光寻址及探测器的集成方法的一个实施例,包括以下步骤:FIG. 1 shows an embodiment of a method for integrating a surface electrode ion trap with a silicon photoaddressing and detector provided by the present invention, which includes the following steps:
S10、提供晶圆,在晶圆的顶层光刻、刻蚀形成硅光栅和硅结构,对硅光栅进行离子注入及退火;S10, providing a wafer, photolithography and etching on the top layer of the wafer to form a silicon grating and a silicon structure, and performing ion implantation and annealing on the silicon grating;
需要进一步说明的是:晶圆优选为具有高阻抗衬底的SOI(Silicon-On-Insulator,绝缘衬底上的硅)晶圆,其具有顶层硅、背衬底和介于两者之间的埋氧化层。It should be further noted that the wafer is preferably an SOI (Silicon-On-Insulator, silicon on insulating substrate) wafer with a high-resistance substrate, which has a top layer silicon, a back substrate and a silicon-on-insulator wafer in between. Buried oxide layer.
在顶层硅上利用现有任意一种光刻和刻蚀方法依次实施光刻和刻蚀,以形成硅光栅,硅光栅具有根据微纳结构的设计来决定的出射角度出射一定波长的激光的作用。Photolithography and etching are sequentially performed on the top layer silicon using any of the existing photolithography and etching methods to form a silicon grating. The silicon grating has the function of emitting a certain wavelength of laser light at an exit angle determined according to the design of the micro-nano structure. .
在形成硅光栅的过程中,在硅光栅一侧的顶层硅上一并形成硅结构,即形成硅结构的工艺以及工艺参数等与形成硅光栅的相同。In the process of forming the silicon grating, a silicon structure is formed on the top layer silicon on one side of the silicon grating, that is, the process and process parameters for forming the silicon structure are the same as those for forming the silicon grating.
硅结构形成之后采用现有任意一种方法进行离子注入及退火,注入的离子为硼和磷,以形成P型掺杂和N型掺杂。After the silicon structure is formed, any existing method is used for ion implantation and annealing, and the implanted ions are boron and phosphorus to form P-type doping and N-type doping.
S11、沉积形成第一介质层,刻蚀硅结构上方的第一介质层以形成外延窗口,并通过外延窗口自硅结构的顶层外延硅或锗,离子注入及退火后形成硅单光子雪崩光电探测器或硅基锗单光子雪崩光电探测器;S11, depositing to form a first dielectric layer, etching the first dielectric layer above the silicon structure to form an epitaxial window, and epitaxial silicon or germanium from the top layer of the silicon structure through the epitaxial window, ion implantation and annealing to form a silicon single-photon avalanche photodetector or silicon-based germanium single-photon avalanche photodetectors;
在本步骤中,在具有硅光栅和硅结构的晶圆的顶层优选等离子体增强化学的气相沉积法(PECVD)沉积形成第一介质层,第一介质层优选为二氧化硅介质层,当然,也可以是其他同样能够起到隔离作用的第一介质层。In this step, a first dielectric layer is formed on the top layer of the wafer with the silicon grating and the silicon structure, preferably by plasma-enhanced chemical vapor deposition (PECVD). The first dielectric layer is preferably a silicon dioxide dielectric layer. Of course, It can also be other first dielectric layers that can also play the role of isolation.
优选地,沉积形成第一介质层后可以进行低温退火处理及化学机械抛光(CMP)处理。Preferably, low temperature annealing treatment and chemical mechanical polishing (CMP) treatment may be performed after depositing to form the first dielectric layer.
可选地,沉积形成第一介质层后也可以不进行低温退火处理及化学机械抛光处理。Optionally, the low-temperature annealing treatment and chemical mechanical polishing treatment may not be performed after the first dielectric layer is formed by deposition.
在对应硅结构的第一介质层上通过刻蚀的方法形成外延窗口,通过外延窗口在硅结构的顶层外延硅或外延锗,即硅或锗形成在由硅结构的顶层和窗口构成的空间内,进一步地进行离子注入及退火,最终形成硅单光子雪崩探测器或硅基锗单光子雪崩探测器。注入的离子为硼和磷,以形成P型掺杂和N型掺杂。硅单光子雪崩探测器或硅基锗单光子雪崩探测器从物理层面上包括吸收层、电荷层和倍增层,作用是实现离子能级跃迁发出的荧光的探测。An epitaxial window is formed by etching on the first dielectric layer corresponding to the silicon structure, and epitaxial silicon or epitaxial germanium is formed on the top layer of the silicon structure through the epitaxial window, that is, silicon or germanium is formed in the space formed by the top layer of the silicon structure and the window. , and further ion implantation and annealing are performed to finally form a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector. The implanted ions are boron and phosphorus to form P-type doping and N-type doping. The silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector physically includes an absorption layer, a charge layer and a multiplication layer, and its function is to realize the detection of the fluorescence emitted by the ion energy level transition.
优选地,硅或锗对应的结构的截面面积较硅结构的截面面积小,且分布在硅结构的中心位置。Preferably, the cross-sectional area of the structure corresponding to silicon or germanium is smaller than that of the silicon structure, and is distributed in the center of the silicon structure.
采用刻蚀晶圆的顶层硅形成硅结构、外延硅或锗并进行离子注入及退火的方式将硅单光子雪崩探测器或硅基锗单光子雪崩探测器集成在晶圆上,具有集成度高,以及尺寸小等优点。The silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector is integrated on the wafer by etching the top silicon of the wafer to form a silicon structure, epitaxial silicon or germanium, and ion implantation and annealing, which has a high degree of integration. , and the advantages of small size.
S12、沉积第二介质层并刻蚀、化学机械抛光,自第二介质层的顶层向下形成面入射型硅单光子雪崩探测器或硅基锗单光子雪崩探测器的第一接触孔;S12, depositing a second dielectric layer, etching, chemical mechanical polishing, and forming a first contact hole of a surface incident type silicon single photon avalanche detector or a silicon-based germanium single photon avalanche detector from the top layer of the second dielectric layer downward;
本步骤中,在具有硅单光子雪崩探测器或硅基锗单光子雪崩探测器、硅光栅和第一介质层的结构的顶层,可以采用如等离子增强化学的气相沉积法沉积第二介质层,第二介质层可以是二氧化硅介质层。In this step, on the top layer of the structure having the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector, the silicon grating and the first dielectric layer, a second dielectric layer may be deposited by a vapor deposition method such as plasma enhanced chemistry, The second dielectric layer may be a silicon dioxide dielectric layer.
沉积形成第二介质层后,在第二介质层的顶层向下形成面入射型硅单光子雪崩探测器或硅基锗单光子雪崩探测器的第一接触孔。After depositing and forming the second dielectric layer, a first contact hole of the surface incident type silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector is formed downward on the top layer of the second dielectric layer.
示例地,可以采用铜工艺、钨工艺、金工艺、铝工艺或铝铜工艺中的任意一种形成第一接触孔。For example, the first contact hole may be formed by any one of a copper process, a tungsten process, a gold process, an aluminum process, or an aluminum-copper process.
下面将以单大马士革铜工艺为例,详细说明形成第一接触孔的方法,具体如下:The following will take the single damascene copper process as an example to describe the method for forming the first contact hole in detail, as follows:
可以采用现有任意一种刻蚀方法,如干法刻蚀自第二介质层的顶部向下刻蚀形成若干第一孔,第一孔的孔径在此不做具体限定,可以根据实际工艺条件选取合适值。Any existing etching method can be used, such as dry etching to etch down from the top of the second dielectric layer to form a number of first holes. The diameter of the first holes is not specifically limited here, and can be determined according to actual process conditions. Choose an appropriate value.
在第一孔的侧壁和底部沉积第一隔离层,第一隔离层可以是Ta、TaN或Ta+TaN,需要说明的是,第一隔离层是在具有第一孔的整个结构上沉积,也即在第一孔的侧壁和底部形成第一隔离层的同时,在第二介质层上也会沉积有第一隔离层。A first isolation layer is deposited on the sidewall and bottom of the first hole. The first isolation layer can be Ta, TaN or Ta+TaN. It should be noted that the first isolation layer is deposited on the entire structure with the first hole. That is, while the first isolation layer is formed on the sidewall and bottom of the first hole, the first isolation layer is also deposited on the second dielectric layer.
继续在具有第一隔离层的第一孔内沉积第一铜种子层,同样地,第一铜种子层也会沉积在第二介质层上,具体是沉积在第一隔离层上。Continue to deposit the first copper seed layer in the first hole with the first isolation layer, and similarly, the first copper seed layer is also deposited on the second dielectric layer, specifically, on the first isolation layer.
继续在具有第一隔离层和第一铜种子层的第一孔内采用电化学镀膜工艺(ECP)填充铜,同样地,铜也会被镀在第二介质层上,具体是被镀在第一铜种子层上;Continue to fill the first hole with the first isolation layer and the first copper seed layer using an electrochemical coating process (ECP). Similarly, copper will also be plated on the second dielectric layer, specifically on the first hole. a copper seed layer;
之后,采用退火及化学机械抛光的方式去除第二介质层表面上的铜、第一铜种子层和第一隔离层,最终由第一孔、以及形成在第一孔内的第一隔离层、第一铜种子层和铜形成与第二介质层的顶层面齐平的第一接触孔。After that, the copper, the first copper seed layer and the first isolation layer on the surface of the second dielectric layer are removed by means of annealing and chemical mechanical polishing, and finally the first hole, the first isolation layer formed in the first hole, The first copper seed layer and copper form a first contact hole flush with the top surface of the second dielectric layer.
第一接触孔与硅单光子雪崩探测器或硅基锗单光子雪崩探测器接触,能够将硅单光子雪崩探测器或硅基锗单光子雪崩探测器与电极连通,以使硅单光子雪崩探测器或硅基锗单光子雪崩探测器通电。The first contact hole is in contact with the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector, and the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector can be communicated with the electrode, so that the silicon single-photon avalanche detector can be detected power on the detector or silicon-based germanium single-photon avalanche detector.
采用单大马士革铜工艺形成第一接触孔后,为了避免在后续工艺中铜被氧化,因此,需要在已形成的结构的顶层沉积第一停止层,第一停止层可以是氮化硅。After the single damascene copper process is used to form the first contact hole, in order to avoid oxidation of copper in the subsequent process, a first stop layer needs to be deposited on the top layer of the formed structure, and the first stop layer may be silicon nitride.
需要进一步说明的是,如果采用铜工艺或金工艺形成第一接触孔,则需要采用电化学镀膜的方式将铜和金形成在第一孔内,针对铜工艺进行退火、化学机械抛光,而针对金工艺则进行化学机械抛光。如果采用铝工艺或铝铜工艺形成第一接触孔,则需要采用沉积的方式将铝或铝铜形成在第一孔内,而后再进行刻蚀。如果采用钨工艺,则需要采用沉积的方式将钨形成在第一孔内,而后再进行化学机械抛光。It should be further explained that if the first contact hole is formed by a copper process or a gold process, it is necessary to form copper and gold in the first hole by means of electrochemical plating, and annealing and chemical mechanical polishing are performed for the copper process. The gold process is chemical mechanical polishing. If an aluminum process or an aluminum-copper process is used to form the first contact hole, the aluminum or aluminum-copper needs to be formed in the first hole by deposition, and then etched. If the tungsten process is used, tungsten needs to be formed in the first hole by means of deposition, and then chemical mechanical polishing is performed.
S13、沉积第三介质层,自第三介质层的顶层向下形成若干硅通孔;S13, depositing a third dielectric layer, and forming a plurality of through silicon vias downward from the top layer of the third dielectric layer;
在本步骤中,在具有第一接触孔的第二介质层或第一停止层的顶层,可以采用如等离子增强化学的气相沉积法沉积第三介质层,即第三介质层将第一接触孔或第一停止层完全覆盖,第三介质层可以是二氧化硅介质层。In this step, on the top layer of the second dielectric layer with the first contact hole or the first stop layer, a third dielectric layer may be deposited by a vapor deposition method such as plasma enhanced chemistry, that is, the first contact hole is formed by the third dielectric layer. Or the first stop layer is completely covered, and the third dielectric layer may be a silicon dioxide dielectric layer.
沉积形成第三介质层后,在第三介质层的顶层向下形成若干硅通孔。After depositing and forming the third dielectric layer, several through-silicon vias are formed downward on the top layer of the third dielectric layer.
可以采用铜工艺、钨工艺或金工艺中的任意一种形成硅通孔,但通常使用铜。Through silicon vias can be formed using any of copper, tungsten, or gold processes, but copper is usually used.
下面将以单大马士革铜工艺为例,详细说明形成硅通孔的方法,具体如下:The following will take the single damascene copper process as an example to describe the method of forming through silicon vias in detail, as follows:
可以采用DRIE刻蚀形成第二孔,第二孔的孔径在此不做具体限定,可以根据实际应用需求和DRIE工艺条件选取合适值。The second hole may be formed by DRIE etching, and the diameter of the second hole is not specifically limited here, and an appropriate value may be selected according to actual application requirements and DRIE process conditions.
在第二孔的侧壁和底部沉积第二隔离层,第二隔离层可以是Ta、TaN或Ta+TaN,需要说明的是,第二隔离层是在具有第二孔的整个结构上沉积,也即在第二孔的侧壁和底部形成第二隔离层的同时,在第三介质层上也会沉积有第二隔离层;A second isolation layer is deposited on the sidewall and bottom of the second hole. The second isolation layer can be Ta, TaN or Ta+TaN. It should be noted that the second isolation layer is deposited on the entire structure with the second hole. That is, while the second isolation layer is formed on the sidewall and bottom of the second hole, the second isolation layer is also deposited on the third dielectric layer;
继续在具有第二隔离层的第二孔内沉积第二铜种子层,第二铜种子层也会沉积在第三介质层上,具体是沉积在第二隔离层上;Continue to deposit a second copper seed layer in the second hole with the second isolation layer, and the second copper seed layer is also deposited on the third dielectric layer, specifically on the second isolation layer;
继续在具有第二隔离层、第二铜种子层的第二孔内采用电化学镀膜的方式填充铜,铜也会被镀在第三介质层上,具体是被镀在第二铜种子层上;Continue to fill the second hole with the second isolation layer and the second copper seed layer by means of electrochemical plating, and copper will also be plated on the third dielectric layer, specifically on the second copper seed layer. ;
之后,采用退火及化学机械抛光的方式去除第三介质层表面上的铜、第二铜种子层和第二隔离层,最终由第二孔、以及形成在第二孔内的第二隔离层、第二铜种子层和铜形成与第三介质层的顶层面齐平的硅通孔。After that, the copper, the second copper seed layer and the second isolation layer on the surface of the third dielectric layer are removed by means of annealing and chemical mechanical polishing, and finally the second hole, the second isolation layer formed in the second hole, The second copper seed layer and copper form through silicon vias that are flush with the top surface of the third dielectric layer.
采用单大马士革铜工艺形成硅通孔后,为了避免在后续工艺中铜被氧化,因此,需要在已形成的结构的顶层沉积第二停止层,第二停止层可以是氮化硅。After the TSV is formed by the single damascene copper process, in order to avoid oxidation of copper in the subsequent process, a second stop layer needs to be deposited on the top layer of the formed structure, and the second stop layer may be silicon nitride.
硅通孔能够实现离子阱芯片中电极与下层转接板的垂直互连。TSVs enable vertical interconnections between electrodes in the ion trap chip and the underlying interposer.
硅通孔的数量为若干个,硅通孔分布在硅单光子雪崩探测器或硅基锗单光子雪崩探测器的侧面,且距离硅单光子雪崩探测器或硅基锗单光子雪崩探测器具有一定的距离。The number of through-silicon vias is several, and the through-silicon vias are distributed on the side of the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector, and have a distance from the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector. a certain distance.
示例地:硅通孔和硅单光子雪崩探测器或硅基锗单光子雪崩探测器相邻面之间的垂直距离不小于硅通孔直径的1.5倍。两个相邻硅通孔的中心轴线间的垂直距离不小于硅通孔直径的3倍。For example, the vertical distance between the through-silicon via and the adjacent surfaces of the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector is not less than 1.5 times the diameter of the through-silicon hole. The vertical distance between the central axes of two adjacent TSVs is not less than 3 times the diameter of the TSVs.
硅通孔与硅单光子雪崩探测器或硅基锗单光子雪崩探测器具有优选的距离,以及相邻硅通孔之间具有优选的距离,能够避免硅通孔处的应力集中对硅单光子雪崩探测器或硅基锗单光子雪崩探测器的不利影响,或者是硅通孔之间的相互不利影响。The through-silicon via has a preferred distance from the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector, as well as a preferred distance between adjacent through-silicon vias, which can avoid stress concentration at the through-silicon hole and affect the silicon single-photon. Adverse effects of avalanche detectors or silicon-based germanium single-photon avalanche detectors, or mutual adverse effects between TSVs.
需要进一步说明的是:如果采用铜工艺或金工艺形成硅通孔,则需要采用电化学镀膜的方式将铜和金形成在第二孔内,针对铜工艺进行退火、化学机械抛光,而针对金工艺进行化学机械抛光。如果采用钨工艺,则需要采用沉积的方式将钨形成在第二孔内,而后再进行化学机械抛光。It should be further explained that if the through-silicon via is formed by the copper process or the gold process, the copper and gold need to be formed in the second hole by electrochemical coating, and annealing and chemical mechanical polishing are performed for the copper process, while for the gold Process for chemical mechanical polishing. If the tungsten process is used, tungsten needs to be formed in the second hole by means of deposition, and then chemical mechanical polishing is performed.
S14、沉积第四介质层,在第四介质层的顶层形成电极,电极包括与硅单光子雪崩探测器或硅基锗单光子雪崩探测器对应的第一电极,以及表面电极离子阱的第二电极;每一个第一电极均对应第一接触孔和硅通孔,且自每一个第一电极的底部分别向下形成与第一接触孔、硅通孔连接的第二接触孔和第三接触孔;每一个第二电极均对应硅通孔,且自每一个第二电极的底部分别向下形成与硅通孔相对的第三接触孔。S14, depositing a fourth dielectric layer, and forming an electrode on the top layer of the fourth dielectric layer, the electrode includes a first electrode corresponding to a silicon single photon avalanche detector or a silicon-based germanium single photon avalanche detector, and a second electrode of the surface electrode ion trap electrodes; each first electrode corresponds to a first contact hole and a through silicon hole, and a second contact hole and a third contact connected to the first contact hole and the through silicon hole are respectively formed downward from the bottom of each first electrode A hole; each second electrode corresponds to a through silicon hole, and a third contact hole opposite to the through silicon hole is respectively formed downward from the bottom of each second electrode.
在本步骤中,在具有硅通孔的第三介质层或第二停止层的顶层,可以采用如等离子增强化学的气相沉积法沉积第四介质层,即第四介质层将硅通孔或第二停止层完全覆盖,第四介质层可以是二氧化硅介质层。In this step, on the top layer of the third dielectric layer or the second stop layer with the TSVs, a fourth dielectric layer may be deposited by a vapor deposition method such as plasma enhanced chemistry. The second stop layer is completely covered, and the fourth dielectric layer may be a silicon dioxide dielectric layer.
沉积形成第四介质层后,在第四介质层的顶层向下形成电极、第二接触孔和第三接触孔。After depositing and forming the fourth dielectric layer, electrodes, second contact holes and third contact holes are formed downward on the top layer of the fourth dielectric layer.
可以采用铜工艺、钨工艺、金工艺、铝工艺、铝铜工艺中的任意一种形成电极、第二接触孔和第三接触孔。The electrodes, the second contact holes, and the third contact holes may be formed using any one of a copper process, a tungsten process, a gold process, an aluminum process, and an aluminum-copper process.
下面将以双大马士革铜工艺为例,详细说明形成电极、第二接触孔和第三接触孔的方法,具体如下:The following will take the double damascene copper process as an example to describe the method of forming the electrode, the second contact hole and the third contact hole in detail, as follows:
在第四介质层均采用如干法刻蚀等现有任意一种刻蚀方法,形成电极槽,自电极槽的槽底继续向下刻蚀,形成与第一接触孔对应的第三孔和与硅通孔对应的第四孔。In the fourth dielectric layer, any existing etching methods such as dry etching are used to form electrode grooves, and continue to etch downwards from the groove bottom of the electrode grooves to form third holes corresponding to the first contact holes and A fourth hole corresponding to the TSV.
在电极槽、第三孔和第四孔的内侧和底部一次沉积第三隔离层,第三隔离层可以是Ta、TaN或Ta+TaN中的任意一种,需要说明的是,第三隔离层是在具有电极槽、第三孔和第四孔的整个结构上沉积,也即在电极槽、第三孔和第四孔的侧壁和底部形成第三隔离层的同时,在第四介质层上也会沉积有第三隔离层;A third isolation layer is deposited on the inside and bottom of the electrode groove, the third hole and the fourth hole at one time. The third isolation layer can be any one of Ta, TaN or Ta+TaN. It should be noted that the third isolation layer It is deposited on the entire structure with the electrode groove, the third hole and the fourth hole, that is, while the third isolation layer is formed on the sidewall and bottom of the electrode groove, the third hole and the fourth hole, the fourth dielectric layer is formed at the same time. There will also be a third isolation layer deposited on it;
继续在具有第三隔离层的电极槽、第三孔和第四孔内沉积第三铜种子层,第三铜种子层也会沉积在第四介质层上,具体是沉积在第三隔离层上;Continue to deposit a third copper seed layer in the electrode groove with the third isolation layer, the third hole and the fourth hole, and the third copper seed layer is also deposited on the fourth dielectric layer, specifically on the third isolation layer ;
在具有第三隔离层和第三铜种子层的第三铜种子层的电极槽、第三孔和第四孔内采用电化学镀膜的方式填充铜,铜也会被镀在第三介质层上,具体是被镀在第二铜种子层上;The electrode groove, the third hole and the fourth hole of the third copper seed layer with the third isolation layer and the third copper seed layer are filled with copper by means of electrochemical plating, and the copper will also be plated on the third dielectric layer , which is specifically plated on the second copper seed layer;
之后,采用退火及化学机械抛光的方式去除第四介质层上的铜、第三铜种子层和第三隔离层。After that, the copper, the third copper seed layer and the third isolation layer on the fourth dielectric layer are removed by means of annealing and chemical mechanical polishing.
由电极槽、第三隔离层、第三铜种子层和铜构成能够与硅单光子雪崩探测器或硅基锗单光子雪崩探测器相对的第一电极和电极离子阱的第二电极;由第三孔、第三隔离层、第三铜种子层和铜构成第二接触孔,第二接触孔能够将第一电极与第一接触孔连通,进而将第一电极与硅单光子雪崩探测器或硅基锗单光子雪崩探测器连通;由第四孔、第三隔离层、第三铜种子层和铜构成第三接触孔,第三接触孔能够将第一电极和第二电极与硅通孔连通,进而将第一电极与硅单光子雪崩探测器或硅基锗单光子雪崩探测器连通。The electrode groove, the third isolation layer, the third copper seed layer and the copper constitute the first electrode and the second electrode of the electrode ion trap which can be opposite to the silicon single photon avalanche detector or the silicon-based germanium single photon avalanche detector; The three holes, the third isolation layer, the third copper seed layer and the copper form a second contact hole, and the second contact hole can connect the first electrode with the first contact hole, thereby connecting the first electrode with the silicon single photon avalanche detector or the silicon single photon avalanche detector. The silicon-based germanium single-photon avalanche detector is connected; the third contact hole is formed by the fourth hole, the third isolation layer, the third copper seed layer and the copper, and the third contact hole can connect the first electrode and the second electrode with the through silicon hole The first electrode is connected with the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector.
在形成第一电极、第二电极、第二接触孔和第三接触孔之后实施退火和机械抛光。进一步地,采用现有任意一种钝化方法对形成的第一电极和第二电极做钝化处理。Annealing and mechanical polishing are performed after forming the first electrode, the second electrode, the second contact hole, and the third contact hole. Further, any existing passivation method is used to perform passivation treatment on the formed first electrode and the second electrode.
而且,采用双大马士革铜工艺形成第一电极和第二电极时,当第一电极和第二电极的特征尺寸大于20微米时,需要设置栅格型介质隔离结构以防止后续化学机械抛光时,造成铜表面的凹陷。Moreover, when the first electrode and the second electrode are formed by the double damascene copper process, when the feature size of the first electrode and the second electrode is larger than 20 microns, a grid-type dielectric isolation structure needs to be provided to prevent subsequent chemical mechanical polishing, resulting in Depression on the copper surface.
需要进一步说明的是:如果采用铜工艺或金工艺形成电极、第二接触孔和第三接触孔,则需要采用电化学镀膜的方式将铜和金形成在电极槽、第三孔和第四孔内,针对铜工艺进行退火、化学机械抛光,而针对金工艺则进行化学机械抛光。如果采用铝工艺或铝铜工艺形成电极、第二接触孔和第三接触孔,则需要采用沉积的方式将铝或铝铜形成在电极槽、第三孔和第四孔内,而后再进行刻蚀。如果采用钨工艺,则需要采用沉积的方式将钨形成在电极槽、第三孔和第四孔内,而后再进行化学机械抛光。It should be further explained that if the electrode, the second contact hole and the third contact hole are formed by the copper process or the gold process, it is necessary to form the copper and gold in the electrode groove, the third hole and the fourth hole by means of electrochemical plating Inside, annealing, chemical mechanical polishing is performed for copper processes, and chemical mechanical polishing is performed for gold processes. If the electrode, the second contact hole and the third contact hole are formed by the aluminum process or the aluminum-copper process, the aluminum or aluminum-copper needs to be formed in the electrode groove, the third hole and the fourth hole by deposition, and then the etching is performed. eclipse. If a tungsten process is used, tungsten needs to be deposited in the electrode groove, the third hole and the fourth hole, and then chemical mechanical polishing is performed.
S15、研磨晶圆的背面,使硅通孔露出;S15, grinding the back of the wafer to expose the TSV;
在本步骤中,可以采用热塑料材料将上述已形成的结构的正面临时键合在载片晶圆上,载片晶圆可以是体硅晶圆。In this step, a thermoplastic material can be used to temporarily bond the front side of the above-formed structure on a carrier wafer, and the carrier wafer can be a bulk silicon wafer.
采用现有任意一种研磨工艺对晶圆的背面进行研磨,以使晶圆的厚度减薄至露出硅通孔。The backside of the wafer is ground by any existing grinding process, so as to reduce the thickness of the wafer to expose the TSV.
S16、在晶圆的背面沉积钝化层;S16, depositing a passivation layer on the backside of the wafer;
S17、刻蚀钝化层,形成硅通孔的钝化层窗口,并在钝化层窗口处形成重布线层和第一微凸块下金属或第一微凸块,或在钝化层窗口处形成第一微凸块下金属或第一微凸块。S17, etch the passivation layer to form the passivation layer window of the TSV, and form the redistribution layer and the metal under the first micro-bump or the first micro-bump at the passivation layer window, or at the passivation layer window The first microbump under metal or the first microbump is formed there.
在本步骤中,优选采用电化学镀膜的方式在钝化层窗口处形成第一微凸块;In this step, the first micro-bumps are preferably formed at the passivation layer window by means of electrochemical coating;
可选地,采用电化学镀膜的方式在钝化层窗口处形成第一微凸块下金属中的任意一种。Optionally, any one of the metals under the first micro-bumps is formed at the window of the passivation layer by means of electrochemical plating.
在上述实施例的基础上,进一步地,第一微凸块下金属为Cu/Ni/Au,第一微凸块为Cu/Ni/SnAg。On the basis of the above embodiment, further, the metal under the first micro-bump is Cu/Ni/Au, and the first micro-bump is Cu/Ni/SnAg.
本发明还提供一种表面电极离子阱与硅光寻址及探测器的集成方法的第二个实施例,具体参见图2:The present invention also provides a second embodiment of a method for integrating surface electrode ion traps with silicon photo-addressing and detectors, specifically referring to FIG. 2 :
S20、提供晶圆,在晶圆的顶层光刻、刻蚀形成硅结构,或,硅结构和硅光栅;对硅结构进行离子注入及退火;S20, providing a wafer, photolithography and etching on the top layer of the wafer to form a silicon structure, or a silicon structure and a silicon grating; ion implantation and annealing of the silicon structure;
本步骤提供的晶圆的结构可以与第一实施例步骤S10中提供的晶圆的结构相同,与步骤S10不同的是,可以在晶圆的顶层采用现有任意一种光刻和刻蚀方法仅形成硅结构,而不形成硅光栅,或者,与步骤S10相同,既形成硅结构又形成硅光栅。The structure of the wafer provided in this step may be the same as that of the wafer provided in step S10 of the first embodiment, and the difference from step S10 is that any existing photolithography and etching methods may be used on the top layer of the wafer Only the silicon structure is formed without forming the silicon grating, or, as in step S10, both the silicon structure and the silicon grating are formed.
S21、依次沉积第一介质层和氮化硅层,并在氮化硅层的顶层光刻、刻蚀形成氮化硅光栅;S21, depositing a first dielectric layer and a silicon nitride layer in sequence, and photolithography and etching on the top layer of the silicon nitride layer to form a silicon nitride grating;
在本步骤中,可以采用步骤S11中提供的方法沉积形成第一介质层,在此不再赘述。In this step, the method provided in step S11 may be used to deposit and form the first dielectric layer, which will not be repeated here.
优选采用等离子体增强化学的气相沉积法(PECVD)沉积以形成氮化硅层。Plasma-enhanced chemical vapor deposition (PECVD) deposition is preferably employed to form the silicon nitride layer.
在氮化硅层的顶层利用现有任意一种光刻和刻蚀方法依次实施光刻和刻蚀,以形成氮化硅光栅,氮化硅光栅同样具有根据微纳结构的设计来决定的出射角度出射一定波长的激光的作用。On the top layer of the silicon nitride layer, any existing photolithography and etching methods are used to sequentially perform photolithography and etching to form a silicon nitride grating. The silicon nitride grating also has an output determined according to the design of the micro-nano structure. The effect of angularly emitting a certain wavelength of laser light.
S22、沉积第二介质层,刻蚀硅结构的上方的第一介质层和第二介质层以形成外延窗口,并通过外延窗口自硅结构的顶层外延硅或锗,离子注入及退火后形成硅单光子雪崩探测器或硅基锗单光子雪崩探测器;S22, depositing a second dielectric layer, etching the first dielectric layer and the second dielectric layer above the silicon structure to form an epitaxial window, and epitaxial silicon or germanium from the top layer of the silicon structure through the epitaxial window, ion implantation and annealing to form silicon Single-photon avalanche detectors or silicon-based germanium single-photon avalanche detectors;
可以采用第一实施例的步骤S11中提供的方法沉积以形成第二介质层,而且同样采用步骤S11中提供的方法形成硅单光子雪崩探测器或硅基锗单光子雪崩探测器。区别在于步骤S11中的外延窗口贯穿第一介质层,而本步骤中的窗口则需要贯穿本实施例中的第一介质层和第二介质层。The second dielectric layer can be formed by deposition using the method provided in step S11 of the first embodiment, and the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector can also be formed by using the method provided in step S11. The difference is that the epitaxial window in step S11 penetrates the first dielectric layer, while the window in this step needs to penetrate the first dielectric layer and the second dielectric layer in this embodiment.
S23、沉积第三介质层并刻蚀、化学机械抛光;自第三介质层的顶层向下形成面入射型硅单光子雪崩探测器或硅基锗单光子雪崩探测器的第一接触孔;S23, depositing a third dielectric layer, etching and chemical mechanical polishing; forming a first contact hole of a surface incident type silicon single photon avalanche detector or a silicon-based germanium single photon avalanche detector from the top layer of the third dielectric layer downward;
本步骤中形成第一接触孔的方法与第一实施例的步骤S12中形成第一接触孔的方法基本相同,在此不再赘述。The method for forming the first contact hole in this step is basically the same as the method for forming the first contact hole in step S12 of the first embodiment, and details are not repeated here.
S24、沉积第四介质层;自第四介质层的顶层向下形成若干硅通孔;S24, depositing a fourth dielectric layer; forming a plurality of through silicon vias downward from the top layer of the fourth dielectric layer;
本步骤中形成硅通孔的方法与第一实施例的步骤S13中形成硅通孔的方法基本相同,在此不再赘述。The method for forming the TSV in this step is basically the same as the method for forming the TSV in step S13 of the first embodiment, and details are not repeated here.
S25、沉积第五介质层,在第五介质层的顶层形成电极,电极包括与硅单光子雪崩探测器或硅基锗单光子雪崩探测器对应的第一电极,以及表面电极离子阱的第二电极;每一个第一电极均对应第一接触孔和硅通孔,且自每一个第一电极的底部分别向下形成与第一接触孔、硅通孔连通的第二接触孔和第三接触孔;每一个第二电极均对应硅通孔,且自每一个述第二电极的底部向下形成与硅通孔相对的第三接触孔。S25, depositing a fifth dielectric layer, and forming an electrode on the top layer of the fifth dielectric layer. The electrode includes a first electrode corresponding to the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector, and a second electrode of the surface electrode ion trap. Electrodes; each first electrode corresponds to a first contact hole and a through silicon hole, and a second contact hole and a third contact that communicate with the first contact hole and the through silicon hole are respectively formed downward from the bottom of each first electrode A hole; each second electrode corresponds to a through silicon hole, and a third contact hole opposite to the through silicon hole is formed downward from the bottom of each of the second electrodes.
本步骤中形成第一电极、第二电极、第二接触孔和第三接触孔的方法与第一个实施例的步骤S14中形成第一电极、第二电极、第二接触孔和第三接触孔的方法基本相同,在此不再赘述。The method of forming the first electrode, the second electrode, the second contact hole and the third contact hole in this step is the same as the method of forming the first electrode, the second electrode, the second contact hole and the third contact in step S14 of the first embodiment The method of the hole is basically the same and will not be repeated here.
S26、研磨晶圆的背面,使硅通孔露出;S26, grinding the back of the wafer to expose the TSV;
在本步骤与第一个实施例中的步骤S15相同,在此不再赘述。This step is the same as step S15 in the first embodiment, and is not repeated here.
S27、在晶圆的背面沉积钝化层;S27, depositing a passivation layer on the backside of the wafer;
S28、刻蚀钝化层,形成硅通孔的钝化层窗口,并在钝化层窗口处形成重布线层和第一微凸块下金属或第一微凸块,或在钝化层窗口处形成第一微凸块下金属或第一微凸块。S28, etch the passivation layer to form the passivation layer window of the through silicon via, and form the redistribution layer and the metal under the first micro-bump or the first micro-bump at the passivation layer window, or form the passivation layer window The first microbump under metal or the first microbump is formed there.
在本步骤与第一个实施例中的步骤S17相同,在此不再赘述。This step is the same as step S17 in the first embodiment, and will not be repeated here.
在上述实施例的基础上,进一步地,第一微凸块下金属为Cu/Ni/Au,第一微凸块为Cu/Ni/SnAg。On the basis of the above embodiment, further, the metal under the first micro-bump is Cu/Ni/Au, and the first micro-bump is Cu/Ni/SnAg.
综上所述,本发明将表面电极离子阱与硅单光子雪崩探测器或硅基锗单光子雪崩探测器、硅光栅和/或氮化硅光栅和硅通孔集成,通电后,利用表面电极离子阱俘获离子并将其囚禁在一定的范围内。利用端面耦合等任意一种耦合方式,或片上集成激光源的方式将激光源耦合至硅光栅和/或氮化硅光栅的波导上,激光经三个方位的硅光栅和/或氮化硅光栅出射至离子上,以完成寻址。离子受光激发后能够发生能级跃迁,能级跃迁后,离子会辐射出荧光,荧光被硅单光子雪崩探测器或硅基锗单光子雪崩探测器探测到,最终完成量子比特信息的探测。相对于传统的自由空间域的寻址和探测,简化了光路调试系统,而且降低了规划、调试光路对空间的要求,降低了集成芯片的尺寸,提高了集成化程度。再者,采用自由空间的寻址和探测方式时,其光路容易因震动等外界因素的干扰而产生不稳定的现象,本发明能够避免上述不稳定现象的发生。除此,本发明可以根据需要俘获的离子数量,采用相同的集成方法,集成能够满足对应数量离子寻址和探测的硅单光子雪崩探测器、硅通孔和光栅数量,具有较好的通用性和可扩展性。To sum up, the present invention integrates surface electrode ion traps with silicon single-photon avalanche detectors or silicon-based germanium single-photon avalanche detectors, silicon gratings and/or silicon nitride gratings and through-silicon vias. An ion trap traps ions and traps them within a certain range. The laser source is coupled to the waveguide of the silicon grating and/or silicon nitride grating by any coupling method such as end-face coupling, or the method of integrating the laser source on-chip, and the laser passes through the silicon grating and/or silicon nitride grating in three directions. out onto the ions to complete the addressing. After the ion is excited by light, an energy level transition can occur. After the energy level transition, the ion radiates fluorescence, and the fluorescence is detected by a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector, and finally the detection of qubit information is completed. Compared with the traditional addressing and detection in the free space domain, the optical path debugging system is simplified, the space requirements for planning and debugging the optical path are reduced, the size of the integrated chip is reduced, and the integration degree is improved. Furthermore, when the addressing and detection methods of free space are adopted, the optical path of the optical path is easily disturbed by external factors such as vibrations, resulting in an unstable phenomenon, and the present invention can avoid the occurrence of the above-mentioned unstable phenomenon. In addition, the present invention can use the same integration method to integrate the number of silicon single-photon avalanche detectors, through-silicon holes and gratings that can satisfy the addressing and detection of the corresponding number of ions according to the number of ions to be captured, and has good versatility. and scalability.
本发明还提供一种架构的集成方法,包括以下步骤:The present invention also provides a method for integrating the architecture, comprising the following steps:
S30、将利用表面电极离子阱与硅光寻址及探测器的集成方法制备的集成结构的重布线层和微凸块或微凸块下金属键合硅转接板,或者利用集成结构的第一微凸块或第一微凸块下金属键合硅转接板;S30. The redistribution layer of the integrated structure prepared by the integration method of the surface electrode ion trap and the silicon photo-addressing and detector and the micro-bump or the metal under the micro-bump are bonded to the silicon interposer, or the first integrated structure is used. A micro-bump or a metal-bonded silicon interposer under the first micro-bump;
S31、硅转接板通过设置在其背面的第二微凸块或第二微凸块下金属与封装基板连通,或通过引线与封基板连通;S31, the silicon interposer is communicated with the packaging substrate through the second micro-bumps or the metal under the second micro-bumps disposed on the back of the silicon interposer, or communicated with the packaging substrate through leads;
或,利用集成结构的重布线层和第一微凸块或第一微凸块下金属直接与封装基板连通。Or, the redistribution layer of the integrated structure and the first micro-bump or the metal under the first micro-bump are directly communicated with the package substrate.
在上述实施例的基础上,进一步地,第二微凸块下金属为Cu/Ni/Au,第二微凸块为Cu/Ni/SnAg。On the basis of the above embodiment, further, the metal under the second micro-bump is Cu/Ni/Au, and the second micro-bump is Cu/Ni/SnAg.
以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
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