CN110854025A - Silicon optical adapter plate and integration method of three-dimensional framework - Google Patents
Silicon optical adapter plate and integration method of three-dimensional framework Download PDFInfo
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Abstract
The invention provides an integration method of a silicon optical adapter plate, which comprises the following steps: completing waveguide etching, epitaxy, ion implantation and thermode preparation of a silicon optical device on a wafer; depositing a first dielectric layer on the top layer of the silicon optical device and carrying out chemical mechanical polishing to form a first contact hole of the thermo-optical device and/or the silicon optical active device; depositing a second medium layer to form a silicon through hole; depositing a third dielectric layer to form an electrode corresponding to the thermo-optic device and/or the silicon photo-active device; the electrode corresponds to the first contact hole and the silicon through hole, and a second contact hole and a third contact hole are formed downwards from the bottom of the electrode; chemically and mechanically polishing and depositing a fourth medium layer, wherein the fourth medium layer is provided with a bonding pad window and forms a first micro-bump lower metal or a first micro-bump; exposing the silicon through hole and depositing a passivation layer; and etching the passivation layer to form a passivation layer window of the silicon through hole, and forming a rewiring layer and a second micro-bump lower metal or a second micro-bump. The invention also provides an integration method of the three-dimensional architecture.
Description
Technical Field
The invention relates to the technical field of silicon-based photoelectricity, in particular to a silicon optical adapter plate and a three-dimensional framework integration method.
Background
The Silicon-based photoelectric technology is one of effective means for realizing the 'beyond mole', and the Silicon optical adapter plate integrates a Silicon optical device and a Through Silicon Via (TSV) single chip together and realizes interconnection and intercommunication of electric signals between upper and lower chips Through the TSV. The integration method of the photoelectric three-dimensional architecture based on the silicon optical adapter plate technology can enable the chip packaging area to be smaller and the integration level to be higher, and compared with the traditional plane architecture or the three-dimensional architecture integrated in a lead bonding mode, the formed three-dimensional architecture has the advantages of smaller electric signal delay, higher bandwidth and higher speed.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a silicon optical interposer and a three-dimensional structure integration method, which can achieve smaller chip package area, higher integration level, smaller electrical signal delay, and higher bandwidth and speed.
In order to achieve the above object, the present invention adopts the following technical solution, and an integration method of a silicon optical adapter plate includes the following steps:
providing a wafer, and completing waveguide etching, epitaxy, ion implantation and thermode preparation of a silicon optical device on the wafer, wherein the silicon optical device comprises a silicon optical passive device and a silicon optical active device;
depositing a first dielectric layer on the top layer of the silicon optical device and carrying out chemical mechanical polishing, and forming a first contact hole of a thermo-optical device and/or a silicon optical active device in the silicon optical passive device downwards from the top layer of the first dielectric layer;
depositing a second dielectric layer, and forming a plurality of through silicon vias downwards from the top layer of the second dielectric layer;
depositing a third dielectric layer, and forming an electrode corresponding to the thermo-optic device and/or the silicon photo-active device on the top layer of the third dielectric layer; each electrode corresponds to the first contact hole and the silicon through hole, and a second contact hole and a third contact hole which are connected with the first contact hole and the silicon through hole are respectively formed downwards from the bottom of each electrode;
chemically and mechanically polishing the top layer of the formed structure, depositing a fourth medium layer, forming a bonding pad window through the fourth medium layer, and forming a first micro-bump lower metal or a first micro-bump, wherein the bonding pad window is positioned above the electrode;
grinding the back surface of the wafer to expose the through silicon via;
depositing a passivation layer on the back of the wafer;
etching the passivation layer to form a passivation layer window of the through silicon via, and forming a rewiring layer and a second micro bump lower metal or a second micro bump at the passivation layer window; or forming a second micro-bump under metal or a second micro-bump at the passivation layer window.
Preferably, the step of forming the first contact hole downward from the top layer of the first dielectric layer comprises:
etching downwards from the top layer of the first dielectric layer to form a first hole;
depositing a first isolation layer on the side wall and the bottom of the first hole;
electrochemically plating or depositing a first metal in the first hole;
and chemically and mechanically polishing or etching to remove the first metal and the first isolating layer on the surface of the first dielectric layer.
Preferably, the first metal is copper, the first hole is filled with copper by adopting an electrochemical plating process, and annealing and chemical mechanical polishing treatment are carried out;
and depositing a first stop layer after the first contact hole is formed and before the second dielectric layer is deposited.
Preferably, the step of forming the through-silicon-via downward from the top layer of the second dielectric layer comprises:
etching downwards from the top layer of the second dielectric layer to form a second hole;
depositing a second isolation layer on the side wall and the bottom of the second hole;
electrochemically plating a second metal in the second hole;
and chemically and mechanically polishing to remove the second metal and the second isolating layer on the surface of the second dielectric layer.
Preferably, the second metal is copper, and the second hole is filled with copper by adopting an electrochemical plating process and is subjected to annealing and chemical mechanical polishing treatment;
and depositing a second stop layer after the silicon through hole is formed and before the third dielectric layer is deposited.
Preferably, the step of forming the electrode, the second contact hole and the third contact hole includes:
etching the top layer of the third dielectric layer respectively to form a plurality of electrode grooves, and etching downwards from the bottoms of the electrode grooves respectively to form a third hole and a fourth hole;
depositing a third isolating layer on the side walls and the bottoms of the electrode grooves, the third holes and the fourth holes;
electrochemically plating or depositing a third metal in the electrode groove, the third hole and the fourth hole;
and chemically and mechanically polishing or etching to remove the third metal and the third isolating layer on the surface of the third dielectric layer.
Preferably, the third metal is copper, and the electrode groove, the third hole and the fourth hole are filled with copper by adopting an electrochemical plating process and are subjected to annealing and chemical mechanical polishing treatment;
and depositing a third stop layer after the electrode, the second contact hole and the third contact hole are formed and before the fourth dielectric layer is deposited.
Preferably, the first isolation layer, the second isolation layer and the third isolation layer are all any one of Ta, TaN or Ta + TaN.
Preferably, the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are silicon dioxide dielectric layers.
Preferably, the first stop layer, the second stop layer and the third stop layer are all silicon nitride.
Preferably, the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are formed by a plasma enhanced chemical vapor deposition method.
Preferably, the first hole, the third hole, the fourth hole, and the electrode groove are formed using dry etching.
Preferably, the second hole is formed using DRIE etching.
Preferably, the vertical distance between the through silicon via and the adjacent surface of the thermo-optic device and/or the silicon photo-active device is not less than 1.5 times the diameter of the through silicon via;
and the vertical distance between the central axes of two adjacent through silicon vias is not less than 3 times of the diameter of the through silicon via.
Preferably, the first micro-bump is made of metal Cu/Ni/Au, and the first micro-bump is made of Cu/Ni/SnAg; and the metal under the second micro-bump is Cu/Ni/Au, and the second micro-bump is Cu/Ni/SnAg.
The invention also provides an integration method of the three-dimensional architecture, which comprises the following steps:
providing a silicon optical adapter plate prepared by the integration method related by the invention;
bonding an electronic chip or an optoelectronic chip by using a first micro-bump underbump metal or a first micro-bump of the silicon optical adapter plate;
bonding the silicon adapter plate by utilizing the redistribution layer of the silicon optical adapter plate and the second micro-bump lower metal or the second micro-bump, or the second micro-bump lower metal or the second micro-bump of the silicon optical adapter plate;
the silicon adapter plate is communicated with the packaging substrate through a third micro-bump lower metal or a third micro-bump arranged on the back surface of the silicon adapter plate;
or the redistribution layer of the silicon optical adapter plate and the second micro-bump under metal or the second micro-bump, or the second micro-bump under metal or the second micro-bump of the silicon optical adapter plate are directly communicated with the packaging substrate.
Preferably, the third micro-bump under-metal is Cu/Ni/Au, the third micro-bump is Cu/Ni/SnAg.
The silicon optical device and the silicon through hole are monolithically integrated to form a silicon optical adapter plate, the front side of the silicon optical adapter plate can form a first micro bump or a first micro bump under metal (UBM) which can be integrated with an electronic chip or an optoelectronic chip on a bonding pad window through an electrochemical coating process, the back side of the silicon optical adapter plate can form a second micro bump or a second micro bump under metal on a passivation layer window through the electrochemical coating process so as to be communicated with the silicon adapter plate, further, the silicon adapter plate can be integrated with a packaging substrate through a third micro bump or a third micro bump under metal positioned on the back side of the silicon optical adapter plate, or the silicon optical adapter plate can be integrated with the packaging substrate through a lead, or the silicon optical adapter plate can be directly connected with the packaging substrate. After the silicon optical adapter plate is used for integrating an electronic chip or an optoelectronic chip and a packaging substrate, interconnection and intercommunication of upper and lower electric signals are realized through a silicon through hole in the silicon optical adapter plate, integration of a three-dimensional framework is realized based on the integration of the silicon through hole and a silicon optical device, the integrated chip area is smaller, the integration degree is higher, and the formed three-dimensional framework has smaller electric signal delay and higher bandwidth and speed compared with the traditional plane framework or the three-dimensional framework integrated in a lead bonding mode.
Drawings
FIG. 1 is a flow diagram of a method of integrating a silicon optical interposer according to one embodiment of the present invention;
fig. 2 is a flowchart of an integration method of a three-dimensional architecture according to an embodiment of the present invention.
Detailed Description
The following describes an embodiment according to the present invention with reference to the drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
In order to improve the integration degree of a chip and reduce the delay of an electric signal, the invention provides a silicon optical adapter plate and an integration method of a three-dimensional framework.
Fig. 1 shows an embodiment of an integration method of a silicon optical interposer provided by the present invention, comprising the following steps:
s10, providing a wafer, and completing waveguide etching, epitaxy, ion implantation and thermode preparation of a silicon optical device on the wafer, wherein the silicon optical device comprises a silicon optical passive device and a silicon optical active device;
in this step, the wafer is preferably a SOI (Silicon-On-Insulator) wafer with a high impedance substrate having a top Silicon, a back substrate and a buried oxide layer therebetween.
Other auxiliary processes involved in waveguide etching, epitaxy, ion implantation and thermode preparation of the silicon optical device are all existing mature processes and are not core improvement points of the invention, so that the details are not repeated.
Silicon optical devices include silicon optical passive devices including, but not limited to, silicon or silicon nitride waveguides, gratings, arrayed waveguide gratings, microring resonators, multimode interferometers, thermo-optic devices, etc., and silicon optical active devices including, but not limited to, modulators and detectors.
In addition, the thermo-optical device and the silicon optical active device in the silicon optical passive device need to be powered on.
S11, depositing a first dielectric layer on the top layer of the silicon optical device and chemically and mechanically polishing the first dielectric layer, and downwards forming a thermo-optical device in the silicon optical passive device and a first contact hole of the silicon optical active device from the top layer of the first dielectric layer;
in this step, a first dielectric layer, which may be a silicon dioxide dielectric layer, may be deposited on the top layer of the silicon optical device by a plasma enhanced chemical vapor deposition method, for example.
After a first dielectric layer is formed through deposition, a first contact hole of the thermo-optic device and/or the silicon photo-active device is formed downwards on the top layer of the first dielectric layer.
For example, the first contact hole may be formed using any one of a copper process, a tungsten process, a gold process, an aluminum process, or an aluminum-copper process.
The method for forming the first contact hole will be described in detail below by taking a single damascene copper process as an example, specifically as follows:
and etching downwards from the top of the first dielectric layer by adopting dry etching to form a plurality of first holes, wherein the aperture of each first hole is not specifically limited, and a proper value can be selected according to actual process conditions.
Depositing a first isolation layer on the side wall and the bottom of the first hole, wherein the first isolation layer can be Ta, TaN or Ta + TaN, and it should be noted that the first isolation layer is deposited on the whole structure with the first hole, that is, the first isolation layer is deposited on the first dielectric layer while the first isolation layer is formed on the side wall and the bottom of the first hole.
The deposition of the first copper seed layer in the first hole with the first isolation layer is continued, and likewise the first copper seed layer is deposited on the first dielectric layer, in particular on the first isolation layer.
Continuing to fill copper in the first hole with the first isolation layer and the first copper seed layer by using an electrochemical plating process (ECP), and similarly, plating the copper on the first dielectric layer, specifically on the first copper seed layer;
and finally, forming a first contact hole which is flush with the top surface of the first dielectric layer by the first hole, the first isolation layer formed in the first hole, the first copper seed layer and the copper.
The first contact hole is in contact with the thermo-optic device and/or the silicon photo-active device, and can communicate the thermo-optic device and/or the silicon photo-active device with the electrode to energize the thermo-optic device and/or the silicon photo-active device.
After the first contact hole is formed by adopting a single damascene copper process, in order to avoid copper oxidation in subsequent processes, a first stop layer needs to be deposited on the top layer of the formed structure, and the first stop layer can be silicon nitride.
It should be further noted that, if the first contact hole is formed by using a copper process or a gold process, the copper and the gold are formed in the first contact hole by using an electrochemical plating method, and annealing and chemical mechanical polishing are performed for the copper process, while chemical mechanical polishing is performed for the gold process. If the first contact hole is formed by adopting an aluminum process or an aluminum-copper process, aluminum or aluminum-copper needs to be formed in the first hole by adopting a deposition mode, and then etching is carried out. If a tungsten process is used, tungsten is deposited into the first hole and then chemically mechanically polished.
S12, depositing a second dielectric layer, and forming a plurality of through silicon vias downwards from the top layer of the second dielectric layer;
in this step, a second dielectric layer may be deposited on the top layer of the silicon optical device having the first contact hole by a vapor deposition method such as plasma enhanced chemical, i.e., the second dielectric layer completely covers the first contact hole and the first dielectric layer, or the first via hole and the first stop layer, and the second dielectric layer may be a silicon dioxide dielectric layer.
And after a second dielectric layer is formed by deposition, a plurality of through silicon vias are formed downwards on the top layer of the second dielectric layer.
The through-silicon via may be formed using any one of a copper process, a tungsten process, or a gold process, but a copper process is generally used.
The method for forming the through silicon via will be described in detail below by taking a single damascene copper process as an example, specifically as follows:
the second hole may be formed by DRIE etching, and the diameter of the second hole is not specifically limited herein, and may be selected to have a suitable value according to the actual application requirement and DRIE process conditions.
A second spacer, which may be Ta, TaN or Ta + TaN, is deposited on the sidewalls and bottom of the second hole. It should be noted that the second isolation layer is deposited on the entire structure with the second hole, that is, the second isolation layer is deposited on the second dielectric layer while the second isolation layer is formed on the sidewall and the bottom of the second hole;
continuously depositing a second copper seed layer in the second hole with the second isolation layer, wherein the second copper seed layer is also deposited on the second dielectric layer, particularly the second isolation layer;
continuously filling copper in a second hole with a second isolating layer and a second copper seed layer by adopting an electrochemical plating process, wherein the copper is also plated on a second dielectric layer, particularly a second copper seed layer;
and finally, removing the copper, the second copper seed layer and the second isolating layer on the surface of the second dielectric layer by adopting an annealing and chemical mechanical polishing mode, and finally forming the silicon through hole which is flush with the top surface of the second dielectric layer by the second hole, the second isolating layer formed in the second hole, the second copper seed layer and the copper.
After the single damascene copper process is used to form the through-silicon via, in order to avoid oxidation of copper in subsequent processes, a second stop layer needs to be deposited on the top layer of the formed structure, and the second stop layer may be silicon nitride.
The number of the silicon through holes is a plurality, the silicon through holes are distributed on the side faces of the thermo-optic device and/or the silicon-optic active device, and a certain distance is reserved between the silicon through holes and the thermo-optic device and/or the silicon-optic active device.
The method comprises the following steps: the vertical distance between the through silicon via and the adjacent surface of the thermo-optic device and/or the silicon photo-active device is not less than 1.5 times the diameter of the through silicon via. The vertical distance between the central axes of two adjacent through silicon vias is not less than 3 times the diameter of the through silicon via.
The through silicon vias have the optimal distance from the thermo-optic device and/or the silicon-optic active device and the optimal distance between the adjacent through silicon vias, so that the adverse influence of the stress at the through silicon vias on the thermo-optic device and/or the silicon-optic active device or the mutual adverse influence between the through silicon vias can be avoided.
It needs to be further explained that: if the through silicon via is formed by a copper process or a gold process, copper and gold are formed in the second hole by adopting an electrochemical plating mode, annealing and chemical mechanical polishing are carried out aiming at the copper process, and chemical mechanical polishing is carried out aiming at the gold process. If a tungsten process is used, tungsten is deposited into the second hole and then chemical mechanical polishing is performed.
S13, depositing a third dielectric layer, and forming electrodes corresponding to the thermo-optic device and/or the silicon photo-active device on the top layer of the third dielectric layer; each electrode corresponds to the first contact hole and the silicon through hole, and a second contact hole and a third contact hole which are connected with the first contact hole and the silicon through hole are respectively formed downwards from the bottom of each electrode;
in this step, a third dielectric layer may be deposited on the top layer of the silicon optical device having the first contact hole and the through-silicon via by a vapor deposition method such as plasma enhanced chemical, where the third dielectric layer covers the through-silicon via and the second dielectric layer, or the through-silicon via and the second stop layer completely, and the third dielectric layer may be a silicon dioxide dielectric layer.
And depositing to form a third dielectric layer, and then forming an electrode, a second contact hole and a third contact hole downwards on the top layer of the third dielectric layer.
The electrode, the second contact hole, and the third contact hole may be formed using any one of a copper process, a tungsten process, a gold process, an aluminum process, and an aluminum-copper process.
The method for forming the electrode, the second contact hole and the third contact hole will be described in detail below by taking the dual damascene copper process as an example, specifically as follows:
and forming an electrode groove corresponding to the thermo-optic device and/or the silicon-optic active device on the third dielectric layer by adopting any one of the conventional etching methods such as dry etching and the like, and continuously etching downwards from the bottom of the electrode groove to form a third hole corresponding to the first contact hole and a fourth hole corresponding to the through silicon via.
Depositing a third isolating layer at one time on the inner sides and the bottoms of the electrode groove, the third hole and the fourth hole, wherein the third isolating layer can be any one of Ta, TaN or Ta + TaN, and the third isolating layer is deposited on the whole structure with the electrode groove, the third hole and the fourth hole, namely, the third isolating layer is deposited on the third dielectric layer while the third isolating layer is formed on the side walls and the bottoms of the electrode groove, the third hole and the fourth hole;
continuously depositing a third copper seed layer in the electrode groove with the third isolation layer, the third hole and the fourth hole, wherein the third copper seed layer is also deposited on the third dielectric layer, particularly the third isolation layer;
filling copper in the electrode groove, the third hole and the fourth hole of a third copper seed layer with a third isolating layer and the third copper seed layer by adopting an electrochemical plating process, wherein the copper is plated on a third dielectric layer, particularly a second copper seed layer;
and then, removing the copper, the third copper seed layer and the third isolating layer formed on the surface of the third medium layer in the process by adopting an annealing and chemical mechanical polishing mode.
An electrode which can be opposite to the thermo-optical device and/or the silicon optical active device is formed by the electrode groove, the third isolating layer, the third copper seed layer and copper; a second contact hole is formed by the third hole, the third isolating layer, the third copper seed layer and copper, and the second contact hole can communicate the electrode with the first contact hole so as to communicate the electrode with the thermo-optic device and/or the silicon-optic active device; and a third contact hole is formed by the fourth hole, the third isolating layer, the third copper seed layer and copper, and can communicate the electrode with the silicon through hole so as to communicate the electrode with the thermo-optic device and/or the silicon-optic active device.
When the electrode is formed by adopting a dual damascene copper process, when the characteristic dimension of the electrode is larger than 20 microns, a grid type dielectric isolation structure is required to be arranged to prevent the copper surface from being sunken when the subsequent chemical mechanical polishing is carried out.
It needs to be further explained that: if the electrode, the second contact hole and the third contact hole are formed by a copper process or a gold process, copper and gold are formed in the electrode groove, the third hole and the fourth hole by adopting an electrochemical plating mode, annealing and chemical mechanical polishing are carried out aiming at the copper process, and chemical mechanical polishing is carried out aiming at the gold process. If the electrode, the second contact hole and the third contact hole are formed by adopting an aluminum process or an aluminum-copper process, aluminum or aluminum-copper is formed in the electrode groove, the third hole and the fourth hole by adopting a deposition mode, and then etching is carried out. If the tungsten process is adopted, tungsten is formed in the electrode groove, the third hole and the fourth hole in a deposition mode, and then chemical mechanical polishing is carried out.
It should be further noted that if the electrode is formed by a copper process, a third stop layer, which may be silicon nitride, is deposited after the top layer of the formed structure is chemically and mechanically polished and before the fourth dielectric layer is deposited.
S14, chemically and mechanically polishing the top layer of the formed structure, depositing a fourth dielectric layer, Opening a Bonding Pad Opening (BPO) through the fourth dielectric layer, and forming a first micro-bump under-metal or a first micro-bump;
in this step, after the electrode, the second contact hole and the third contact are formed, the top layer of the formed structure is subjected to chemical mechanical polishing, and a fourth dielectric layer is deposited, wherein the fourth dielectric layer can be a silicon dioxide dielectric layer.
After the fourth dielectric layer is formed by deposition, a bonding pad window is formed by etching, and a first micro bump under-metal is preferably formed on the bonding pad window by an electrochemical plating process, although the first micro bump can also be formed on the bonding pad window by the electrochemical plating process.
S15, grinding the back surface of the wafer to expose the through silicon via;
in this step, the front side of the formed structure may be temporarily bonded to a carrier wafer, which may be a bulk silicon wafer, using a thermoplastic material.
And grinding the back surface of the wafer by adopting any conventional grinding process so as to reduce the thickness of the wafer until the through silicon via is exposed.
S16, depositing a passivation layer on the back of the wafer;
and S17, etching the passivation layer to form a passivation layer window of the through silicon via, and forming a rewiring layer and a second micro-bump lower metal or a second micro-bump at the passivation layer window, or only forming the second micro-bump lower metal or the second micro-bump at the passivation layer window.
In this step, preferably, an electrochemical plating process is adopted to form a second micro-bump at the passivation layer window;
optionally, an electrochemical plating process is used to form a second micro-under-bump metallization at the passivation layer window.
Based on the above embodiments, the first micro-bump under-metal is Cu/Ni/Au, and the first micro-bump is Cu/Ni/SnAg.
The invention also provides an integration method of the three-dimensional architecture, which comprises the following steps (see fig. 2 in particular):
s20, providing a silicon optical adapter plate prepared by the integration method of the silicon optical adapter plate;
s21, bonding an electronic chip or an optoelectronic chip by using the first metal under the first micro-bump or the first micro-bump of the silicon optical adapter plate;
s22, bonding the silicon adapter plate by utilizing the redistribution layer of the silicon optical adapter plate and the second metal or the second micro bump under the second micro bump, or the second metal or the second micro bump under the second micro bump of the silicon optical adapter plate;
and S23, communicating the silicon adapter plate with the packaging substrate through a third micro-bump lower metal or a third micro-bump arranged on the back surface of the silicon adapter plate, or communicating the silicon adapter plate with the packaging substrate through a lead.
As another alternative embodiment, the redistribution layer of the silicon optical interposer and the second micro under bump metal or the second micro bump, or the second micro under bump metal or the second micro bump of the silicon optical interposer are directly connected to the package substrate.
Based on the above embodiments, further, the third under-bump metallurgy is Cu/Ni/Au, and the third micro-bump is Cu/Ni/SnAg.
In summary, the invention monolithically integrates the silicon optical device and the through-silicon via to form a silicon optical interposer, the front side of the silicon optical interposer may form a first micro-bump or a first micro-bump under metal (UBM) capable of being integrated with the electronic chip or the optoelectronic chip on the bonding pad window by an electrochemical plating process, the back side of the silicon optical interposer may form a second micro-bump or a second micro-bump under metal on the passivation layer window by an electrochemical plating to communicate with the silicon interposer, further, the silicon interposer may be integrated with the package substrate by a third micro-bump or a third micro-bump under metal on the back side thereof, or the silicon interposer may be integrated with the package substrate by a lead, or the silicon optical interposer may be directly connected with the package substrate, the electronic chip or the optoelectronic chip is integrated by the silicon optical interposer, and after the package substrate, the interconnection and the interconnection of the up and down electrical signals are realized by the through-silicon via in the silicon optical interposer, the integration of a three-dimensional framework is realized based on the integration of the silicon through hole and the silicon optical device, the integrated chip area is smaller, the integration degree is higher, and compared with the traditional plane framework or the three-dimensional framework integrated in a lead bonding mode, the formed three-dimensional framework has smaller electric signal delay and higher bandwidth and speed.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (17)
1. An integration method of a silicon optical adapter plate is characterized by comprising the following steps:
providing a wafer, and completing waveguide etching, epitaxy, ion implantation and thermode preparation of a silicon optical device on the wafer, wherein the silicon optical device comprises a silicon optical passive device and a silicon optical active device;
depositing a first dielectric layer on the top layer of the silicon optical device and carrying out chemical mechanical polishing, and forming a thermo-optical device in the silicon optical passive device and/or a first contact hole of the silicon optical active device downwards from the top layer of the first dielectric layer;
depositing a second dielectric layer, and forming a plurality of through silicon vias downwards from the top layer of the second dielectric layer;
depositing a third dielectric layer, and forming an electrode corresponding to the thermo-optic device and/or the silicon photo-active device on the top layer of the third dielectric layer; each electrode corresponds to the first contact hole and the silicon through hole, and a second contact hole and a third contact hole which are connected with the first contact hole and the silicon through hole are respectively formed downwards from the bottom of each electrode;
chemically and mechanically polishing the top layer of the formed structure, depositing a fourth medium layer, forming a bonding pad window through the fourth medium layer, and forming a first micro-bump lower metal or a first micro-bump, wherein the bonding pad window is positioned above the electrode;
grinding the back surface of the wafer to expose the through silicon via;
depositing a passivation layer on the back side of the wafer;
etching the passivation layer to form a passivation layer window of the through silicon via, and forming a rewiring layer and a second micro-bump lower metal or a second micro-bump at the passivation layer window; or forming the second micro-bump under metal or the second micro-bump at the passivation layer window.
2. The method of claim 1, wherein the step of forming a first contact hole down from the top layer of the first dielectric layer comprises:
etching downwards from the top layer of the first dielectric layer to form a first hole;
depositing a first isolation layer on the side wall and the bottom of the first hole;
electrochemically plating or depositing a first metal in the first hole;
and chemically and mechanically polishing or etching to remove the first metal and the first isolating layer on the surface of the first dielectric layer.
3. The method of claim 2, wherein the first metal is copper, and the first hole is filled with copper by an electrochemical plating process and annealed and chemically mechanically polished;
and depositing a first stop layer after the first contact hole is formed and before the second dielectric layer is deposited.
4. The method of claim 3, wherein the step of forming through-silicon-vias down from the top layer of the second dielectric layer comprises:
etching downwards from the top layer of the second dielectric layer to form a second hole;
depositing a second isolation layer on the side wall and the bottom of the second hole;
electrochemically plating a second metal in the second hole;
and chemically and mechanically polishing to remove the second metal and the second isolating layer on the surface of the second dielectric layer.
5. The method of claim 4, wherein the second metal is copper, and the second hole is filled with copper by an electrochemical plating process and is annealed and chemically mechanically polished;
and depositing a second stop layer after the silicon through hole is formed and before the third dielectric layer is deposited.
6. The method of claim 5, wherein the step of forming the electrode, the second contact hole, and the third contact hole comprises:
etching the top layer of the third dielectric layer respectively to form a plurality of electrode grooves, and etching downwards from the bottoms of the electrode grooves respectively to form a third hole and a fourth hole;
depositing a third isolating layer on the side walls and the bottoms of the electrode grooves, the third holes and the fourth holes;
electrochemically plating or depositing a third metal in the electrode groove, the third hole and the fourth hole;
and chemically and mechanically polishing or etching to remove the third metal and the third isolating layer on the surface of the third dielectric layer.
7. The method of claim 6, wherein the third metal is copper, and the electrode trenches, the third hole and the fourth hole are filled with copper by an electrochemical plating process and annealed and chemically mechanically polished;
and depositing a third stop layer after the electrode, the second contact hole and the third contact hole are formed and before the fourth medium layer is deposited.
8. The method of claim 6, wherein the first, second, and third spacers are each Ta, TaN, or Ta + TaN.
9. The method of claim 1, wherein the first, second, third and fourth dielectric layers are silicon dioxide dielectric layers.
10. The method of claim 7, wherein the first, second, and third stop layers are silicon nitride.
11. The method of claim 1, wherein the first, second, third, and fourth dielectric layers are formed by plasma enhanced chemical vapor deposition.
12. The method of claim 6, wherein the first hole, the third hole, the fourth hole, and the electrode trench are formed by dry etching.
13. The method of claim 4, wherein the second hole is formed using DRIE etching.
14. The method of integrating a silicon light interposer as recited in claim 1, wherein:
the vertical distance between the silicon through hole and the adjacent surface of the thermo-optic device and/or the silicon optic active device is not less than 1.5 times of the diameter of the silicon through hole;
and the vertical distance between the central axes of two adjacent through silicon holes is not less than 3 times of the diameter of the through silicon hole.
15. The method of integrating a silicon light interposer as recited in claim 1, wherein:
the first micro-bump is made of metal Cu/Ni/Au, and the first micro-bump is made of Cu/Ni/SnAg;
and the metal under the second micro-bump is Cu/Ni/Au, and the second micro-bump is Cu/Ni/SnAg.
16. A method for integrating a three-dimensional architecture, comprising the steps of:
providing a silicon light interposer prepared using the integration method of any of claims 1-15;
bonding an electronic chip or an optoelectronic chip by using the first micro-bump underbump metal or the first micro-bump of the silicon optical adapter plate;
bonding the silicon optical adapter plate by utilizing the redistribution layer of the silicon optical adapter plate and the second micro-bump under-metal or the second micro-bump, or the second micro-bump under-metal or the second micro-bump of the silicon optical adapter plate;
the silicon adapter plate is communicated with the packaging substrate through a third micro-bump lower metal or a third micro-bump arranged on the back surface of the silicon adapter plate;
or, the redistribution layer of the silicon optical adapter plate and the second micro-bump under metal or the second micro-bump, or the second micro-bump under metal or the second micro-bump of the silicon optical adapter plate is bonded with the silicon adapter plate and directly communicated with the packaging substrate.
17. The method of claim 16, wherein the third metal under bump is Cu/Ni/Au and the third micro bump is Cu/Ni/SnAg.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911120086.0A CN110854025A (en) | 2019-11-15 | 2019-11-15 | Silicon optical adapter plate and integration method of three-dimensional framework |
| SG11202012334SA SG11202012334SA (en) | 2019-11-15 | 2019-11-21 | Method for manufacturing silicon optical interposer, method for manufacturing three-dimensional structure, method for integrating surface-electrode ion trap and silicon photoelectronic device, integrated structure, and three-dimensional structure |
| PCT/CN2019/119912 WO2021092991A1 (en) | 2019-11-15 | 2019-11-21 | Integrated method for silicon optical adapter plate and three-dimensional architecture and for surface electrode ion trap, silicon optical device and three-dimensional architecture, integrated structure and three-dimensional architecture |
| US17/121,396 US11810986B2 (en) | 2019-11-15 | 2020-12-14 | Method for integrating surface-electrode ion trap and silicon photoelectronic device, integrated structure, and three-dimensional structure |
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| CN201911120086.0A CN110854025A (en) | 2019-11-15 | 2019-11-15 | Silicon optical adapter plate and integration method of three-dimensional framework |
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