CN116990907A

CN116990907A - Photonic integrated circuit chip and method of manufacturing the same

Info

Publication number: CN116990907A
Application number: CN202210433905.2A
Authority: CN
Inventors: 达迪·塞蒂亚迪; 彭博; 苏湛; 吴建华; 孟怀宇; 沈亦晨
Original assignee: Shanghai Xizhi Technology Co ltd
Current assignee: Shanghai Xizhi Technology Co ltd
Priority date: 2022-04-24
Filing date: 2022-04-24
Publication date: 2023-11-03

Abstract

The invention relates to the field of semiconductors, and provides a photonic integrated circuit chip and a manufacturing method thereof, wherein the method comprises the following steps: providing a photonic integrated structure; providing a first substrate, wherein the first substrate comprises a groove; bonding the photonic integrated structure to the first substrate; removing a portion of the photonic integrated structure to form an optical coupling end that enables coupling of light into the photonic integrated circuit chip from a side of the photonic integrated circuit; the side surface of the photonic integrated structure, where the optical coupling end is located, corresponds to the groove of the first substrate. Which enables optimization of the fabrication process and optical coupling of photonic integrated circuit chips.

Description

Photonic integrated circuit chip and method of manufacturing the same

Technical Field

The present invention relates to the field of semiconductors, and more particularly, to photonic integrated circuit chips and methods of fabricating the same.

Background

In photonic integrated circuits, external light is typically required to be input into the photonic integrated circuit, and there are generally two modes of coupling light into the photonic integrated circuit, vertical coupling and end-face coupling. Wherein the end-face coupling is such that light enters the photonic integrated circuit chip from the side. In end-face coupling: the optical fiber can be laterally coupled to the photonic integrated circuit chip independent of the wavelength of the light, and thus an efficient optical coupling can be achieved.

In end-face coupling, it is important to manufacture a suitable coupling structure and to optimize the manufacturing process.

Disclosure of Invention

The invention provides a photonic integrated circuit chip and a manufacturing method thereof.

In one exemplary embodiment, a method of fabricating a photonic integrated circuit chip is provided, comprising: providing a photonic integrated structure; providing a first substrate, wherein the first substrate comprises a groove; bonding the photonic integrated structure to the first substrate; removing a portion of the photonic integrated structure to form an optical coupling end that enables coupling of light from a side of the photonic integrated circuit into the optical sub-integrated circuit chip; the side surface of the photonic integrated structure, where the optical coupling end is located, corresponds to the groove of the first substrate.

In some embodiments, including in the step of providing a photonic integrated structure, the photonic integrated structure provided includes a first dielectric layer; the step of providing a photonic integrated structure includes: forming the photonic integrated structure based on an SOI substrate, wherein the SOI substrate comprises a back substrate, an insulating layer and a top silicon, and the first dielectric layer is from the insulating layer in the SOI substrate; and removing the backing bottom.

In some embodiments, after bonding the photonic integrated structure to the first substrate, a portion of the photonic integrated structure is removed to form the optical coupling end.

In some embodiments, a portion of the photonic integrated structure is removed to form the optical coupling end prior to bonding the photonic integrated structure to the first substrate.

In some embodiments, a portion of the photonic integrated structure is removed by etching to form an optical coupling end.

In some embodiments, further comprising: cutting the first substrate, wherein the first substrate passes through the groove of the first substrate during cutting.

In some embodiments, the photonic integrated structure includes a waveguide, the optical coupling end being capable of coupling light to the waveguide.

In some embodiments, the removing a portion of the photonic integrated structure to form an optical coupling end, wherein the removed portion includes portions on both sides of the waveguide.

In some embodiments, the photonic integrated circuit chip includes an edge coupler, the light coupling end being capable of coupling light to the edge coupler.

In some embodiments, in the step of providing a photonic integrated structure, the photonic integrated structure further comprises: a first opening, and a conductive material disposed in the first opening; in the step of providing a first substrate, the first substrate further includes: a second opening, and a conductive material disposed in the second opening; in the step of bonding the photonic integrated structure to the first substrate, the first openings are aligned with the second openings, and the conductive material in the first openings is electrically connected with the conductive material in the corresponding second openings.

In some embodiments, including forming a fifth dielectric layer on a first side of the first substrate; and, in the step of bonding the photonic integrated structure to the first substrate, the fifth dielectric layer is positioned between the photonic integrated structure and the first substrate.

In one exemplary embodiment, a photonic integrated circuit chip is presented, comprising: a first substrate comprising a recess; a photonic integrated structure comprising an optical coupling end at a side thereof, the optical coupling end enabling coupling of light from the side of the photonic integrated circuit chip into the photonic integrated circuit chip; the side surface of the optical coupling end corresponds to the groove of the first substrate.

In some embodiments, the photonic integrated circuit chip is obtained by bonding the photonic integrated structure to the first substrate.

In some embodiments, the photonic integrated structure includes a first dielectric layer; the first dielectric layer is from an insulating layer in an SOI substrate, and an original back substrate in the SOI substrate is removed, and the photonic integrated structure is bonded to the first substrate on a side where the back substrate is removed.

In some embodiments, the photonic integrated circuit includes a waveguide, and the optical coupling end is configured to enable optical coupling to the waveguide.

In some embodiments, the photonic integrated structure comprises: a first opening, and a conductive material disposed in the first opening; a first substrate, the first substrate comprising: a second opening, and a conductive material disposed in the second opening; the first openings are aligned with the second openings, and the conductive material in the first openings is electrically connected with the conductive material in the corresponding second openings.

In one exemplary embodiment, a package structure of a photonic integrated circuit chip is provided, which includes the photonic integrated circuit chip of the present invention, and an optical fiber coupled to the optical coupling terminal.

In some embodiments, the photonic integrated circuit chip includes a receiving space below the photo-coupling end, and the encapsulation structure includes an adhesive disposed in the receiving space.

The invention can optimize the manufacturing process and the optical coupling mode of the photonic integrated circuit chip.

Various aspects, features, advantages, etc. of embodiments of the invention will be described in detail below with reference to the accompanying drawings. The above aspects, features, advantages and the like of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Drawings

FIGS. 1A-7 are schematic diagrams illustrating some states or results of photonic integrated circuit chip fabrication in one embodiment;

FIG. 8 illustrates a cross-sectional view of a photonic integrated circuit chip of an embodiment;

FIG. 9 illustrates a top view along the plane of AA' in FIG. 8, in one embodiment;

FIG. 10 illustrates a package structure of a photonic integrated circuit chip in one embodiment;

FIG. 11 illustrates a top view along the plane of AA' in FIG. 8, in one embodiment;

fig. 12A-12B illustrate a schematic diagram of some states or results of photonic integrated circuit chip fabrication in one embodiment.

Detailed Description

In order to facilitate understanding of the various aspects, features and advantages of the technical solution of the present invention, the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the various embodiments described below are for illustration only and are not intended to limit the scope of the present invention.

The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used in this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used in this disclosure, the term "and/or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of a and B" means a alone, B alone, or both a and B. In this disclosure, a substrate may refer to an uncut substrate, such as an uncut wafer, and may also refer to a cut substrate. In the present disclosure, the chip may include a bare chip (die). Features of one embodiment may also be applied and incorporated as features of other embodiments described in the present disclosure as appropriate in the present disclosure.

The method for manufacturing the photonic integrated circuit chip adopts a conventional semiconductor process, so that the photonic integrated circuit chip is also a method for manufacturing a semiconductor structure, and the semiconductor structure is correspondingly manufactured. Fig. 1A to 1C show steps of forming the provided photonic integrated structure, that is, steps of preparing the photonic integrated structure.

As shown in fig. 1A, in particular, the photonic integrated structure may be fabricated based On a semiconductor layer On an Insulator, such as Silicon-On-Insulator (SOI), silicon-germanium-On-Insulator (S-SiGeOI), or the like, and in addition, other substrates may be provided for fabricating the photonic integrated structure, and the substrate material may be: silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, compound semiconductors, alloy semiconductors, or the like, or combinations of the above materials. The substrate may be a wafer, such as an SOI wafer. Taking a Silicon-On-Insulator (SOI) substrate as an example, an SOI substrate is provided that includes a back substrate, an insulating layer, and a top layer of Silicon. Illustratively, the insulating layer is a buried oxide layer. Wherein the insulating layer acts as a first dielectric layer, fig. 1A shows a backing bottom 101, a first dielectric layer 102, and a top layer of silicon 103. Wherein the back substrate may be a wafer, such as a silicon wafer. The first dielectric layer has a first side and a second side opposite the first side, wherein a top layer of silicon 103 is located on the first side of the first dielectric layer 102 and a backing bottom 101 is located on the second side of the first dielectric layer.

As shown in fig. 1B, in the step of forming the photonic integrated structure, forming the photonic device layer 104 based on the SOI substrate may be included, and the photonic device layer 104 includes various types of photonic devices, such as a waveguide, a grating coupler, an optical modulator, a directional coupler, a multimode interferometer (MMI), a photodetector, an optical beam splitter, and the like. The photonic device may be formed by photolithography, etching, patterning, etc., as well as deposition, doping steps based on the top layer silicon. In forming the photonic device, it may include depositing different types of semiconductor materials as well as metallic materials. Illustratively, in FIG. 1C, photonic device layer 104 includes waveguides 1041, which may be used to form, for example, edge couplers, and 1042 in photonic device layer 104 may be a waveguide, as well as other photonic devices.

Illustratively, the photonic devices are located above (on the first side of) the first dielectric layer 102, where the various types of photonic devices may be one or more.

After the photonic devices are formed, a second dielectric layer 105 is formed, the second dielectric layer 105 covering one or more of the photonic devices, as shown in fig. 1C. A suitable number of conductive connection structures (not shown) may be provided in the second dielectric layer 105 to electrically connect to one or more photonic devices. Alternatively, the second dielectric layer 105 may include a plurality of sub-layers.

As shown in fig. 1D, electrical connection structures and other material layers may be further formed as desired. Wherein a first conductive layer M1, such as a first metal layer, may be formed on the second dielectric layer 105; also shown is the formation of a third dielectric layer 106 and a fourth dielectric layer 107 on the second dielectric layer 105.

As shown in fig. 2A, the third dielectric layer 106 and the fourth dielectric layer 107 may be stacked alternately, and the thickness and the material of each layer may be inconsistent, and the material of the third dielectric layer and the fourth dielectric layer may be, for example, silicon oxide and silicon nitride. A conductive connection structure is formed in the photonic integrated structure, wherein the conductive connection structure comprises conductive layers (M1, M2), and conductive vias V12, which may be used to connect the conductive layers, the number of conductive layers and conductive vias may be set as desired. The conductive layer surrounds the third dielectric layer and/or the fourth dielectric layer. The number of conductive connection structures may be set as desired, some of which may be used to electrically connect with the photonic device and some of which may be used to electrically connect with the second conductive openings in the first substrate to be bonded. Pads 108 may also be formed according to electrical connection requirements.

As in fig. 2B, the formation of the first recess 110, and the formation of UBM109 is shown. The first recess 110 may be formed by removing a portion of the light-integrating structure, and a method such as etching may be employed.

As shown in fig. 2C, a cladding layer 120 is formed. Cladding layer 120 has a suitable refractive index and may be, for example, an insulating material. The area covered by the cladding layer 120 includes the upper surface of the photonic integrated structure, the sidewalls, and the exposed second dielectric layer 105.

As in fig. 2D, the photonic integrated structure has a first side and a second side opposite the first side, and fig. 2D shows thinning the second side of the photonic integrated structure to remove the back substrate from the SOI substrate, thereby exposing the first dielectric layer 102 at the second side of the photonic integrated structure. Alternatively, the insulating layer in a part of the SOI substrate may be thinned. Therefore, the first dielectric layer 102 is an insulating layer in an SOI substrate, and the insulating layer in the SOI substrate may be directly used as the first dielectric layer 102, or the first dielectric layer 102 may be obtained by performing a process such as thinning of the insulating layer in the SOI substrate.

As shown in fig. 2E, after the first substrate is removed, a process including forming a conductive structure may be selected according to electrical connection requirements. Illustratively, a first opening 111 is formed, the first opening 111 extending in the first dielectric layer 102. Two first openings 111 corresponding to one M1 are shown in fig. 2E. For example, when the first opening 111 is provided in the first dielectric layer, it also includes a case where the first opening 111 extends in other material layers, for example, when the first opening 111 is formed, the first opening 111 may extend in the first dielectric layer 102 and extend in the second dielectric layer 105, and the first opening includes a first portion in the first dielectric layer and a second portion in the second dielectric layer. In the example of fig. 2E, etching may be started from the second side of the photonic integrated structure, thereby forming the first opening 111.

As shown in fig. 3, a conductive material is formed in the first opening, thereby forming a first conductive opening 112, and the first conductive opening 112 is electrically connected to the conductive layer M1. The first openings can penetrate through the first dielectric layer, and the corresponding first conductive openings penetrate through the first dielectric layer to form first conductive through holes. The first opening penetrates through the first dielectric layer and the second dielectric layer. The first conductive opening 112 is electrically connected to the conductive layer M1, and penetrates through the first dielectric layer 102 and the second dielectric layer 105. Illustratively, the present invention may include a damascene process in forming the first conductive openings 112.

Fig. 4A-4E illustrate steps of providing a first substrate 201, and processing the first substrate.

Fig. 4A-4B illustrate forming a second opening in and in the first substrate 201. As shown in fig. 4A, an original substrate is provided as the first substrate 201, for example, a silicon substrate, but is not limited thereto. In fig. 4B, a second opening 202 is formed in the original substrate by etching, and then a conductive material 204a (as in fig. 4C) is formed, thereby forming a second conductive opening 204. Optionally, before the conductive material 204a is disposed, an isolation layer 204b may be formed, and the second conductive opening 204 may include the isolation layer 204b and the conductive material 204a in the second opening, where the isolation layer may include an insulating material. In this process, conventional through-silicon via fabrication processes may be employed.

Illustratively, the first substrate has a first side and a second side, and fig. 4B illustrates forming the second aperture from the first side. Then, a conductive material is disposed in the second opening to form a conductive material layer, thereby forming a conductive opening. Illustratively, the step of forming an insulating material on the sidewalls and bottom of the second opening may be included to form an insulating isolation layer. In some embodiments, the insulating layer may cover the first side of the first substrate in addition to the sidewalls and the bottom. In some embodiments, the second openings are filled using copper metallization and using copper plating techniques to form conductive openings.

Optionally, before disposing the conductive material 204b in the second opening, a step of forming a barrier layer may be further included, where the barrier layer may be used as a diffusion barrier to prevent diffusion of metal in the conductive material layer to the substrate, and may also be used as an adhesive layer between the conductive material and the dielectric. An exemplary barrier layer may be, for example, taN, ta, ti, tiN, but is not limited thereto.

The material of the conductive material layer in the second opening may be copper or a copper-based alloy. Exemplary conductive materials may also include tungsten, aluminum, etc., as well as other materials having good conductive properties. After the conductive material layer is formed. The redundant conductive material layer and the blocking layer which are covered on the surface of the first substrate can be removed through grinding, etching and other processes. In some embodiments, the insulating isolation layer partially or completely covering the surface of the substrate may be removed by polishing, etching, or the like.

Alternatively, the first substrate may be a transparent substrate, such as a glass substrate, a quartz substrate, etc., or other substrate materials commonly known in the art.

In fig. 4C, a second conductive aperture 204 is shown formed in the first substrate 201, the second conductive aperture 204 being formed on a first side of the substrate 201. After the second conductive opening 204 is formed, as shown in fig. 4D, optionally, a dielectric layer (fifth dielectric layer 205) is further formed covering the first substrate surface and the second conductive opening. And forming a third opening in the fifth dielectric layer, and disposing a conductive material in the third opening to form a third conductive opening 206, wherein the third conductive opening 206 may penetrate through the fifth dielectric layer 205, thereby forming a third conductive via. The third conductive opening is electrically connected with the second conductive opening. The third conductive opening may be a plug (plug), such as a copper plug, but may also include other metal materials or conductive materials. Wherein the third opening, the second opening may have different opening area sizes on the aligned side. For example, there may be one or more third apertures aligned with the same second aperture, for example two third apertures are shown aligned to the second aperture. Unless specifically stated otherwise, "alignment" between apertures in the present disclosure includes the case (for example, alignment of a third aperture with a second aperture), where alignment of the third aperture with the second aperture does not require strict centering of the apertures; in some cases, the opening area of the third opening on the aligned side and the opening area of the second opening on the aligned side may only partially overlap, only to perform the function of a normal conductive connection. For example, the third conductive opening may include a damascene process during formation.

Fig. 4E illustrates forming a groove 211 in the first substrate. In some embodiments, the recess 211 may be replaced by an opening, wherein, for example, etching may be used, or other common semiconductor processes for forming the recess or opening may be used.

In fig. 5, the photonic integrated structure is bonded to a first substrate. The recess 211 of the first substrate 201 corresponds to the location of the optical coupling end in the photonic integrated structure when bonded.

In some embodiments, the photonic integrated structure has a first side and a second side opposite the first side, the first dielectric layer is exposed at the second side of the photonic integrated structure, and the second side of the first dielectric layer 102 is bonded toward the first substrate 201. Illustratively, when bonded, the second side of the first dielectric layer is oriented toward the first side of the first substrate such that the first opening 111 of the photonic integrated structure is aligned with the second opening 202 of the first substrate 201 such that the conductive material in the first opening 111, the second opening 202 is electrically connected, i.e., the first conductive opening is aligned with the corresponding second conductive opening, and is electrically connected. Wherein the first and second openings may have different opening area sizes on the aligned side, the alignment of the first and second openings need not be exactly such that their centers are aligned. In some cases, the open area of the first opening on the aligned side and the open area of the second opening on the aligned side may only partially overlap, only to perform the function of a normal conductive connection. For example, there may be one or more second openings aligned with the same first opening, two first openings aligned with the same second opening being shown in fig. 5, and, in turn, corresponding two first conductive openings 112 aligned with the same second conductive opening 204. In some embodiments, the photonic integrated structure may have a plurality of first apertures, and each second aperture may be aligned with one or a set of first apertures, wherein a set of first apertures includes a plurality of first apertures. The photonic integrated structure removes the back substrate without forming a via in the back substrate, reducing the process conditions that may adversely affect the photonic integrated structure when forming a via in the back substrate.

For example, the first and second openings may have different pore sizes, e.g., the first opening may have a smaller pore size than the second opening. In some embodiments, the aperture of the second opening is 2-10 times that of the first opening, and the number of the second openings corresponding to one first opening can be adjusted according to the size of the opening size, so as to obtain proper electrical connection performance.

In fig. 5, a fifth dielectric layer 205 is further provided between the first substrate and the photonic integrated structure, and the third conductive openings 206 are electrically connected to the corresponding first conductive openings 112 when bonding. The third openings are aligned with the corresponding first openings, i.e., the third conductive openings 206 are aligned with the corresponding first conductive openings 112. Illustratively, the native oxide/insulating layer (buried oxide layer) of the SOI substrate in the photonic integrated structure may serve as the bonding layer.

The bond between the photonic integrated structure and the first substrate may employ an oxide-oxide bond, such as a silicon oxide (SiOx) -silicon oxide (SiOx) bond. Illustratively, the first dielectric layer is a silicon oxide (SiOx) material and the fifth dielectric layer is a silicon oxide (SiOx) material, where SiOx represents a material system and does not represent that the oxygen content of both the first dielectric layer and the fifth dielectric layer are the same.

And when in bonding, a dielectric layer (such as a first dielectric layer) in the photon integrated structure is adopted for bonding, so that an additional bonding structure is not required to be arranged on the photon integrated structure, and the process flow is reduced.

Fig. 6A shows a schematic view of the second side thinning and subsequent processing of the first substrate 201. In fig. 6A, the first substrate 201 may be thinned on the second side of the first substrate 201 of fig. 5 to form a corresponding through-substrate opening (Through sbustrate via), i.e., such that the second opening penetrates the first substrate, and correspondingly, the second conductive opening 204 penetrates the first substrate 201 to form a second conductive via. Optionally, a dielectric layer 207 is formed on the second side of the first substrate (see fig. 6A). The thinning process may be, for example, grinding, chemical mechanical polishing, etching, etc.

A photonic integrated circuit chip schematic is shown in fig. 6B after further formation of other connection structures. After fig. 6A, a rewiring layer (RDL) 208 is formed on the second side of the first substrate.

In addition, UBM may also be formed as needed so that UBM is electrically connected with rewiring layer 208. Conductive connections to UBM may be formed according to electrical connection requirements. The conductive connections may be controlled collapse chip connection (C4) bumps, ball Grid Array (BGA) connections, solder balls, metal pillars, micro bumps, etc. The conductive connection may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, the conductive connection may be formed by first forming a solder layer by conventional methods such as evaporation, electroplating, printing, and the like. In some embodiments, the conductive connection is a metal post, such as a copper post, formed by sputtering, electroplating, electroless plating, CVD, or the like.

As in fig. 7, a schematic diagram of fig. 6 with a portion of the photonic integrated structure removed is shown and may be used to form an edge coupler, which may include waveguide 1041. In some embodiments, the waveguide 1041 may act as a first waveguide, and the edge coupler may further comprise a second waveguide, the first waveguide being coupled to the second waveguide, and both the first waveguide and the second waveguide may have a tapered structure. The material of the waveguide may be, for example, silicon nitride.

In fig. 7, after removing a portion of the photonic integrated structure in fig. 6B, the sides of the photonic integrated structure form an optical coupling end 121. Wherein, the side surface of the photonic integrated structure where the optical coupling end 121 is located corresponds to the groove of the first substrate. An opening may be formed in the photonic integrated circuit by etching the first dielectric layer 102, the second dielectric layer 105 in fig. 6B, and a portion of the photonic integrated circuit structure may be removed, thereby exposing the sides of the optical coupling end 121 (as in fig. 7), wherein the opening may have a different shape as desired. The step of forming the opening may occur after removing the substrate 101, and thus, the substrate 101 may not have to be etched, reducing the difficulty and complexity of etching.

In some embodiments, other layers of material may be formed on the surface of the optical coupling end 121 as desired.

In some embodiments, as in fig. 7, the end of waveguide 1041 is exposed at the optical coupling end. In some embodiments, the end of waveguide 1041 is a distance from the side on which the optical coupling end is located. In some embodiments, waveguide 1041 acts as a first waveguide through which light is coupled to a second waveguide.

Wherein the optical coupling end 121 may correspondingly mount an optical Fiber, or an Array of optical Fibers (FA), to enable coupling of light into the photonic integrated circuit chip, wherein the grooves 211 may be used to accommodate the optical fibers/Array of optical fibers, or have sufficient space to accommodate an adhesive to bond the optical fibers or Array of optical fibers.

Because the photon integrated structure and the first substrate are manufactured separately, a proper groove can be conveniently formed in the first substrate, the photon integrated structure above the first substrate is not influenced, and the size of the formed groove can be conveniently controlled. In addition, the process is compatible with the process steps of manufacturing the conductive through holes, and the manufacturing process flow is optimized. Illustratively, by removing the initial substrate in the photonic integrated structure, the original oxide layer/insulating layer (buried oxide layer) of the SOI substrate in the photonic integrated structure may be used as a bonding layer, so that the bonding with the first substrate can be conveniently performed.

The photonic integrated structure and the first substrate may be fabricated separately such that the openings in the first substrate do not affect the photonic integrated structure. In addition, the openings of the first dielectric layer in the photonic integrated structure may be fabricated by a different process than the openings in the first substrate, or may have different dimensions, for example, the conductive openings in the photonic integrated structure that are electrically connected to the first substrate may have a smaller aperture than the first substrate via, thereby making the process easier to implement.

In fig. 8, a schematic diagram of a photonic integrated circuit chip is shown, which may be obtained by dicing the package structure formed by the photonic integrated circuit structure and the first substrate in fig. 7, through the recess 211 of the first substrate, for example along PP' in fig. 7.

In one exemplary embodiment, the present invention proposes a photonic integrated circuit chip, as shown in fig. 8, comprising: a first substrate 201 comprising a recess 211; a photonic integrated structure comprising an optical coupling end 121 located at a side of the photonic integrated circuit structure, the optical coupling end 121 enabling coupling of light from the side of the photonic integrated circuit into the photonic integrated circuit; wherein the side surface of the optical coupling end corresponds to the groove 211 of the first substrate 201.

In an exemplary embodiment, the side of the optical coupling end 121 is located at a distance L0 from the side of the recess of the first substrate 201, such that a cavity is located below the optical coupling end, for example, forming a receiving space.

In fig. 8, an exemplary photonic integrated circuit chip 800 includes a first substrate 201, a fifth dielectric layer 205, a first dielectric layer 102, a photonic device layer 104, a second dielectric layer 105, a third dielectric layer 106, and a fourth dielectric layer 107, which are disposed in this order.

The photonic integrated circuit chip 800 has a first surface (the upper surface of the photonic integrated circuit chip in fig. 8) and a second surface opposite the first surface, and the photonic integrated circuit includes a conductive path that passes through the photonic integrated circuit chip, the conductive path extending between the first surface and the second surface of the photonic integrated circuit chip, the conductive path passing through the first conductive aperture 112 and the second conductive aperture 204 in that order in a direction from the first surface to the second surface. In some embodiments, the conductive path passes through the first conductive aperture 112, the third conductive aperture 206, and the second conductive aperture 204 in that order in a direction from the first surface to the second surface.

Photonic integrated circuit chip 800 includes fifth dielectric layer 205 between the first dielectric layer and the third dielectric layer; the fifth dielectric layer 205 has a third opening that extends through the fifth dielectric layer and is aligned with the second opening; and forming a conductive material in the third opening such that the conductive material in the third opening is connected with the conductive material in the second opening, whereby the fifth dielectric layer 205 has a third conductive opening 206.

In fig. 9, a top view along the plane AA' of fig. 8 is shown, which mainly shows the general position of the waveguide 1041, with other structures omitted. Illustratively, the waveguide 1041 may be a waveguide having a tapered structure, such as a tapered waveguide, and illustratively, the width 1041 of the waveguide increases progressively from a side closer to the optical coupling end to a side farther from the optical coupling end. Illustratively, it can also be said that the waveguide 1041 becomes larger and smaller from the side closer to the optical coupling region to the side farther from the optical coupling end. In some embodiments, the edge coupler of the photonic integrated circuit chip may be accessed through an optical coupling end.

In an exemplary embodiment, a photonic integrated circuit chip package structure is provided, such as shown in fig. 10, in which a connector of an optical fiber array 300 is mounted on a photonic integrated circuit chip 800, and the photonic integrated circuit chip package structure may include an optical fiber (may be disposed in the optical fiber array 300, not shown) and the photonic integrated circuit chip 800, where the optical fiber is coupled to the optical coupling terminal. The fiber array 300 is disposed at the optical coupling end of the photonic integrated circuit chip 800 so that optical fibers (not shown) in the fiber array 300 can be optically coupled to the photonic integrated circuit chip. In an exemplary embodiment, the side where the optical coupling end 121 is located has a distance L0 from the side where the groove of the first substrate 201 is located, so that there is a receiving space thereunder. The package structure may include an adhesive, and the receiving space may be used, for example, to receive more adhesive, etc., to more easily secure the optical fibers (fiber array 300).

In some embodiments, the fiber array 300 may be replaced with other light sources, such as laser devices.

In some embodiments, as shown in FIG. 11, a top view along AA' in FIG. 8 is shown, primarily showing the general location of waveguide 1041, with other structures omitted. In fig. 11, it is shown that both sides of the waveguide 1041 are etched, so that the mode field of light can be limited, and the coupling propagation efficiency of light can be improved.

In some embodiments, as shown in fig. 12A, a first opening is formed in the first dielectric layer and further a first conductive opening 112 is formed prior to removing the backing substrate in the SOI substrate. After the step of fig. 1C, a step of forming a first opening in the first dielectric layer 102 may be included, and a conductive material is provided to form a first conductive opening 112 (fig. 12A), and the backing substrate 101 in the SOI substrate is removed in a subsequent step. Illustratively, after forming the second dielectric layer 105, as shown in fig. 12A, etching may be performed from the second dielectric layer 105 to the first dielectric layer 102 to form a first opening through the second dielectric layer, the first opening including a first portion of the first dielectric layer and a second portion of the second dielectric layer, a conductive material disposed in the first opening to form a first conductive opening 112, the first conductive opening 112 extending through the first dielectric layer to form a first conductive via.

Then, as shown in fig. 12B, a first conductive layer M1 may be formed on the second dielectric layer 105, and an electrical connection structure and other material layers or structures may be further formed as needed, thereby obtaining the structure in fig. 12B.

Removing the substrate 101 of fig. 12B may also be included such that the first conductive openings 112 are exposed. In a subsequent step, the photonic integrated structure after removal of the substrate 101 is bonded to a first substrate, resulting in a structure as in fig. 5.

In some embodiments, the order of fabrication of some materials or layers may be adjusted as desired. For example, pad 108 and UBM109 may be formed after the photonic integrated structure is bonded to the first substrate. Optionally, a second opening is formed in the first substrate through the first substrate prior to bonding the photonic integrated structure to the first substrate. Optionally, the RDL structure is formed on the second side of the first substrate prior to bonding the photonic integrated structure to the first substrate. Optionally, a rewiring layer may also be formed on the second side of the first dielectric layer of the photonic integrated structure before the photonic integrated structure is bonded to the first substrate, where (the conductive material of) the first conductive opening of the photonic integrated structure is electrically connected to (the conductive material of) the corresponding second conductive opening in the first substrate through the rewiring layer, and the first conductive opening and the second conductive opening do not need to be aligned during the electrical connection.

It will be appreciated by those skilled in the art that what has been disclosed is illustrative only and is not intended to limit the scope of the claimed invention, as the invention may be modified in equivalent ways to the embodiments described herein, but is also within the scope of the appended claims.

Claims

1. A method of fabricating a photonic integrated circuit chip, comprising:

providing a photonic integrated structure;

providing a first substrate, wherein the first substrate comprises a groove;

bonding the photonic integrated structure to the first substrate;

removing a portion of the photonic integrated structure to form an optical coupling end that enables coupling of light into the photonic integrated circuit chip from a side of the photonic integrated circuit;

the side surface of the photonic integrated structure, where the optical coupling end is located, corresponds to the groove of the first substrate.

2. The method for fabricating a photonic integrated circuit chip as recited in claim 1, comprising

In the step of providing a photonic integrated structure, the photonic integrated structure provided includes a first dielectric layer;

the step of providing a photonic integrated structure includes:

forming the photonic integrated structure based on an SOI substrate, wherein the SOI substrate comprises a back substrate, an insulating layer, and a top silicon, the first dielectric layer being from the insulating layer in the SOI substrate;

and removing the backing bottom.

3. The method of fabricating a photonic integrated circuit chip of claim 1, wherein after bonding the photonic integrated structure to the first substrate, a portion of the photonic integrated structure is removed to form the optical coupling end.

4. The method of fabricating a photonic integrated circuit chip of claim 1, wherein a portion of the photonic integrated structure is removed to form the optical coupling end prior to bonding the photonic integrated structure to the first substrate.

5. The method of fabricating a photonic integrated circuit chip as claimed in claim 3 or 4, wherein a portion of the photonic integrated structure is removed by etching to form an optical coupling end.

6. The method of fabricating a photonic integrated circuit chip of claim 1, further comprising: cutting the first substrate, wherein the first substrate passes through the grooves of the first substrate during cutting.

7. The method of fabricating a photonic integrated circuit chip as in any one of claims 1-3, 6, wherein the photonic integrated structure comprises a waveguide, the optical coupling end being capable of coupling light into the waveguide.

8. The method of fabricating a photonic integrated circuit chip as in claim 7, said removing a portion of the photonic integrated structure to form an optical coupling, wherein the removed portion includes portions on both sides of the waveguide.

9. The method of manufacturing a photonic integrated circuit chip as in any one of claims 1-3, 6, wherein the photonic integrated circuit chip comprises an edge coupler, the optical coupling end being capable of coupling light to the edge coupler.

10. The method for manufacturing a photonic integrated circuit chip as claimed in any one of claims 1 to 3, wherein,

in the step of providing a photonic integrated structure, the photonic integrated structure further includes: a first opening, and a conductive material disposed in the first opening;

in the step of providing a first substrate, the first substrate further includes: a second opening, and a conductive material disposed in the second opening;

in the step of bonding the photonic integrated structure to the first substrate, the first openings are aligned with the second openings, and the conductive material in the first openings is electrically connected with the conductive material in the corresponding second openings.

11. The method of fabricating a photonic integrated circuit chip of claim 9, comprising forming a fifth dielectric layer on a first side of the first substrate; and, in the step of bonding the photonic integrated structure to the first substrate, the fifth dielectric layer is positioned between the photonic integrated structure and the first substrate.

12. A photonic integrated circuit chip comprising:

a first substrate comprising a recess;

a photonic integrated structure comprising an optical coupling end at a side thereof, the optical coupling end enabling coupling of light from the side of the photonic integrated circuit chip into the photonic integrated circuit chip;

the side surface of the optical coupling end corresponds to the groove of the first substrate.

13. The photonic integrated circuit chip of claim 12, the photonic integrated circuit chip being obtained by bonding the photonic integrated structure to the first substrate.

14. The photonic integrated circuit chip of claim 13, the photonic integrated structure comprising a first dielectric layer; the first dielectric layer is from an insulating layer in an SOI substrate, and an original back substrate in the SOI substrate is removed, and the photonic integrated structure is bonded to the first substrate on a side where the back substrate is removed.

15. The photonic integrated circuit chip of any one of claims 12 to 14, the photonic integrated circuit comprising a waveguide, the optical coupling end configured to enable optical coupling to the waveguide.

16. The photonic integrated circuit chip of claim 15, wherein the photonic integrated structure comprises: a first opening, and a conductive material disposed in the first opening; a first substrate, the first substrate comprising: a second opening, and a conductive material disposed in the second opening; the first openings are aligned with the second openings, and the conductive material in the first openings is electrically connected with the conductive material in the corresponding second openings.

17. The photonic integrated circuit chip of any one of claims 12 to 14, wherein the photonic integrated circuit chip comprises an edge coupler, the optical coupling end being capable of coupling light to the edge coupler.

18. A package structure for a photonic integrated circuit chip, the package structure comprising the photonic integrated circuit chip as claimed in any one of claims 12-17, and

an optical fiber coupled to the optical coupling end.

19. The package structure of claim 18, wherein,

the photonic integrated circuit chip comprises an accommodating space below the photo-coupling end,

the packaging structure comprises an adhesive arranged in the accommodating space.