CN110854128B

CN110854128B - Array substrate

Info

Publication number: CN110854128B
Application number: CN201910999710.2A
Authority: CN
Inventors: 宋文清; 郭威宏; 陈铭耀; 黄国有
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2019-03-15
Filing date: 2019-10-21
Publication date: 2022-04-19
Anticipated expiration: 2039-10-21
Also published as: TW202036105A; CN110854128A; TWI696866B

Abstract

An array substrate comprises a substrate, a first active element arranged on the substrate and a first insulating layer arranged on the substrate. The first active device includes a first semiconductor layer, and a first source and a first drain electrically connected to the first semiconductor layer. The first insulating layer includes a first protrusion and a plurality of second protrusions. The vertical projection of the first protrusion on the substrate is partially overlapped with the vertical projection of the first drain on the substrate. The height of the second protrusions is greater than that of the first protrusions.

Description

Array substrate

Technical Field

The invention relates to an array substrate, and more particularly to an array substrate having a first protrusion and a second protrusion belonging to the same film layer.

Background

With the vigorous development of Display technology, Display panels (EPDs) such as Liquid Crystal Displays (LCDs), Light Emitting Diode displays (LEDs), Organic Light Emitting Diode displays (OLEDs), plasma displays (pdps) have gradually become the mainstream of future displays.

In recent years, in order to increase the pixel density and avoid misalignment (COA) caused when the Array substrate and the opposite substrate are assembled, a technique of directly forming a Color Filter layer on a thin film transistor Array substrate (COA) has been proposed. However, the process of integrating the color filter layer into the tft array substrate requires an additional mask for photolithography and etching. Therefore, the process steps are complicated, resulting in increased process time and high manufacturing cost.

Disclosure of Invention

The invention provides an array substrate, which can simplify the manufacturing process, reduce the manufacturing time, reduce the manufacturing cost and provide excellent display quality.

The array substrate comprises a substrate, a first active element arranged on the substrate and a first insulating layer arranged on the substrate. The first active device includes a first semiconductor layer, and a first source and a first drain electrically connected to the first semiconductor layer. The first insulating layer includes a first protrusion and a plurality of second protrusions. The first protrusion is disposed on the substrate. The vertical projection of the first protrusion on the substrate is partially overlapped with the vertical projection of the first drain on the substrate. The second protrusions are arranged on the substrate, wherein the height of the second protrusions is greater than that of the first protrusions.

In view of the above, the array substrate according to an embodiment of the invention can form the first insulating layer including the first protrusions and the second protrusions having different heights through a patterning process, so that the number of masks used in the manufacturing process can be reduced, and the effects of simplifying the manufacturing process, reducing the manufacturing time, and reducing the manufacturing cost can be achieved.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Drawings

Fig. 1 is a schematic top view of an array substrate according to an embodiment of the invention.

FIG. 2A is a schematic partial cross-sectional view taken along section line A-A' of FIG. 1.

FIG. 2B is a partial cross-sectional view taken along section line B-B' of FIG. 1.

FIG. 2C is a partial cross-sectional view of FIG. 1 taken along section line C-C'.

Fig. 3 is a partial cross-sectional view of an array substrate according to another embodiment of the invention.

Fig. 4 is a partial cross-sectional view of an array substrate according to another embodiment of the invention.

Fig. 5 is a partial cross-sectional view of an array substrate according to another embodiment of the invention.

Fig. 6 is a partial cross-sectional view of an array substrate according to still another embodiment of the invention.

Fig. 7A is a schematic top view of an array substrate according to another embodiment of the invention.

FIG. 7B is a partial cross-sectional view of FIG. 7A along section line D-D'.

Fig. 8 is a partial cross-sectional view of a display panel to which an array substrate according to an embodiment of the invention is applied.

Fig. 9 is a partial cross-sectional view of a display panel to which an array substrate according to another embodiment of the present invention is applied.

Wherein, the reference numbers:

1. 2: display panel

10. 10A, 10B, 10C, 10D, 10E: array substrate

100: substrate

110: shielding layer

120: insulating layer

130: gate insulating layer

132. 134, O1, O2: contact window

140: interlayer insulating layer

141: surface of

160. 160': a first insulating layer

162. 162': first protrusion

1621. 1641A, 1641A ', 1641B': the top surface

164: second protrusion

164A, 164A': first spacer

164B, 164B': second spacer

170. 170A, 170B: first conductive layer

172: second conductive layer

180: pixel electrode

191: first protective layer

192: second protective layer

260. 260A, 260B, 260C: a second insulating layer

262: opening of the container

263A, 263C: a first top surface

264A, 264B, 264C: second top surface

300: opposite substrate

310: first support

320. 320A: second support

A-A ', B-B', C-C ', D-D': section line

BM: light shielding layer

CH 1: first semiconductor layer

CH 2: a second semiconductor layer

CH 3: third semiconductor layer

CF: color filter layer

CF1, CF2, CF 3: color filter pattern

COM: common electrode layer

D1: a first drain electrode

D2: second drain electrode

DL: data line

G1: a first grid electrode

G2: second grid

H1, H2, H3: height

k1, k2, k 2': distance between two adjacent plates

LC: liquid crystal molecules

TFT 1: a first active element

TFT 2: second active element

TFT 3: third active element

S1: a first source electrode

S2: second source electrode

S3: third source electrode

SL: scanning line

Detailed Description

The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:

in the following description, for purposes of explanation, numerous implementation details are set forth in order to provide a thorough understanding of the various embodiments of the present invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such implementation details are not necessary. In addition, some conventional structures and elements are shown in simplified schematic form in the drawings.

In the drawings, the thickness of layers, films, panels, regions, etc. have been exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected" to another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Further, an "electrical connection" or "coupling" may be the presence of other elements between the two elements.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer" or "portion" discussed below could be termed a second element, component, region, layer or portion without departing from the teachings herein.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a schematic top view of an array substrate according to an embodiment of the invention. FIG. 2A is a schematic partial cross-sectional view taken along section line A-A' of FIG. 1. FIG. 2B is a partial cross-sectional view taken along section line B-B' of FIG. 1. FIG. 2C is a partial cross-sectional view of FIG. 1 taken along section line C-C'. Referring to fig. 1 and fig. 2A, in the present embodiment, the array substrate 10 may include a substrate 100, a first active device TFT1, and a first insulating layer 160, wherein the first insulating layer 160 includes a first protrusion 162 and a plurality of second protrusions 164. In addition, in the present embodiment, the array substrate 10 may further include a shielding layer 110, an insulating layer 120, a scan line SL, a data line DL, a gate insulating layer 130, an interlayer insulating layer 140, a third active device TFT3, a color filter layer CF, a light shielding layer BM, a second insulating layer 260, a common electrode layer COM, a first conductive layer 170, a second conductive layer 172, a first protective layer 191, a second protective layer 192, and a pixel electrode 180. For convenience of explanation and observation, fig. 1 schematically illustrates only some of the members, and the substrate 100, the insulating layer 120, the gate insulating layer 130, the interlayer insulating layer 140, the second insulating layer 260, the common electrode layer COM, the first protective layer 191, and the second protective layer 192 are not illustrated.

As shown in fig. 2A, the array substrate 10 includes a substrate 100. In the present embodiment, the material of the substrate 100 may be glass, quartz, organic polymer, or opaque/reflective material (e.g., conductive material, wafer, ceramic, or other suitable material), or other suitable material, which is not limited by the invention.

As shown in fig. 2A, an insulating layer 120 may be disposed on the substrate 100. In this embodiment, the insulating layer 120 is made of an inorganic material, an organic material, a combination of the above materials, or another suitable material. Such inorganic materials are for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the foregoing materials. Examples of such organic materials are (but not limited to): polyimide resin, epoxy resin, acrylic resin, or the like.

As shown in fig. 1 and 2A, the shielding layer 110 may be disposed on the substrate 100 between the substrate 100 and the insulating layer 120. In the present embodiment, the material of the shielding layer 110 includes, for example, metal, resin, graphite, or other suitable material. The shielding layer 110 can improve the problem of light leakage generated by the first active device TFT1, but the invention is not limited thereto.

In this embodiment, the first active device TFT1, the scan line SL and the data lines DL are disposed on the substrate 100. It should be noted that fig. 1 is a partial top view of the array substrate 10, which only schematically illustrates one first active device TFT1 and one scan line SL crossing two data lines DL, but the invention is not limited thereto. It should be understood by one of ordinary skill in the art that the number of the first active devices TFT1, the scan lines SL and the data lines DL is set according to the user's requirement, and is not limited to the number shown in fig. 1. The first active device TFT1 is electrically connected to a scan line SL and a data line DL, respectively. In detail, as shown in fig. 1 and 2A, the first active device TFT1 includes a first semiconductor layer CH1, and a first source S1 and a first drain D1 electrically connected to the first semiconductor layer CH 1. The first active device TFT1 also includes a first gate G1. As shown in fig. 1, 2B and 2C, in a direction perpendicular to the substrate 100, the first gate G1 overlaps the first semiconductor layer CH1, and the gate insulating layer 130 is sandwiched between the first gate G1 and the first semiconductor layer CH 1. The first gate G1 is electrically connected to the scan line SL and belongs to the same layer, but the invention is not limited thereto. As shown in fig. 2A, 2B and 2C, an interlayer insulating layer 140 is disposed on the gate insulating layer 130. The first source S1 and the first drain D1 are disposed on the interlayer insulating layer 140. As shown in fig. 1 and fig. 2C, the first source S1 is electrically connected to the data line DL and belongs to the same layer, but the invention is not limited thereto. The first source S1 is electrically connected to the first semiconductor layer CH1 through the contact 134. The first drain D1 is electrically connected to the first semiconductor layer CH1 through the contact hole 132. In the present embodiment, the first source S1, the first drain D1 and the data line DL belong to the same layer, but the invention is not limited thereto.

In this embodiment, the first active device TFT1 is illustrated as a top gate thin film transistor (top gate TFT), but the present invention is not limited thereto. According to other embodiments, the first active device TFT1 may also be a bottom gate Thin Film Transistor (TFT) or other suitable TFT. In this embodiment, the first active device TFT1 is, for example, a low temperature polysilicon thin film transistor (LTPS) or an amorphous silicon thin film transistor (a-Si), but the invention is not limited thereto.

Referring to fig. 1 and fig. 2A, the scan lines SL and the data lines DL are disposed alternately and on different planes. As shown in fig. 2A, the scan line SL is disposed between the gate insulating layer 130 and the interlayer insulating layer 140. The data line DL is disposed on the surface 141 of the interlayer insulating layer 140. In the present embodiment, the scan line SL, the data line DL, the first gate G1, the first source S1 and the first drain D1 are made of metal materials for conductivity, but the invention is not limited thereto.

In this embodiment, the color filter layer CF is disposed on the substrate 100. As shown in fig. 1, 2A, 2B and 2C, the color filter layer CF may include a color filter pattern CF1, a color filter pattern CF2 and a color filter pattern CF 3. The color filter patterns CF1, CF2, CF3 are disposed on the interlayer insulating layer 140. In other words, the array substrate 10 applies a technology of directly integrating the color filter pattern into a pixel array (COA). As shown in fig. 1, the color filter pattern CF1 may be disposed corresponding to the first active element TFT 1. The color filter pattern CF2 may be disposed at the right of the color filter pattern CF1, and the color filter pattern CF3 may be disposed at the left of the color filter pattern CF1, but the invention is not limited thereto. As shown in fig. 1, fig. 2A, fig. 2B and fig. 2C, the color filter patterns CF1, CF2 and CF3 may partially overlap the shielding layer 110, the scan line SL and the data line DL in a direction perpendicular to the substrate 100, but the invention is not limited thereto.

In the present embodiment, the color filter patterns CF1, CF2, and CF3 may correspond to different colors of light, respectively, but the invention is not limited thereto. In detail, the color filter pattern CF1 may correspond to red, green, blue, yellow, white or other colors of light. The color filter pattern CF2 may correspond to red, green, blue, yellow, white, or other colors of light. The color filter pattern CF3 may correspond to red, green, blue, yellow, white, or other colors of light. In some embodiments, the color filter patterns CF1, CF2, CF3 may also partially correspond to the same color light or all correspond to the same color light.

In the present embodiment, the light-shielding layer BM is provided corresponding to the boundary between the color filter patterns CF1, CF2, and CF 3. In the present embodiment, the light-shielding layer BM is disposed on the color filter layer CF as shown in fig. 1, but the present invention is not limited thereto. In other embodiments, the light-shielding layer BM may be disposed under the color filter layer CF. As shown in fig. 1 and 2C, the light-shielding layer BM partially overlaps the data line DL in a direction perpendicular to the substrate 100. In this embodiment, the material of the light-shielding layer BM may include metal, resin, graphite, or other suitable materials, but the invention is not limited thereto. In this embodiment, as shown in fig. 1, the color filter layer CF and the light-shielding layer BM only partially overlap the shielding layer 110 and do not overlap the first source S1 and the first drain D1 in a direction perpendicular to the substrate 100. As such, the first drain D1 may be electrically connected to the pixel electrode 180 (described in detail later).

As shown in fig. 1 and 2A, the first insulating layer 160 is disposed on the surface 141 of the interlayer insulating layer 140. The first insulating layer 160 includes a first protrusion 162 and a plurality of second protrusions 164. In other words, the first protrusions 162 and the second protrusions 164 belong to the same film layer. In this embodiment, the first protrusions 162 and the plurality of second protrusions 164 of the first insulating layer 160 correspondingly overlap the shielding layer 110 in a direction perpendicular to the substrate 100. The first protrusions 162 are disposed corresponding to the first drain electrodes D1, and the second protrusions 164 are disposed corresponding to the data lines DL, respectively. In other words, the vertical projection of the first protrusion 162 on the substrate 100 partially overlaps the vertical projection of the first drain D1 on the substrate 100. The vertical projection of the second protrusion 164 on the substrate 100 partially overlaps the vertical projection of the data line DL on the substrate 100. On the other hand, as shown in fig. 1 and fig. 2A, in the direction perpendicular to the substrate 100, the first protrusion 162 completely overlaps the contact window 132 and is disposed on the first drain D1, and the vertical projection of the first protrusion 162 on the substrate 100 is located within the vertical projection of the first drain D1 on the substrate 100, so that a portion of the first drain D1 is exposed. However, the invention is not limited thereto, and in some embodiments, the first protrusion 162 may not completely overlap the contact 132 but only partially overlap the contact 132 in a direction perpendicular to the substrate 100. Thus, more of the first drain D1 may be exposed, and the contact area between the first drain D1 and the first conductive layer 170 (described in detail later) may be increased.

In the present embodiment, the first protrusions 162 and the second protrusions 164 are defined by the same patterning process. In detail, a first insulating material (not shown) may be formed on the surface 141 of the interlayer insulating layer 140 after the patterning process of the data line DL and the first drain electrode D1 is completed. The first insulating material may overlap the shielding layer 110 in a direction perpendicular to the substrate 100, but the invention is not limited thereto. In this embodiment, the forming method of the first insulating material may include a Physical Vapor Deposition (PVD) method or a Chemical Vapor Deposition (CVD) method, but the invention is not limited thereto. In this embodiment, the material of the first insulating material includes, for example, a photoresist material. The first insulating material may then be used as a mask for photolithography by using a Half Tone Mask (HTM), a phase shift mask (phase shift mask), or a gray tone mask (gray tone mask). In this way, the first insulating material can be patterned to form the first insulating layer 160 having the first protrusions 162 and the second protrusions 164. In other words, the first bump 162 and the second bump 164 belong to the same layer (both belong to the first insulating layer 160) and can be defined by the same mask. Therefore, in the manufacturing process of the array substrate 10, the number of masks used can be reduced, so that the manufacturing process can be simplified, the manufacturing time can be reduced, and the manufacturing cost can be reduced.

As shown in fig. 1 and 2A, the first conductive layer 170 is disposed on the interlayer insulating layer 140 and covers the first protrusion 162 and a portion of the first drain D1 (e.g., a portion of the first drain D1 that does not overlap the first protrusion 162). Thus, the first conductive layer 170 is electrically connected to the first drain D1, and the first conductive layer 170 can extend along the first protrusion 162 to a higher topography. In other words, the first conductive layer 170 and the first protrusion 162 together form a higher topography on the interlayer insulating layer 140. In this embodiment, the material of the first conductive layer 170 may include a metal material or a transparent conductive material, but the invention is not limited thereto.

In this embodiment, the plurality of second protrusions 164 may be disposed on opposite sides of the first protrusion 162, respectively. As shown in fig. 1 and 2A, the second protrusions 164 may include first spacers 164A and second spacers 164B. The first spacer 164A is disposed on the right side of the first protrusion 162, for example, and the second spacer 164B is disposed on the left side of the first protrusion 162, for example, but the invention is not limited thereto. As shown in fig. 1, 2A and 2C, the first spacer 164A is disposed on the data line DL on the right side of the first protrusion 162, and overlaps the data line DL, the first semiconductor layer CH1 and the first source S1 in a direction perpendicular to the substrate 100. In other words, the first spacer 164A may be disposed corresponding to the first active device TFT 1. As shown in fig. 1 and 2A, the second spacer 164B is disposed on the data line DL on the left side of the first protrusion 162, and overlaps the data line DL, the third semiconductor layer CH3 and the third source S3 in a direction perpendicular to the substrate 100. The third semiconductor layer CH3 and the third source S3 are part of the third active device TFT3, and the third active device TFT3 is disposed corresponding to the third color filter pattern CF 3. The third active device TFT3 is similar to the first active device TFT1, and therefore the description thereof is omitted here. Based on the foregoing description of the first active element TFT1, it should be understood by one of ordinary skill in the art that the third active element TFT3 includes a gate and a drain not disclosed in fig. 1. In another aspect, the second spacer 164B may be disposed corresponding to the third active device TFT3 and adjacent to the first active device TFT1, but the invention is not limited thereto.

As shown in fig. 2A, the first spacers 164A and the second spacers 164B have the same height H2. In other words, in the present embodiment, the plurality of second protrusions 164 have the same height H2. Herein, the height H2 of the first spacer 164A may be defined as the distance between the surface 141 of the interlayer insulating layer 140 to the top surface 1641A of the first spacer 164A. Likewise, the height H2 of the second spacer 164B may be defined as the distance between the surface 141 of the interlayer insulating layer 140 to the top surface 1641B of the second spacer 164B. From another point of view, in the present embodiment, the top surface 1641A of the first spacer 164A is aligned with the top surface 1641B of the second spacer 164B.

As shown in fig. 2A, the height H2 of the first spacers 164A and the second spacers 164B (i.e., the second protrusions 164) is greater than the height H1 of the first protrusions 162. Herein, the height H1 of the first protrusion 162 may be defined as a distance between the surface 141 of the interlayer insulating layer 140 to the top surface 1621 of the first protrusion 162. In this way, when the array substrate 10 is assembled into a display panel, the second protrusions 164 having a higher height than the first protrusions 162 can function to provide a supporting function and maintain a liquid crystal gap (cell gap), but the invention is not limited thereto.

In this embodiment mode, the second insulating layer 260 may be provided over the entire surface of the substrate 100. As shown in fig. 2A, the second insulating layer 260 is disposed on the interlayer insulating layer 140 and covers the first protrusion 162 and the first conductive layer 170. In addition, as shown in fig. 2A, the second protrusions 164 protrude from the second insulating layer 260. In other words, in this embodiment mode, the top surface 1641A of the first spacer 164A is higher than the surface of the second insulating layer 260, and the top surface 1641B of the second spacer 164B is higher than the surface of the second insulating layer 260. As shown in fig. 2A, 2B and 2C, the second insulating layer 260 may further cover the color filter patterns CF1, CF2 and CF 3. From another perspective, the color filter layer CF (including the color filter patterns CF1, CF2, CF3) is disposed between the substrate 100 and the second insulating layer 260. In this embodiment, a method for forming the second insulating layer 260 includes a Physical Vapor Deposition (PVD) method or a Chemical Vapor Deposition (CVD) method, but the invention is not limited thereto. In this embodiment, the material of the second insulating layer 260 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, photoresist material, or other suitable materials.

As shown in fig. 1, 2A, 2B and 2C, the second insulating layer 260 has an opening 262. In this embodiment, a vertical projection of the opening 262 on the substrate 100 overlaps a vertical projection of the first protrusion 162 on the substrate 100. Thus, the opening 262 may expose the first conductive layer 170 on the top surface 1621 of the first protrusion 162. In some embodiments, the vertical projection of the opening 262 on the substrate 100 may only partially overlap the vertical projection of the first protrusion 162 on the substrate 100. It should be understood by one skilled in the art having referred to the above embodiments that the layout of the opening 262 is not limited to fig. 1 and fig. 2A to 2C, as long as the opening 262 can expose the first conductive layer 170 to electrically connect the first drain electrode D1 with the pixel electrode 180 (described in detail later), which falls into the scope of the present invention. In the present embodiment, the forming method of the opening 262 may include patterning the second insulating layer 260 by photolithography, half tone mask process, phase transfer mask process or gray tone mask process. When the opening 262 is formed by a half-tone mask process, a phase-shift mask process or a gray-tone mask process, the second insulating layer 260 can be formed as described above with reference to the first insulating layer 160, and thus, the description thereof is omitted. In addition, in the process of forming the opening 262, a portion of the second insulating layer 260 corresponding to the second protrusion 164 may be removed together, so that the second protrusion 164 protrudes from the second insulating layer 260.

In this embodiment, the second conductive layer 172 is disposed on the second insulating layer 260. As shown in fig. 1, fig. 2A and fig. 2B, in the direction perpendicular to the substrate 100, the second conductive layer 172 overlaps the first protrusion 162 and is located between the first spacer 164A and the second spacer 164B. In addition, the second conductive layer 172 partially overlaps the shielding layer 110 and the color filter layer CF in a direction perpendicular to the substrate 100. It should be noted that, in fig. 1, only one second conductive layer 172 is shown to be disposed corresponding to the color filter pattern CF1 for clarity and convenience of illustration. It should be understood by one of ordinary skill in the art that the second conductive layer 172 may also be disposed corresponding to the color filter patterns CF2 and CF3, which is not limited to the illustration of fig. 1.

As shown in fig. 2A, the second conductive layer 172 is electrically connected to the first conductive layer 170 through the opening 262. As described above, the first conductive layer 170 electrically connected to the first drain D1 can extend along the first protrusion 162 to a higher position, so that the first protrusion 162 serves as a landing structure for the first conductive layer 170, such that the first conductive layer 170 extends from the first drain D1 to the second conductive layer 172. From another perspective, the second conductive layer 172 is electrically connected to the first drain D1 through the first conductive layer 170 to receive a voltage or a driving signal from the first active device TFT 1. In this embodiment, the material of the second conductive layer 172 includes a transparent conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or other suitable oxide, or a stacked layer of at least two of the foregoing, but the invention is not limited thereto.

As shown in fig. 2A and 2B, the common electrode layer COM is disposed on the second insulating layer 260. As shown in fig. 2A and 2B, in the direction perpendicular to the substrate 100, the common electrode layer COM corresponds to and overlaps the color filter layer CF (including the color filter patterns CF1, CF2, and CF3), but does not overlap the first conductive layer 170, the first protrusions 162, and the second protrusions 164. The common electrode layer COM partially overlaps the second conductive layer 172, the data line DL, and the scan line SL. As shown in fig. 2B, the common electrode layer COM overlaps the second conductive layer 172 in a direction perpendicular to the substrate 100, and the first protective layer 191 is interposed between the common electrode layer COM and the second conductive layer 172. In this embodiment, the material of the first protection layer 191 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials. Thus, a storage capacitor (storage capacitor) is formed between the second conductive layer 172 and the common electrode layer COM. In other words, the second conductive layer 172, the first protection layer 191 and the common electrode layer COM form a structure of a storage capacitor. Thus, the performance and display quality of the array substrate 10 can be improved.

In this embodiment, the pixel electrode 180 is disposed on the common electrode layer COM. As shown in fig. 2A and 2B, a second protective layer 192 is interposed between the pixel electrode 180 and the common electrode layer COM. In detail. The second passivation layer 192 is disposed on the first passivation layer 191, and the second passivation layer 192 may cover the common electrode layer COM. In other words, the common electrode layer COM is located between the first protective layer 191 and the second protective layer 192. The second protection layer 192 is located between the common electrode layer COM and the pixel electrode 180. Thereby, the common electrode layer COM can be separated from the pixel electrode 180. In this embodiment, the material of the second protection layer 192 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials. In this embodiment mode, the material of the second protective layer 192 and the material of the first protective layer 191 may be the same or different.

As shown in fig. 2A, the first passivation layer 191 and the second passivation layer 192 respectively have a contact O1 and a contact O2. The contact windows O1 and O2 may overlap the second conductive layer 172 and the opening 262 in a direction perpendicular to the substrate 100. The formation method of the contact holes O1 and O2 includes, for example, performing a photolithography process on the first passivation layer 191 and the second passivation layer 192. In addition, as shown in fig. 2A, the first protective layer 191 and the second protective layer 192 do not cover the top surface 1641A of the first spacers 164A and the top surface 1641B of the second spacers 164B. In other words, the second protrusions 164 protrude from the first passivation layer 191 and the second passivation layer 192. In addition, in the process of forming the contact O1, a portion of the first protection layer 191 corresponding to the second bump 164 may be removed together, so that the second bump 164 protrudes from the first protection layer 191. Similarly, in the process of forming the contact O2, a portion of the second passivation layer 192 corresponding to the second protrusion 164 may be removed, so that the second protrusion 164 protrudes from the second passivation layer 192. However, the present invention is not limited thereto. In other embodiments, the first protective layer 191 and the second protective layer 192 may cover the

top surfaces

1641A and 1641B of the first spacers 164A and the second spacers 164B.

In this embodiment, as shown in fig. 1 and 2B, the pixel electrode 180 can be electrically connected to the second conductive layer 172 through the contact O2 of the second passivation layer 192 and the contact O1 of the first passivation layer 191. As described above, the second conductive layer 172 is electrically connected to the first drain D1 through the first conductive layer 170, so that the pixel electrode 180 is electrically connected to the first drain D1 through the second conductive layer 172 and the first conductive layer 170 to receive a voltage or a driving signal from the first active device TFT 1. Under the above arrangement, a driving electric field can be generated between the common electrode COM and the pixel electrode 180. That is, the array substrate 10 may drive the liquid crystal using a Fringe Field Switching (FFS) technique or an In-Plane-Switching (IPS) technique. However, the invention is not limited thereto. In other embodiments, the array substrate 10 may drive liquid crystal using Twisted Nematic (TN) technology. In other words, the array substrate 10 is, for example, an active device array substrate (active device array substrate) of a Liquid Crystal Display (LCD), but the invention is not limited thereto. In this embodiment, the material of the common electrode layer COM and the pixel electrode 180 includes a transparent conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or other suitable oxide, or a stacked layer of at least two of the foregoing, but the invention is not limited thereto.

As described above, the first conductive layer 170 electrically connected to the first drain D1 can extend along the first protrusion 162 to a higher topography, and the pixel electrode 180 is electrically connected to the first drain D1 through the second conductive layer 172 and the first conductive layer 170, so that the pixel electrode 180 can be electrically connected to the first drain D1 through a higher topography in the array substrate 10. Therefore, the pixel electrode 180 can be prevented from being chipped or broken during the formation process. From another point of view, in the present embodiment, the first protrusion 162 may serve as a bonding structure for electrically connecting the pixel electrode 180 to the first drain electrode D1.

In some embodiments, the array substrate 10 may not include the second conductive layer 172. At this time, the pixel electrode 180 may be electrically connected to the first conductive layer 170 through the contact O1, the contact O2 and the opening 262 to receive a voltage or a driving signal from the first active device TFT 1.

It should be noted that, since the array substrate 10 may be formed by a patterning process to form the first insulating layer 160 including the first protrusions 162 and the second protrusions 164 having different heights, the number of masks used in the manufacturing process of the array substrate 10 may be reduced, thereby achieving the effects of simplifying the manufacturing process, reducing the manufacturing time, and reducing the manufacturing cost.

In addition, in the array substrate 10, the second protrusions 164 may function as spacers, and the first protrusions 162 belonging to the same layer as the second protrusions 164 may provide a higher topography and serve as a bonding structure for electrically connecting the pixel electrode 180 to the first drain D1, so as to prevent the pixel electrode 180 from being chipped or broken during the formation process. Thus, the array substrate 10 not only has the advantages of simplifying the manufacturing process, reducing the manufacturing time and reducing the manufacturing cost, but also is suitable for the COA technology.

The following embodiments follow the reference numerals and part of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the parts with the same technical contents omitted can refer to the foregoing embodiments, and will not be repeated in the following embodiments.

Fig. 3 is a partial cross-sectional view of an array substrate according to another embodiment of the invention. The array substrate 10A shown in this embodiment is similar to the array substrate 10 shown in fig. 2A, and the main difference is that: the height H3 of the second spacers 164B 'is greater than the height H2 of the first spacers 164A'. In detail, the height H2 of the first spacer 164A ' may be defined as the distance between the surface 141 of the interlayer insulating layer 140 and the top surface 1641A ' of the first spacer 164A '. The height H3 of the second spacer 164B ' may be defined as a distance between the surface 141 of the interlayer insulating layer 140 to the top surface 1641B ' of the second spacer 164B '. In other words, as shown in fig. 3, the first spacers 164A 'and the second spacers 164B' have different heights. From another point of view, in the present embodiment, the top surface 1641A 'of the first spacer 164A' is not aligned with the top surface 1641B 'of the second spacer 164B'. Under the above arrangement, the first spacer 164A 'may be used as a secondary spacer, and the second spacer 164B' may be used as a primary spacer, but the invention is not limited thereto. In addition, the heights H2 and H3 of the first spacers 164A 'and the second spacers 164B' are both greater than the height H1 of the first protrusion 162. Thus, the array substrate 10A can achieve similar technical effects as those of the above embodiments. For the rest, please refer to the foregoing embodiments, which are not described herein.

Fig. 4 is a partial cross-sectional view of an array substrate according to another embodiment of the invention. The array substrate 10B shown in this embodiment is similar to the array substrate 10 shown in fig. 2A, and the main difference is that: the second insulating layer 260A may cover the first spacers 164A and the second spacers 164B in addition to the first protrusions 162. In this embodiment, the second insulating layer 260 has a first top surface 263A corresponding to the first spacer 164A and a second top surface 264A corresponding to the second spacer 164B in a direction perpendicular to the substrate 100. As shown in fig. 4, the distance k1 between the first top surface 263A and the first spacer 164A is the same as the distance k2 between the second top surface 264A and the second spacer 164B. In detail, the distance k1 can be defined as the distance from the first top surface 263A to the top surface 1641A of the first spacer 164A in the direction perpendicular to the substrate 100. The distance k2 can be defined as the distance from the second top surface 264A to the top surface 1641B of the second spacers 164B in the direction perpendicular to the substrate 100. From another perspective, in the present embodiment, the first top surface 263A is aligned with the second top surface 264A. Thus, the array substrate 10B can achieve similar technical effects as those of the above embodiments. For the rest, please refer to the foregoing embodiments, which are not described herein.

Fig. 5 is a partial cross-sectional view of an array substrate according to another embodiment of the invention. The array substrate 10C shown in this embodiment is similar to the array substrate 10B shown in fig. 4, and the main difference is that: the distance k1 between the first top surface 263A and the first spacer 164A corresponding to the overlapping first spacer 164A and the distance k 2' between the second top surface 264B and the second spacer 164B corresponding to the overlapping second spacer 164B are different. In detail, the distance k1 can be defined as the distance from the first top surface 263A to the top surface 1641A of the first spacer 164A in the direction perpendicular to the substrate 100. The distance k 2' may be defined as the distance from the second top surface 264B to the top surface 1641B of the second spacer 164B in the direction perpendicular to the substrate 100. From another perspective, in the present embodiment, the first top surface 263A and the second top surface 264B are not aligned. Under the above arrangement, even though the heights of the first spacer 164A and the second spacer 164B are the same, the first spacer 164A can still function as a secondary spacer through the second insulating layer 260B. The second spacer 164B may function as a main spacer through the second insulating layer 260B, but the invention is not limited thereto. Thus, the array substrate 10C can achieve similar technical effects as those of the above embodiments. For the rest, please refer to the foregoing embodiments, which are not described herein.

Fig. 6 is a partial cross-sectional view of an array substrate according to still another embodiment of the invention. The array substrate 10D shown in this embodiment is similar to the array substrate 10A shown in fig. 3, and the main difference is that: the second insulating layer 260C may cover the first spacers 164A 'and the second spacers 164B'. In this embodiment, the second insulating layer 260C has a first top surface 263C corresponding to the first spacer 164A 'and a second top surface 264C corresponding to the second spacer 164B' in a direction perpendicular to the substrate 100. As shown in fig. 6, the distance k1 between the first top surface 263C and the first spacer 164A 'and the distance k2 between the second top surface 264C and the second spacer 164B' are the same. In detail, the distance k1 can be defined as the distance from the first top surface 263C to the top surface 1641A 'of the first spacer 164A' in the direction perpendicular to the substrate 100. The distance k2 can be defined as the distance from the second top surface 264C to the top surface 1641B 'of the second spacer 164B' in the direction perpendicular to the substrate 100. From another point of view, in the present embodiment, the first spacer 164A 'and the second spacer 164B' have different heights, and the first top surface 263C and the second top surface 264C are located on different horizontal planes. The first top surface 263C is not aligned with the second top surface 264C. Under the above arrangement, even if the second insulating layer 260C is disposed on the first spacer 164A 'and the second spacer 164B' having different heights, respectively, the first spacer 164A can be used as a secondary spacer. The second spacer 164B may be used as a main spacer, but the invention is not limited thereto. Thus, the array substrate 10D can achieve similar technical effects as those of the above embodiments. For the rest, please refer to the foregoing embodiments, which are not described herein.

Fig. 7A is a schematic top view of an array substrate according to another embodiment of the invention. FIG. 7B is a partial cross-sectional view of FIG. 7A along section line D-D'. For convenience of explanation and observation, fig. 7A schematically illustrates only some of the members, and the substrate 100, the insulating layer 120, the gate insulating layer 130, the interlayer insulating layer 140, the second insulating layer 260, the common electrode layer COM, the first protective layer 191, and the second protective layer 192 are not illustrated. The array substrate 10E shown in this embodiment is similar to the array substrate 10 shown in fig. 1, and the main difference is that: the second active device TFT2 is disposed on the substrate 100 and adjacent to the first active device TFT 1. In detail, as shown in fig. 7A and 7B, the second active device TFT2 is disposed on the right side of the first active device TFT1 and is disposed corresponding to the color filter pattern CF2, but the invention is not limited thereto. In this embodiment, a vertical projection of the first protrusion 162 'of the first insulating layer 160' on the substrate 100 partially overlaps a vertical projection of at least one of the data lines DL on the substrate 100. Thereby, the first protrusion 162' may cross the data line DL and overlap the first drain electrode D1 of the first active device TFT1 and the second drain electrode D2 of the second active device TFT2 at the same time.

As shown in fig. 1 and fig. 7A, the second active device TFT2 and the first active device TFT1 are similar in material and structure, and therefore are not described in detail. In brief, the second active device TFT2 and the first active device TFT1 may be electrically connected to the same scan line SL. The second active device TFT2 and the first active device TFT1 are electrically connected to different data lines DL, respectively. The second active device TFT2 includes a second gate G2, a second semiconductor layer CH2, and a second source S2 and a second drain D2 electrically connected to the second semiconductor layer CH 2. As shown in fig. 7A and 7B, the second gate electrode G2 overlaps the second semiconductor layer CH2, and the gate insulating layer 130 is interposed between the second gate electrode G2 and the second semiconductor layer CH 2. The second gate G2 is electrically connected to the scan line SL and belongs to the same layer, but the invention is not limited thereto. The second source S2 and the second drain D2 are located on the interlayer insulating layer 140. The second source S2 is electrically connected to the data line DL and belongs to the same layer, but the invention is not limited thereto.

As shown in fig. 7A and 7B, the first protrusion 162' is disposed across the data line DL and overlaps the drains D1 and D2 of the adjacent two active devices TFT1 and TFT 2. In detail, a vertical projection of the first protrusion 162' on the substrate 100 partially overlaps a vertical projection of the first drain D1 of the first active device TFT1 on the substrate 100 and a vertical projection of the second drain D2 of the second active device TFT2 on the substrate 100. In addition, as shown in fig. 7A and 7B, in the direction perpendicular to the substrate 100, the first protrusion 162' partially overlaps the contact 132 corresponding to the first drain D1 and partially overlaps the contact 132 corresponding to the second drain D2, but the invention is not limited thereto. In other embodiments, the first protrusion 162' may completely overlap the contact 132 corresponding to the first drain D1 and completely overlap the contact 132 corresponding to the second drain D2 in a direction perpendicular to the substrate 100. In the embodiment, the first protrusion 162' partially overlaps the contact window 134 and is disposed on the first source S1, but the invention is not limited thereto.

In this embodiment, the adjacent first

conductive layers

170A and 170B may be disposed on the same first protrusion 162'. As shown in fig. 7A and 7B, the first conductive layer 170A corresponding to the first active device TFT1 is disposed on the interlayer insulating layer 140, and covers a portion of the first protrusion 162' and a portion of the first drain electrode D1. Similarly, the first conductive layer 170B corresponding to the second active device TFT2 covers a portion of the first protrusion 162' and a portion of the second drain electrode D2. Under the above arrangement, the first conductive layer 170A and the first conductive layer 170B can extend along the first protrusions 162' to a higher topography. In other words, the first conductive layer 170A, the first conductive layer 170B and the first protrusion 162' together form a higher topography on the interlayer insulating layer 140.

In this embodiment, the first conductive layer 170A may be electrically connected to the first drain D1, and the first conductive layer 170B may be electrically connected to the second drain D2. As shown in fig. 7A and 7B, the second conductive layer 172 is electrically connected to the first conductive layer 170A and the first conductive layer 170B through the opening 262. As described above, the first conductive layer 170A electrically connected to the first drain D1 and the first conductive layer 170B electrically connected to the second drain D2 can extend along the first protrusion 162 'to a higher position, so that the first protrusion 162' serves as a bridging structure for the first conductive layer 170A and the first conductive layer 170B, such that the first conductive layer 170A extends from the first drain D1 (the first conductive layer 170B extends from the second drain D2) to the second conductive layer 172. From another perspective, the second conductive layer 172 is electrically connected to the first drain D1 through the first conductive layer 170A (electrically connected to the second drain D2 through the first conductive layer 170B). In other words, the first protrusion 162' may be shared by the first conductive layer 170A and the first conductive layer 170B disposed adjacently, but the invention is not limited thereto. Therefore, the first protrusions 162' can be applied to the array substrate 10E with high resolution requirements, thereby improving performance and display quality. In some embodiments, the first protrusion 162' may also overlap more data lines DL, shared by three, four or more adjacent first conductive layers 170A. Therefore, the manufacturing process can be further simplified, the manufacturing time can be reduced, and the manufacturing cost can be reduced.

In addition, as shown in fig. 7A, the color filter layer CF and the light-shielding layer BM do not overlap the shielding layer 110 and the scan line SL, but the invention is not limited thereto. As shown in fig. 7A and 7B, a plurality of second protrusions 164 may be correspondingly disposed to overlap the data lines DL and the scan lines SL, but the invention is not limited thereto. In addition, as shown in fig. 7B, the first protective layer 191 and the second protective layer 192 cover the second bump 164, but the invention is not limited thereto. In another aspect, in the present embodiment, the second protrusions 164 do not protrude from the first passivation layer 191 and the second passivation layer 192. Thus, the array substrate 10E can achieve similar technical effects as those of the above embodiments. For the rest, please refer to the foregoing embodiments, which are not described herein.

Fig. 8 is a partial cross-sectional view of a display panel to which an array substrate according to an embodiment of the invention is applied. Referring to fig. 1 and 8, in the present embodiment, the display panel 1 includes an opposite substrate 300 disposed opposite to the array substrate 10, in addition to the array substrate 10 shown in fig. 1 and 2A. In the present embodiment, the material of the opposite substrate 300 may be glass, quartz, organic polymer, or other applicable materials, which is not limited by the invention. In some embodiments, the liquid crystal molecules LC may be further included between the array substrate 10 and the opposite substrate 300, but the invention is not limited thereto. In other words, the display panel 1 is, for example, a liquid crystal display panel, but the invention is not limited thereto.

In the present embodiment, the opposite substrate 300 is provided with a first supporter 310 and a second supporter 320. The first supports 310 are disposed corresponding to the first spacers 164A, and the second supports 320 are disposed corresponding to the second spacers 164B. In the present embodiment, the first supporter 310 and the second supporter 320 have different thicknesses. Specifically, the thickness of the second supporter 320 is greater than that of the first supporter 310. In another aspect, the display panel 1 is, for example, a spacer (PS) disposed on the opposite substrate 300. As shown in fig. 8, in the direction perpendicular to the substrate 100, the first supports 310 overlap the first spacers 164A, and the second supports 320 overlap the second spacers 164B. The second spacers 164B may abut against the second supports 320 to provide the required support and liquid crystal gap for the display panel 1. The first spacers 164A do not abut against the first supporting member 310, but the invention is not limited thereto. In some embodiments, the first spacer 164A and the second spacer 164B may both abut against the first support 310 and the second support 320, respectively. In other embodiments, the first spacer 164A and the second spacer 164B may not abut against the first holder 310 and the second holder 320.

As described above, since the first insulating layer 160 including the first protrusions 162 and the second protrusions 164 having different heights may be formed through a patterning process, the number of masks used in the manufacturing process of the display panel 1 may be reduced, thereby achieving the effects of simplifying the manufacturing process, reducing the manufacturing time, and reducing the manufacturing cost.

In addition, in the display panel 1, the first protrusion 162 may provide a higher topography and serve as a bonding structure for electrically connecting the pixel electrode 180 to the first drain D1, thereby preventing the pixel electrode 180 from being chipped or broken during the formation process, and enabling the display panel 1 to provide excellent display quality.

In some embodiments, an alignment layer (not shown) may be further disposed on the array substrate 10 or the opposite substrate 300. For example, the alignment layer may be disposed on the opposite substrate 300 between the

supports

310 and 320 and the opposite substrate 300, but not limited thereto. For the rest, please refer to the foregoing embodiments, which are not described herein.

Fig. 9 is a partial cross-sectional view of a display panel to which an array substrate according to another embodiment of the present invention is applied. The display panel 2 shown in the present embodiment is similar to the display panel 1 shown in fig. 8, and the main differences are that: the first supporter 310 has the same thickness as the second supporter 320A. In addition, the height of the second spacers 164B 'is greater than the height of the first spacers 164A'. In another aspect, the display panel 2 is, for example, a spacer (PS) disposed on the array substrate 10A. In other words, the first spacers 164A 'may function as secondary spacers, for example, while the second spacers 164B' may function as primary spacers. Under the above arrangement, the second spacers 164B' may abut against the second supports 320A to provide the required support and liquid crystal gap for the display panel 1A. The first spacers 164A' do not abut against the first support 310, but the invention is not limited thereto. In some embodiments, the first spacer 164A 'and the second spacer 164B' may both abut against the first support 310 and the second support 320A, respectively. In other embodiments, the first spacer 164A 'and the second spacer 164B' may not abut against the first support 310 and the second support 320A. For the rest, please refer to the foregoing embodiments, which are not described herein.

In summary, the array substrate according to an embodiment of the invention can form the first insulating layer including the first protrusions and the second protrusions with different heights through a patterning process, so that the number of masks used in the manufacturing process of the array substrate can be reduced, and the effects of simplifying the manufacturing process, reducing the manufacturing time, and reducing the manufacturing cost can be achieved.

In addition, in the array substrate according to an embodiment of the invention, the second protrusion may serve as a spacer, and the first protrusion belonging to the same film as the second protrusion may provide a higher topography and serve as a lap joint structure for electrically connecting the pixel electrode to the first drain electrode, so as to prevent the pixel electrode from generating a gap or a disconnection during the formation process. Therefore, the array substrate of the embodiment of the invention not only has the advantages of simplifying the manufacturing process, reducing the manufacturing time and reducing the manufacturing cost, but also is applicable to the COA technology.

In addition, in the array substrate according to an embodiment of the invention, the first protrusion is disposed so as to prevent the pixel electrode from being chipped or broken during the formation process, so that the display panel including the array substrate has excellent display quality.

Furthermore, in the array substrate according to an embodiment of the invention, the first protrusion can be shared by the first conductive layers disposed adjacently, so that the array substrate can meet the requirement of high resolution.

The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. An array substrate, comprising:

a substrate;

a first active device disposed on the substrate, the first active device including a first semiconductor layer, and a first source and a first drain electrically connected to the first semiconductor layer; and

a first insulating layer disposed on the substrate, the first insulating layer comprising:

a first protrusion disposed on the substrate, wherein a vertical projection of the first protrusion on the substrate partially overlaps a vertical projection of the first drain on the substrate; and

a plurality of second protrusions arranged on the substrate, wherein the heights of the second protrusions are greater than the heights of the first protrusions;

a second insulating layer is arranged on the substrate and covers the first protrusion, wherein the second insulating layer is provided with an opening, and the vertical projection of the opening on the substrate is partially overlapped with the vertical projection of the first protrusion on the substrate.

2. The array substrate of claim 1, further comprising a plurality of data lines disposed on the substrate, wherein the vertical projections of the second protrusions on the substrate partially overlap the vertical projections of the data lines on the substrate.

3. The array substrate of claim 1, further comprising a color filter layer disposed between the substrate and the second insulating layer.

4. The array substrate of claim 1, further comprising:

a first conductive layer covering the first protrusion and electrically connected to the first drain; and

a second conductive layer disposed on the second insulating layer and electrically connected to the first conductive layer through the opening.

5. The array substrate of claim 4, further comprising:

a common electrode layer disposed on the second insulating layer and not overlapping the first insulating layer; and

and a pixel electrode arranged on the common electrode layer and electrically connected to the second conductive layer.

6. The array substrate of claim 1, wherein the second protrusions comprise a first spacer and a second spacer, and the height of the first spacer is the same as the height of the second spacer.

7. The array substrate of claim 6, further comprising a second insulating layer disposed on the substrate covering the first protrusion, the first spacer and the second spacer, wherein the second insulating layer has a first top surface correspondingly overlapping the first spacer and a second top surface correspondingly overlapping the second spacer, and a distance from the first top surface to the first spacer is the same as a distance from the second top surface to the second spacer in a direction perpendicular to the substrate.

8. The array substrate of claim 6, further comprising a second insulating layer disposed on the substrate covering the first protrusion, the first spacer and the second spacer, wherein the second insulating layer has a first top surface overlapping the first spacer and a second top surface overlapping the second spacer, and a distance from the first top surface to the first spacer is different from a distance from the second top surface to the second spacer in a direction perpendicular to the substrate.

9. The array substrate of claim 1, wherein the second protrusions comprise a first spacer and a second spacer, and the height of the first spacer is different from the height of the second spacer.

10. The array substrate of claim 9, further comprising a second insulating layer disposed on the substrate covering the first protrusion, the first spacer and the second spacer, wherein the second insulating layer has a first top surface correspondingly overlapping the first spacer and a second top surface correspondingly overlapping the second spacer, and a distance from the first top surface to the first spacer is the same as a distance from the second top surface to the second spacer in a direction perpendicular to the substrate.

11. The array substrate of claim 1, further comprising:

the second active element is arranged on the substrate and is adjacent to the first active element, wherein the second active element comprises a second semiconductor layer, a second source electrode and a second drain electrode which are electrically connected with the second semiconductor layer, and the vertical projection of the first protrusion on the substrate is partially overlapped with the vertical projection of the first drain electrode on the substrate and partially overlapped with the vertical projection of the second drain electrode on the substrate.

12. The array substrate of claim 11, further comprising a plurality of data lines disposed on the substrate, wherein a vertical projection of the first protrusion on the substrate partially overlaps a vertical projection of at least one of the data lines on the substrate.