TW202036105A - Array substrate - Google Patents

Array substrate Download PDF

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TW202036105A
TW202036105A TW108108859A TW108108859A TW202036105A TW 202036105 A TW202036105 A TW 202036105A TW 108108859 A TW108108859 A TW 108108859A TW 108108859 A TW108108859 A TW 108108859A TW 202036105 A TW202036105 A TW 202036105A
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Taiwan
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substrate
spacer
layer
insulating layer
protrusion
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TW108108859A
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Chinese (zh)
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TWI696866B (en
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宋文清
郭威宏
陳銘耀
黃國有
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友達光電股份有限公司
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Priority to TW108108859A priority Critical patent/TWI696866B/en
Priority to CN201910999710.2A priority patent/CN110854128B/en
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Publication of TW202036105A publication Critical patent/TW202036105A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Abstract

An array substrate includes a substrate, a first active element disposed on the substrate, and a first insulating layer disposed on the substrate. The first active element includes a first semiconducting layer and a first source electrode and a first drain electrode electrically connected to the first semiconducting layer. The first insulating layer includes a first protrusion and a plurality of second protrusions. An orthogonal projection of the first protrusion on the substrate overlaps with an orthogonal projection of the first drain electrode on the substrate. A height of the second protrusions is larger than a height of the first protrusion.

Description

陣列基板Array substrate

本發明是有關於一種陣列基板,且特別是有關於一種具有屬於同一膜層的第一凸起物及第二凸起物之陣列基板。The present invention relates to an array substrate, and particularly relates to an array substrate having first protrusions and second protrusions belonging to the same film layer.

隨著顯示技術的蓬勃發展,液晶顯示器(Liquid Crystal Display,LCD)、發光二極體顯示器(Light Emitting Diode Display,LED)、有機發光二極體顯示器(Organic Light Emitting Diode Display,OLED)、電泳顯示器等顯示面板(Electro-Phoretic Display,EPD)已逐漸地成為未來顯示器之主流。With the vigorous development of display technology, liquid crystal displays (LCD), light emitting diode displays (LED), organic light emitting diode displays (OLED), electrophoretic displays Electro-Phoretic Display (EPD) has gradually become the mainstream of future displays.

近年來,為了提高畫素密度並避免陣列基板與對向基板組立時所產生的對位誤差(misalignment),而提出了將彩色濾光層直接製作於薄膜電晶體陣列基板上(Color Filter on Array,COA)的技術。然而,將彩色濾光層整合至薄膜電晶體陣列基板的製程需要搭配額外的光罩進行微影蝕刻製程。因此,製程步驟繁複,導致製程時間增加,且製作成本高。In recent years, in order to improve the pixel density and avoid the misalignment caused by the assembly of the array substrate and the counter substrate, it has been proposed to directly fabricate the color filter layer on the thin film transistor array substrate (Color Filter on Array). , COA) technology. However, the process of integrating the color filter layer into the thin film transistor array substrate requires an additional photomask to perform the photolithography process. Therefore, the process steps are complicated, resulting in increased process time and high manufacturing costs.

本發明提供一種陣列基板,可以簡化製程、減少製程時間、降低製作成本,並提供優良的顯示品質。The invention provides an array substrate, which can simplify the manufacturing process, reduce the manufacturing process time, reduce the manufacturing cost, and provide excellent display quality.

本發明的陣列基板,包括基板、第一主動元件設置於基板上以及第一絕緣層設置於基板上。第一主動元件包括第一半導體層以及與第一半導體層電性連接之第一源極與第一汲極。第一絕緣層包括第一凸起物以及多個第二凸起物。第一凸起物設置於基板上。第一凸起物於基板上的垂直投影部分重疊於第一汲極於基板上的垂直投影。第二凸起物設置於基板上其中第二凸起物的高度大於第一凸起物的高度。The array substrate of the present invention includes a substrate, a first active element disposed on the substrate, and a first insulating layer disposed on the substrate. The first active device includes a first semiconductor layer, and a first source and a first drain electrically connected to the first semiconductor layer. The first insulating layer includes a first protrusion and a plurality of second protrusions. The first protrusion is arranged on the substrate. The vertical projection of the first protrusion on the substrate partially overlaps the vertical projection of the first drain on the substrate. The second protrusion is arranged on the substrate, wherein the height of the second protrusion is greater than the height of the first protrusion.

基於上述,本發明一實施方式的陣列基板可透過一道圖案化製程而形成包括高度不同的第一凸起物以及第二凸起物的第一絕緣層,藉此製造過程中所使用的光罩之數量可減少,達成簡化製程、減少製程時間並降低製作成本的功效。Based on the above, the array substrate of an embodiment of the present invention can form a first insulating layer including first protrusions and second protrusions with different heights through a patterning process, thereby the photomask used in the manufacturing process The quantity can be reduced to achieve the effect of simplifying the manufacturing process, reducing the manufacturing time and reducing the manufacturing cost.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施方式,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

以下將以圖式揭露本發明的多個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意地方式為之。Hereinafter, a number of embodiments of the present invention will be disclosed in the form of drawings. For clear description, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some conventional structures and elements will be shown schematically in the drawings.

在附圖中,為了清楚起見,放大了層、膜、面板、區域等的厚度。在整個說明書中,相同的附圖標記表示相同的元件。應當理解,當諸如層、膜、區域或基板的元件被稱為在另一元件「上」或「連接到」另一元件時,其可以直接在另一元件上或與另一元件連接,或者中間元件可以也存在。相反,當元件被稱為「直接在另一元件上」或「直接連接到」另一元件時,不存在中間元件。如本文所使用的,「連接」可以指物理及/或電性連接。再者,「電性連接」或「耦合」係可為二元件間存在其它元件。In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connection" can refer to physical and/or electrical connection. Furthermore, "electrical connection" or "coupling" can mean that there are other elements between two elements.

應當理解,儘管術語「第一」、「第二」、「第三」等在本文中可以用於描述各種元件、部件、區域、層及/或部分,但是這些元件、部件、區域、及/或部分不應受這些術語的限制。這些術語僅用於將一個元件、部件、區域、層或部分與另一個元件、部件、區域、層或部分區分開。因此,下面討論的「第一元件」、「部件」、「區域」、「層」或「部分」可以被稱為第二元件、部件、區域、層或部分而不脫離本文的教導。It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or Or part should not be restricted by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, the “first element”, “component”, “region”, “layer” or “portion” discussed below may be referred to as a second element, component, region, layer or portion without departing from the teachings herein.

除非另有定義,本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是,諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義,並且將不被解釋為理想化的或過度正式的意義,除非本文中明確地這樣定義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

圖1為本發明一實施方式的陣列基板的上視示意圖。圖2A為圖1沿剖面線A-A’的局部剖面示意圖。圖2B為圖1沿剖面線B-B’的局部剖面示意圖。圖2C為圖1沿剖面線C-C’的局部剖面示意圖。請參考圖1及圖2A,在本實施方式中,陣列基板10可包括基板100、第一主動元件TFT1以及第一絕緣層160,其中第一絕緣層160包括第一凸起物162以及多個第二凸起物164。另外,在本實施方式中,陣列基板10可更包括遮蔽層110、絕緣層120、掃描線SL、資料線DL、閘絕緣層130、層間絕緣層140、第三主動元件TFT3、彩色濾光層CF、遮光層BM、第二絕緣層260、共用電極層COM、第一導電層170、第二導電層172、第一保護層191、第二保護層192及畫素電極180。為了方便說明及觀察,圖1僅示意性地繪示部分構件,而省略繪示基板100、絕緣層120、閘絕緣層130、層間絕緣層140、第二絕緣層260、共用電極層COM、第一保護層191及第二保護層192。FIG. 1 is a schematic top view of an array substrate according to an embodiment of the invention. Fig. 2A is a schematic partial cross-sectional view of Fig. 1 along the section line A-A'. Fig. 2B is a schematic partial cross-sectional view of Fig. 1 along the section line B-B'. Fig. 2C is a schematic partial cross-sectional view of Fig. 1 along the section line C-C'. 1 and 2A, in this embodiment, the array substrate 10 may include a substrate 100, a first active device TFT1 and a first insulating layer 160. The first insulating layer 160 includes a first protrusion 162 and a plurality of The second protrusion 164. In addition, in this embodiment, the array substrate 10 may further include a shielding layer 110, an insulating layer 120, a scan line SL, a data line DL, a gate insulating layer 130, an interlayer insulating layer 140, a third active device TFT3, and a color filter layer. CF, light shielding layer BM, second insulating layer 260, common electrode layer COM, first conductive layer 170, second conductive layer 172, first protective layer 191, second protective layer 192 and pixel electrode 180. For the convenience of description and observation, FIG. 1 only schematically illustrates some of the components, while omitting the illustration of the substrate 100, the insulating layer 120, the gate insulating layer 130, the interlayer insulating layer 140, the second insulating layer 260, the common electrode layer COM, and the first insulating layer. A protective layer 191 and a second protective layer 192.

如圖2A所示,陣列基板10包括基板100。在本實施方式中,基板100的材質可以是玻璃、石英、有機聚合物、或是不透光/反射材料(例如:導電材料、晶圓、陶瓷、或其它可適用的材料)、或是其它可適用的材料,本發明不以此為限。As shown in FIG. 2A, the array substrate 10 includes a substrate 100. In this embodiment, the material of the substrate 100 can be glass, quartz, organic polymers, or opaque/reflective materials (for example, conductive materials, wafers, ceramics, or other applicable materials), or other materials. The applicable materials are not limited to this invention.

如圖2A所示,基板100上可設置絕緣層120。在本實施方式中,絕緣層120的材質包括無機材料、有機材料或上述材料的組合或其他合適的材料。上述無機材料例如是(但不限於):氧化矽、氮化矽、氮氧化矽或上述至少二種材料的堆疊層。上述有機材料例如是(但不限於):聚醯亞胺系樹脂、環氧系樹脂或壓克力系樹脂等高分子材料。As shown in FIG. 2A, an insulating layer 120 may be provided on the substrate 100. In this embodiment, the material of the insulating layer 120 includes inorganic materials, organic materials, a combination of the foregoing materials, or other suitable materials. The above-mentioned inorganic material is, for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials. The above-mentioned organic material is, for example (but not limited to): polymer materials such as polyimide resin, epoxy resin, or acrylic resin.

如圖1及圖2A所示,遮蔽層110可設置於基板100上位於基板100與絕緣層120之間。在本實施方式中,遮蔽層110的材質例如包括金屬、樹脂、石墨或其他合適的材料。遮蔽層110例如可以改善第一主動元件TFT1產生光漏電的問題,但本發明不以此為限。As shown in FIG. 1 and FIG. 2A, the shielding layer 110 can be disposed on the substrate 100 between the substrate 100 and the insulating layer 120. In this embodiment, the material of the shielding layer 110 includes, for example, metal, resin, graphite or other suitable materials. The shielding layer 110 can, for example, improve the problem of light leakage of the first active device TFT1, but the invention is not limited to this.

在本實施方式中,第一主動元件TFT1、掃描線SL以及多條資料線DL設置於基板100上。在此需說明的是,圖1為陣列基板10的局部上視示意圖,僅示意性地繪示一個第一主動元件TFT1以及一條掃描線SL交錯兩條資料線DL,然而本發明不以此為限。任何所屬技術領域中具有通常知識者應當能理解,第一主動元件TFT1、掃描線SL以及資料線DL的數量是依據使用者的需求而設置,不以圖1所示的數量為限。第一主動元件TFT1分別電性連接至一條掃描線SL及一條資料線DL。詳細而言,如圖1及2A所示,第一主動元件TFT1包括第一半導體層CH1以及與第一半導體層CH1電性連接之第一源極S1與第一汲極D1。第一主動元件TFT1還包括第一閘極G1。如圖1、圖2B及圖2C所示,於垂直基板100的方向上,第一閘極G1與第一半導體層CH1重疊,且第一閘極G1與第一半導體層CH1之間夾有閘絕緣層130。第一閘極G1與掃描線SL電性連接,且屬於同一膜層,但本發明不以此為限。如圖2A、圖2B及圖2C所示,層間絕緣層140設置於閘絕緣層130上。第一源極S1以及第一汲極D1設置於層間絕緣層140上。如圖1及圖2C所示,第一源極S1與資料線DL電性連接,且屬於同一膜層,但本發明不以此為限。第一源極S1通過接觸窗134與第一半導體層CH1電性連接。第一汲極D1通過接觸窗132與第一半導體層CH1電性連接。在本實施方式中,第一源極S1、第一汲極D1以及資料線DL屬於同一膜層,但本發明不以此為限。In this embodiment, the first active device TFT1, the scan line SL, and a plurality of data lines DL are disposed on the substrate 100. It should be noted that FIG. 1 is a schematic partial top view of the array substrate 10, which only schematically shows a first active device TFT1 and a scan line SL interlacing two data lines DL, but the present invention does not take this as limit. Any person with ordinary knowledge in the art should understand that the number of first active devices TFT1, scan line SL, and data line DL is set according to user requirements, and is not limited to the number shown in FIG. 1. The first active device TFT1 is electrically connected to a scan line SL and a data line DL, respectively. In detail, as shown in FIGS. 1 and 2A, the first active device TFT1 includes a first semiconductor layer CH1 and a first source S1 and a first drain D1 electrically connected to the first semiconductor layer CH1. The first active element TFT1 also includes a first gate G1. As shown in FIGS. 1, 2B and 2C, in the direction perpendicular to the substrate 100, the first gate G1 overlaps the first semiconductor layer CH1, and a gate is sandwiched between the first gate G1 and the first semiconductor layer CH1. Insulation layer 130. The first gate G1 is electrically connected to the scan line SL and belongs to the same film layer, but the invention is not limited to this. As shown in FIGS. 2A, 2B and 2C, the interlayer insulating layer 140 is disposed on the gate insulating layer 130. The first source S1 and the first drain D1 are disposed on the interlayer insulating layer 140. As shown in FIGS. 1 and 2C, the first source S1 is electrically connected to the data line DL and belongs to the same film layer, but the present invention is not limited to this. The first source S1 is electrically connected to the first semiconductor layer CH1 through the contact window 134. The first drain electrode D1 is electrically connected to the first semiconductor layer CH1 through the contact window 132. In this embodiment, the first source S1, the first drain D1 and the data line DL belong to the same film layer, but the invention is not limited to this.

在本實施方式中,第一主動元件TFT1是以頂部閘極型薄膜電晶體(top gate TFT)為例說明,但本發明不限於此。根據其他實施方式,上述第一主動元件TFT1也可為底部閘極型薄膜電晶體(bottom gate TFT)或其他適合之薄膜電晶體。在本實施方式中,第一主動元件TFT1例如為低溫多晶矽薄膜電晶體(low temperature poly-Si,LTPS)或非晶矽薄膜電晶體(amorphous Si,a-Si),但本發明不以此為限。In this embodiment, the first active device TFT1 is described by using a top gate TFT as an example, but the invention is not limited to this. According to other embodiments, the above-mentioned first active device TFT1 may also be a bottom gate TFT or other suitable thin film transistors. In this embodiment, the first active device TFT1 is, for example, a low temperature poly-Si thin film transistor (LTPS) or an amorphous silicon thin film transistor (a-Si), but the invention is not based on this. limit.

請參考圖1及圖2A,掃描線SL與資料線DL交錯設置且位於不同平面。如圖2A所示,掃描線SL設置於閘絕緣層130與層間絕緣層140之間。資料線DL設置於層間絕緣層140的表面141上。在本實施方式中,基於導電性的考量,掃描線SL、資料線DL、第一閘極G1、第一源極S1以及第一汲極D1的材質一般是使用金屬材料,但本發明不以此為限。Please refer to FIG. 1 and FIG. 2A, the scan line SL and the data line DL are alternately arranged and located on different planes. As shown in FIG. 2A, the scan line SL is disposed between the gate insulating layer 130 and the interlayer insulating layer 140. The data line DL is disposed on the surface 141 of the interlayer insulating layer 140. In this embodiment, based on the consideration of conductivity, the scan line SL, the data line DL, the first gate G1, the first source S1, and the first drain D1 are generally made of metal materials, but the present invention does not This is limited.

在本實施方式中,彩色濾光層CF設置於基板100上。如圖1、圖2A、圖2B及圖2C所示,彩色濾光層CF可包括彩色濾光圖案CF1、彩色濾光圖案CF2及彩色濾光圖案CF3。彩色濾光圖案CF1、CF2、CF3設置於層間絕緣層140上。換言之,陣列基板10是應用了將彩色濾光圖案直接整合至畫素陣列(color filter on array,COA)的技術。如圖1所示,彩色濾光圖案CF1可以對應第一主動元件TFT1設置。彩色濾光圖案CF2可以設置於彩色濾光圖案CF1的右方,而彩色濾光圖案CF3可以設置於彩色濾光圖案CF1的左方,但本發明不以此為限。如圖1、圖2A、圖2B及圖2C所示,彩色濾光圖案CF1、CF2、CF3可以於垂直基板100的方向上,部分重疊遮蔽層110、掃描線SL以及資料線DL,但本發明不以此為限。In this embodiment, the color filter layer CF is provided on the substrate 100. As shown in FIGS. 1, 2A, 2B, and 2C, the color filter layer CF may include a color filter pattern CF1, a color filter pattern CF2, and a color filter pattern CF3. The color filter patterns CF1, CF2, and CF3 are disposed on the interlayer insulating layer 140. In other words, the array substrate 10 is a technology of directly integrating color filter patterns into a color filter on array (COA). As shown in FIG. 1, the color filter pattern CF1 may be arranged corresponding to the first active element TFT1. The color filter pattern CF2 can be arranged on the right side of the color filter pattern CF1, and the color filter pattern CF3 can be arranged on the left side of the color filter pattern CF1, but the invention is not limited to this. As shown in FIGS. 1, 2A, 2B, and 2C, the color filter patterns CF1, CF2, and CF3 may partially overlap the shielding layer 110, the scan line SL, and the data line DL in the direction perpendicular to the substrate 100, but the present invention Not limited to this.

在本實施方式中,彩色濾光圖案CF1、CF2、CF3可分別對應不同顏色的光,但本發明不以此為限。詳細而言,彩色濾光圖案CF1可對應紅色、綠色、藍色、黃色、白色或其他顏色的光。彩色濾光圖案CF2可對應紅色、綠色、藍色、黃色、白色或其他顏色的光。彩色濾光圖案CF3可對應紅色、綠色、藍色、黃色、白色或其他顏色的光。在一些實施方式中,彩色濾光圖案CF1、CF2、CF3也可部分對應相同顏色的光或全部對應相同顏色的光。In this embodiment, the color filter patterns CF1, CF2, CF3 can respectively correspond to light of different colors, but the invention is not limited to this. In detail, the color filter pattern CF1 can correspond to light of red, green, blue, yellow, white or other colors. The color filter pattern CF2 can correspond to light of red, green, blue, yellow, white or other colors. The color filter pattern CF3 can correspond to light of red, green, blue, yellow, white or other colors. In some embodiments, the color filter patterns CF1, CF2, CF3 may also partially correspond to the same color light or all of the same color light.

在本實施方式中,遮光層BM對應彩色濾光圖案CF1、CF2、CF3彼此之交界處設置。在本實施方式中,遮光層BM配置於彩色濾光層CF上,如圖1所示,但本發明並不限於此。在其他實施方式中,遮光層BM可配置在彩色濾光層CF下方。此外,如圖1及圖2C所示,於垂直基板100的方向上,遮光層BM部分地重疊於資料線DL。在本實施方式中,遮光層BM的材質可包括金屬、樹脂、石墨或其他合適的材料,但本發明不以此為限。在本實施方式中,如圖1所示,於垂直基板100的方向上,彩色濾光層CF以及遮光層BM僅部分的重疊遮蔽層110,而不重疊第一源極S1以及第一汲極D1。如此,第一汲極D1可與畫素電極180電性連接(於後文進行詳細描述)。In this embodiment, the light-shielding layer BM is provided corresponding to the boundary between the color filter patterns CF1, CF2, and CF3. In this embodiment, the light shielding layer BM is disposed on the color filter layer CF, as shown in FIG. 1, but the present invention is not limited to this. In other embodiments, the light shielding layer BM may be disposed under the color filter layer CF. In addition, as shown in FIGS. 1 and 2C, in the direction perpendicular to the substrate 100, the light shielding layer BM partially overlaps the data line DL. In this embodiment, the material of the light shielding layer BM may include metal, resin, graphite or other suitable materials, but the present invention is not limited thereto. In this embodiment, as shown in FIG. 1, in the direction perpendicular to the substrate 100, the color filter layer CF and the light shielding layer BM only partially overlap the shielding layer 110, and do not overlap the first source S1 and the first drain. D1. In this way, the first drain D1 can be electrically connected to the pixel electrode 180 (described in detail later).

如圖1及圖2A所示,第一絕緣層160設置於層間絕緣層140的表面141上。第一絕緣層160包括第一凸起物162以及多個第二凸起物164。換言之,第一凸起物162與第二凸起物164屬於同一膜層。在本實施方式中,於垂直基板100的方向上,第一絕緣層160的第一凸起物162以及多個第二凸起物164對應地重疊遮蔽層110。第一凸起物162對應第一汲極D1設置,且多個第二凸起物164分別對應多條資料線DL設置。換言之,第一凸起物162於基板100上的垂直投影部分重疊於第一汲極D1於基板100上的垂直投影。第二凸起物164於基板100上的垂直投影部分重疊資料線DL於基板100上的垂直投影。從另一角度而言,如圖1及圖2A所示,於垂直基板100的方向上,第一凸起物162完全重疊接觸窗132並設置於第一汲極D1上,且第一凸起物162於基板100上的垂直投影會位於第一汲極D1於基板100上的垂直投影之內,以使部分第一汲極D1暴露出來。然而,本發明不以此為限,在一些實施方式中,於垂直基板100的方向上,第一凸起物162可以不完全重疊接觸窗132,而僅部分地重疊接觸窗132。如此,可以暴露出更多第一汲極D1,提升第一汲極D1與第一導電層170(於後文進行詳細描述)的接觸面積。As shown in FIGS. 1 and 2A, the first insulating layer 160 is disposed on the surface 141 of the interlayer insulating layer 140. The first insulating layer 160 includes a first protrusion 162 and a plurality of second protrusions 164. In other words, the first protrusion 162 and the second protrusion 164 belong to the same film layer. In this embodiment, in the direction perpendicular to the substrate 100, the first protrusion 162 and the plurality of second protrusions 164 of the first insulating layer 160 overlap the shielding layer 110 correspondingly. The first protrusion 162 is disposed corresponding to the first drain electrode D1, and the plurality of second protrusions 164 are disposed corresponding to the plurality of data lines DL, respectively. In other words, the vertical projection of the first protrusion 162 on the substrate 100 partially overlaps the vertical projection of the first drain D1 on the substrate 100. The vertical projection of the second protrusion 164 on the substrate 100 partially overlaps the vertical projection of the data line DL on the substrate 100. From another perspective, as shown in FIGS. 1 and 2A, in the direction perpendicular to the substrate 100, the first protrusion 162 completely overlaps the contact window 132 and is disposed on the first drain electrode D1, and the first protrusion The vertical projection of the object 162 on the substrate 100 is within the vertical projection of the first drain electrode D1 on the substrate 100, so that a part of the first drain electrode D1 is exposed. However, the present invention is not limited to this. In some embodiments, in the direction perpendicular to the substrate 100, the first protrusion 162 may not completely overlap the contact window 132, but only partially overlap the contact window 132. In this way, more first drain electrodes D1 can be exposed, and the contact area between the first drain electrodes D1 and the first conductive layer 170 (described in detail later) can be increased.

在本實施方式中,第一凸起物162以及這些第二凸起物164是利用同一道圖案化製程所定義出來的。詳細而言,可以在完成資料線DL以及第一汲極D1的圖案化製程後,將第一絕緣材料(未繪示)形成於層間絕緣層140的表面141上。於垂直基板100的方向上,第一絕緣材料可以重疊遮蔽層110,但本發明不以此為限。在本實施方式中,第一絕緣材料的形成方法可包括物理氣相沉積法(physical vapor deposition,PVD)或化學氣相沉積法(chemical vapor deposition,CVD),但本發明不以此為限。在本實施方式中,第一絕緣材料的材質例如包括光阻材料。第一絕緣材料可接著藉由半調式光罩(half tone mask,HTM)、相轉移光罩(phase shift mask)、或灰階光罩(gray tone mask)做為罩幕,以進行微影製程。如此一來,第一絕緣材料可以透過一道圖案化製程,便形成具有第一凸起物162以及多個第二凸起物164的第一絕緣層160。換言之,第一凸起物162與第二凸起物164屬於同一膜層(均屬於第一絕緣層160),且可以利用同一道光罩定義。因此,在製造陣列基板10的製程中,可以減少所使用的光罩之數量,故能簡化製程、減少製程時間並降低製作成本。In this embodiment, the first protrusions 162 and the second protrusions 164 are defined by the same patterning process. In detail, after the patterning process of the data line DL and the first drain electrode D1 is completed, a first insulating material (not shown) can be formed on the surface 141 of the interlayer insulating layer 140. In the direction perpendicular to the substrate 100, the first insulating material may overlap the shielding layer 110, but the invention is not limited to this. In this embodiment, the method for forming the first insulating material may include physical vapor deposition (PVD) or chemical vapor deposition (CVD), but the invention is not limited thereto. In this embodiment, the material of the first insulating material includes, for example, a photoresist material. The first insulating material can then be used as a mask with a half tone mask (HTM), phase shift mask (phase shift mask), or gray tone mask for the lithography process . In this way, the first insulating material can pass through a patterning process to form the first insulating layer 160 with the first protrusions 162 and the plurality of second protrusions 164. In other words, the first protrusion 162 and the second protrusion 164 belong to the same film layer (both belong to the first insulating layer 160), and can be defined by the same mask. Therefore, in the process of manufacturing the array substrate 10, the number of masks used can be reduced, so the process can be simplified, the process time can be reduced, and the manufacturing cost can be reduced.

如圖1及圖2A所示,第一導電層170設置於層間絕緣層140上,並且覆蓋第一凸起物162以及部分第一汲極D1(例如:不重疊於第一凸起物162的部分第一汲極D1)。藉此,第一導電層170電性連接於第一汲極D1,且第一導電層170能夠順著第一凸起物162向較高的地形延伸。換言之,第一導電層170與第一凸起物162一起於層間絕緣層140上構成一較高的地形。在本實施方式中,第一導電層170的材質可包括金屬材料或透明導電材料,但本發明不以此為限。As shown in FIGS. 1 and 2A, the first conductive layer 170 is disposed on the interlayer insulating layer 140, and covers the first protrusion 162 and a part of the first drain electrode D1 (for example: the first protrusion 162 does not overlap Part of the first drain D1). Thereby, the first conductive layer 170 is electrically connected to the first drain electrode D1, and the first conductive layer 170 can extend along the first protrusion 162 to a higher terrain. In other words, the first conductive layer 170 and the first protrusion 162 together form a higher topography on the interlayer insulating layer 140. In this embodiment, the material of the first conductive layer 170 may include a metal material or a transparent conductive material, but the invention is not limited thereto.

在本實施方式中,多個第二凸起物164可以分別設置於第一凸起物162的相對兩側。如圖1及圖2A所示,這些第二凸起物164可包括第一間隙物164A以及第二間隙物164B。第一間隙物164A例如設置於第一凸起物162的右側,而第二間隙物164B例如設置於第一凸起物162的左側,但本發明不以此為限。如圖1、圖2A及圖2C所示,第一間隙物164A設置於第一凸起物162右側的資料線DL上,並於垂直基板100的方向上,重疊部分的資料線DL、第一半導體層CH1以及第一源極S1。換言之,第一間隙物164A可以對應第一主動元件TFT1設置。如圖1及圖2A所示,第二間隙物164B設置於第一凸起物162左側的資料線DL上,並於垂直基板100的方向上,重疊部分的資料線DL、第三半導體層CH3以及第三源極S3。第三半導體層CH3以及第三源極S3為第三主動元件TFT3的一部分,且第三主動元件TFT3對應第三彩色濾光圖案CF3設置。第三主動元件TFT3相似於第一主動元件TFT1,故於此相關內容不再贅述。基於前文針對第一主動元件TFT1的描述,所屬技術領域中具有通常知識者應理解,第三主動元件TFT3包括圖1未揭示的閘極與汲極。從另一觀點而言,第二間隙物164B可以對應第三主動元件TFT3設置,而與第一主動元件TFT1相鄰設置,但本發明不以此為限。In this embodiment, a plurality of second protrusions 164 may be respectively disposed on opposite sides of the first protrusion 162. As shown in FIGS. 1 and 2A, the second protrusions 164 may include a first spacer 164A and a second spacer 164B. The first spacer 164A, for example, is disposed on the right side of the first protrusion 162, and the second spacer 164B, for example, is disposed on the left side of the first protrusion 162, but the invention is not limited thereto. As shown in FIGS. 1, 2A, and 2C, the first spacer 164A is disposed on the data line DL on the right side of the first protrusion 162, and in the direction perpendicular to the substrate 100, the overlapped part of the data line DL, the first The semiconductor layer CH1 and the first source S1. In other words, the first spacer 164A may be provided corresponding to the first active device TFT1. As shown in FIGS. 1 and 2A, the second spacer 164B is disposed on the data line DL on the left side of the first protrusion 162, and in the direction perpendicular to the substrate 100, the data line DL and the third semiconductor layer CH3 overlap with each other. And the third source S3. The third semiconductor layer CH3 and the third source electrode S3 are a part of the third active element TFT3, and the third active element TFT3 is disposed corresponding to the third color filter pattern CF3. The third active device TFT3 is similar to the first active device TFT1, so the relevant content will not be described here. Based on the foregoing description of the first active device TFT1, those skilled in the art should understand that the third active device TFT3 includes a gate and a drain that are not disclosed in FIG. 1. From another point of view, the second spacer 164B may be provided corresponding to the third active element TFT3 and adjacent to the first active element TFT1, but the invention is not limited to this.

如圖2A所示,第一間隙物164A以及第二間隙物164B具有相同的高度H2。換言之,在本實施方式中,多個第二凸起物164具有相同的高度H2。在本文中,第一間隙物164A的高度H2可被定義為層間絕緣層140的表面141至第一間隙物164A的頂面1641A之間的距離。同樣地,第二間隙物164B的高度H2可被定義為層間絕緣層140的表面141至第二間隙物164B的頂面1641B之間的距離。從另一觀點而言,在本實施方式中,第一間隙物164A的頂面1641A與第二間隙物164B的頂面1641B切齊。As shown in FIG. 2A, the first spacer 164A and the second spacer 164B have the same height H2. In other words, in this embodiment, the plurality of second protrusions 164 have the same height H2. Herein, the height H2 of the first spacer 164A may be defined as the distance from the surface 141 of the interlayer insulating layer 140 to the top surface 1641A of the first spacer 164A. Similarly, the height H2 of the second spacer 164B may be defined as the distance between the surface 141 of the interlayer insulating layer 140 and the top surface 1641B of the second spacer 164B. From another point of view, in this embodiment, the top surface 1641A of the first spacer 164A is aligned with the top surface 1641B of the second spacer 164B.

如圖2A所示,第一間隙物164A以及第二間隙物164B(亦即第二凸起物164)的高度H2大於第一凸起物162的高度H1。在本文中,第一凸起物162的高度H1可被定義為層間絕緣層140的表面141至第一凸起物162的頂面1621之間的距離。如此,在使陣列基板10組裝為顯示面板時,相對於第一凸起物162,高度較高的第二凸起物164可作用為提供支撐功能以及維持液晶間距(cell gap),但本發明不以此為限。As shown in FIG. 2A, the height H2 of the first spacer 164A and the second spacer 164B (that is, the second protrusion 164) is greater than the height H1 of the first protrusion 162. Herein, the height H1 of the first protrusion 162 may be defined as the distance between the surface 141 of the interlayer insulating layer 140 and the top surface 1621 of the first protrusion 162. In this way, when the array substrate 10 is assembled into a display panel, compared to the first protrusion 162, the second protrusion 164 having a higher height can function to provide a supporting function and maintain the cell gap. However, the present invention Not limited to this.

在本實施方式中,第二絕緣層260可以整面性地設置於基板100上。如圖2A所示,第二絕緣層260設置於層間絕緣層140上,並覆蓋第一凸起物162及第一導電層170。另外,如圖2A所示,第二凸起物164凸出於第二絕緣層260。換言之,在本實施方式中,第一間隙物164A的頂面1641A高於第二絕緣層260的表面,以及第二間隙物164B的頂面1641B高於第二絕緣層260的表面。如圖2A、圖2B及圖2C所示,第二絕緣層260還可以覆蓋彩色濾光圖案CF1、CF2、CF3。從另一角度而言,彩色濾光層CF(包括:彩色濾光圖案CF1、CF2、CF3)設置於基板100與第二絕緣層260之間。在本實施方式中,第二絕緣層260的形成方法包括物理氣相沉積法(physical vapor deposition,PVD)或化學氣相沉積法(chemical vapor deposition,CVD),但本發明不以此為限。在本實施方式中,第二絕緣層260的材質例如包括氧化矽、氮化矽、氮氧化矽或光阻材料或其他合適的材料。In this embodiment, the second insulating layer 260 may be provided on the substrate 100 over the entire surface. As shown in FIG. 2A, the second insulating layer 260 is disposed on the interlayer insulating layer 140 and covers the first protrusion 162 and the first conductive layer 170. In addition, as shown in FIG. 2A, the second protrusion 164 protrudes from the second insulating layer 260. In other words, in this embodiment, the top surface 1641A of the first spacer 164A is higher than the surface of the second insulating layer 260, and the top surface 1641B of the second spacer 164B is higher than the surface of the second insulating layer 260. As shown in FIGS. 2A, 2B, and 2C, the second insulating layer 260 may also cover the color filter patterns CF1, CF2, CF3. From another perspective, the color filter layer CF (including the color filter patterns CF1, CF2, CF3) is disposed between the substrate 100 and the second insulating layer 260. In this embodiment, the method for forming the second insulating layer 260 includes physical vapor deposition (PVD) or chemical vapor deposition (CVD), but the invention is not limited thereto. In this embodiment, the material of the second insulating layer 260 includes, for example, silicon oxide, silicon nitride, silicon oxynitride or photoresist material or other suitable materials.

如圖1、圖2A、圖2B及圖2C所示,第二絕緣層260具有開口262。在本實施方式中,開口262於基板100上的垂直投影重疊於第一凸起物162於基板100上的垂直投影。藉此,開口262可以暴露出第一凸起物162的頂面1621上的第一導電層170。在一些實施方式中,開口262於基板100上的垂直投影也可以僅部分地重疊於第一凸起物162於基板100上的垂直投影。任何所屬技術領域中具有通常知識者在參照上述實施方式的說明後,應當能理解,開口262的布局並不以圖1和圖2A至圖2C為限,只要開口262能暴露出第一導電層170,以達成使第一汲極D1能與畫素電極180(於後文進行詳細描述)電性連接的作用即落入本發明的範疇。在本實施方式中,開口262的形成方法可包括以微影蝕刻製程、半調式光罩製程、相轉移光罩或灰調式光罩製程對第二絕緣層260進行圖案化。當開口262的形成方法採用半調式光罩製程、相轉移光罩或灰調式光罩製程時,則第二絕緣層260的形成方法可參照前述關於第一絕緣層160的描述,故於此不再贅述。另外一提的是,於形成開口262的製程中,可一併移除第二絕緣層260對應位於第二凸起物164上的部分,以使第二凸起物164凸出於第二絕緣層260。As shown in FIGS. 1, 2A, 2B, and 2C, the second insulating layer 260 has an opening 262. In this embodiment, the vertical projection of the opening 262 on the substrate 100 overlaps the vertical projection of the first protrusion 162 on the substrate 100. Thereby, the opening 262 can expose the first conductive layer 170 on the top surface 1621 of the first protrusion 162. In some embodiments, the vertical projection of the opening 262 on the substrate 100 may also only partially overlap the vertical projection of the first protrusion 162 on the substrate 100. Anyone with ordinary knowledge in the art should understand that the layout of the opening 262 is not limited to FIGS. 1 and 2A to 2C, as long as the opening 262 can expose the first conductive layer. 170, in order to achieve the function of enabling the first drain electrode D1 to be electrically connected with the pixel electrode 180 (described in detail later) falls within the scope of the present invention. In this embodiment, the method for forming the opening 262 may include patterning the second insulating layer 260 by a photolithography process, a half-tone mask process, a phase transfer mask, or a gray-scale mask process. When the opening 262 is formed by a half-tone mask process, a phase transfer mask or a gray-scale mask process, the method for forming the second insulating layer 260 can refer to the foregoing description of the first insulating layer 160, so it is not here. Repeat it again. In addition, in the process of forming the opening 262, the part of the second insulating layer 260 corresponding to the second protrusion 164 can be removed at the same time, so that the second protrusion 164 protrudes from the second insulating layer.层260.

在本實施方式中,第二導電層172設置於第二絕緣層260上。如圖1、圖2A及圖2B所示,於垂直基板100的方向上,第二導電層172重疊第一凸起物162並位於第一間隙物164A及第二間隙物164B之間。此外,於垂直基板100的方向上,第二導電層172部份地重疊遮蔽層110以及彩色濾光層CF。需注意的是,圖1為了清楚表示及方便說明,僅繪示一個第二導電層172對應彩色濾光圖案CF1設置。任何所屬技術領域中具有通常知識者應當能理解,第二導電層172還可以對應彩色濾光圖案CF2以及彩色濾光圖案CF3設置,不以圖1所示為限。In this embodiment, the second conductive layer 172 is disposed on the second insulating layer 260. As shown in FIGS. 1, 2A, and 2B, in the direction perpendicular to the substrate 100, the second conductive layer 172 overlaps the first protrusion 162 and is located between the first spacer 164A and the second spacer 164B. In addition, in the direction perpendicular to the substrate 100, the second conductive layer 172 partially overlaps the shielding layer 110 and the color filter layer CF. It should be noted that, for clarity and convenience of description, FIG. 1 only shows one second conductive layer 172 corresponding to the color filter pattern CF1. Anyone with ordinary knowledge in the art should understand that the second conductive layer 172 can also be provided corresponding to the color filter pattern CF2 and the color filter pattern CF3, and is not limited to that shown in FIG. 1.

如圖2A所示,第二導電層172通過開口262而電性連接至第一導電層170。如前文所述,電性連接於第一汲極D1的第一導電層170能夠順著第一凸起物162向較高的地形延伸,故第一凸起物162係作為第一導電層170的搭接結構,以使第一導電層170從第一汲極D1向上延伸至第二導電層172。從另一觀點而言,第二導電層172係透過第一導電層170而電性連接至第一汲極D1,以接收來自第一主動元件TFT1的電壓或驅動訊號。在本實施方式中,第二導電層172的材質包括透明導電材料,例如是銦錫氧化物、銦鋅氧化物、鋁錫氧化物、鋁鋅氧化物、銦鎵鋅氧化物或其他合適的氧化物或者是上述至少二者之堆疊層,但本發明不以此為限。As shown in FIG. 2A, the second conductive layer 172 is electrically connected to the first conductive layer 170 through the opening 262. As mentioned above, the first conductive layer 170 electrically connected to the first drain electrode D1 can extend to a higher terrain along the first protrusion 162, so the first protrusion 162 serves as the first conductive layer 170 The lap structure is such that the first conductive layer 170 extends upward from the first drain D1 to the second conductive layer 172. From another point of view, the second conductive layer 172 is electrically connected to the first drain D1 through the first conductive layer 170 to receive the voltage or driving signal from the first active device TFT1. In this embodiment, the material of the second conductive layer 172 includes a transparent conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or other suitable oxides. Or a stacked layer of at least two of the above, but the present invention is not limited to this.

如圖2A及圖2B所示,共用電極層COM設置於第二絕緣層260上。如圖2A及圖2B所示,於垂直基板100的方向上,共用電極層COM對應並重疊於彩色濾光層CF(包括:彩色濾光圖案CF1、CF2、CF3),但不重疊第一導電層170、第一凸起物162以及第二凸起物164。共用電極層COM部分地重疊第二導電層172、資料線DL以及掃描線SL。如圖2B所示,於垂直基板100的方向上,共用電極層COM重疊於第二導電層172,且共用電極層COM與第二導電層172之間夾有第一保護層191。在本實施方式中,第一保護層191的材質例如包括氧化矽、氮化矽、氮氧化矽或上述至少二種材料的堆疊層。如此,第二導電層172與共用電極層COM之間會產生儲存電容(storage capacitor)。換言之,第二導電層172、第一保護層191以及共用電極層COM可形成儲存電容器的架構。如此,可以提升陣列基板10的性能及顯示品質。As shown in FIGS. 2A and 2B, the common electrode layer COM is disposed on the second insulating layer 260. As shown in FIGS. 2A and 2B, in the direction perpendicular to the substrate 100, the common electrode layer COM corresponds to and overlaps the color filter layer CF (including: color filter patterns CF1, CF2, CF3), but does not overlap the first conductive layer. The layer 170, the first protrusion 162, and the second protrusion 164. The common electrode layer COM partially overlaps the second conductive layer 172, the data line DL, and the scan line SL. As shown in FIG. 2B, in a direction perpendicular to the substrate 100, the common electrode layer COM overlaps the second conductive layer 172, and a first protective layer 191 is sandwiched between the common electrode layer COM and the second conductive layer 172. In this embodiment, the material of the first protection layer 191 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the foregoing materials. In this way, a storage capacitor (storage capacitor) is generated between the second conductive layer 172 and the common electrode layer COM. In other words, the second conductive layer 172, the first protection layer 191, and the common electrode layer COM can form the structure of the storage capacitor. In this way, the performance and display quality of the array substrate 10 can be improved.

在本實施方式中,畫素電極180設置於共用電極層COM上。如圖2A及圖2B所示,畫素電極180與共用電極層COM之間夾有第二保護層192。詳細而言。第二保護層192設置於第一保護層191上,且第二保護層192可以覆蓋共用電極層COM。換言之,共用電極層COM位於第一保護層191與第二保護層192之間。第二保護層192位於共用電極層COM與畫素電極180之間。藉此,共用電極層COM可與畫素電極180分離。在本實施方式中,第二保護層192的材質例如包括氧化矽、氮化矽、氮氧化矽或上述至少二種材料的堆疊層。在本實施方式中,第二保護層192的材料與第一保護層191的材料可相同或不同。In this embodiment, the pixel electrode 180 is provided on the common electrode layer COM. As shown in FIGS. 2A and 2B, a second protective layer 192 is sandwiched between the pixel electrode 180 and the common electrode layer COM. In detail. The second protection layer 192 is disposed on the first protection layer 191, and the second protection layer 192 may cover the common electrode layer COM. In other words, the common electrode layer COM is located between the first protection layer 191 and the second protection layer 192. The second protection layer 192 is located between the common electrode layer COM and the pixel electrode 180. Thereby, the common electrode layer COM can be separated from the pixel electrode 180. In this embodiment, the material of the second protection layer 192 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the foregoing materials. In this embodiment, the material of the second protective layer 192 and the material of the first protective layer 191 may be the same or different.

如圖2A所示,第一保護層191以及第二保護層192分別具有接觸窗O1以及接觸窗O2。於垂直基板100的方向上,接觸窗O1、O2可以重疊第二導電層172以及開口262。接觸窗O1、O2的形成方法例如包括對第一保護層191以及第二保護層192進行微影蝕刻製程。另外,如圖2A所示,第一保護層191以及第二保護層192未覆蓋第一間隙物164A的頂面1641A及第二間隙物164B的頂面1641B。換言之,第二凸起物164凸出於第一保護層191以及第二保護層192。另外一提的是,於形成接觸窗O1的製程中,可一併移除第一保護層191對應位於第二凸起物164上的部分,以使第二凸起物164凸出於第一保護層191。同樣地,於形成接觸窗O2的製程中,可一併移除第二保護層192對應位於第二凸起物164上的部分,以使第二凸起物164凸出於第二保護層192。然而,本發明並不限於此。在其他實施方式中,第一保護層191以及第二保護層192可以覆蓋第一間隙物164A的頂面1641A及第二間隙物164B的頂面1641B。As shown in FIG. 2A, the first protective layer 191 and the second protective layer 192 respectively have a contact window O1 and a contact window O2. In the direction perpendicular to the substrate 100, the contact windows O1 and O2 may overlap the second conductive layer 172 and the opening 262. The method of forming the contact windows O1 and O2 includes, for example, performing a photolithographic etching process on the first protection layer 191 and the second protection layer 192. In addition, as shown in FIG. 2A, the first protective layer 191 and the second protective layer 192 do not cover the top surface 1641A of the first spacer 164A and the top surface 1641B of the second spacer 164B. In other words, the second protrusion 164 protrudes from the first protection layer 191 and the second protection layer 192. In addition, in the process of forming the contact window O1, the part of the first protection layer 191 corresponding to the second protrusion 164 can be removed together, so that the second protrusion 164 protrudes from the first Protection layer 191. Similarly, in the process of forming the contact window O2, the portion of the second protection layer 192 corresponding to the second protrusion 164 can be removed together, so that the second protrusion 164 protrudes from the second protection layer 192 . However, the present invention is not limited to this. In other embodiments, the first protective layer 191 and the second protective layer 192 may cover the top surface 1641A of the first spacer 164A and the top surface 1641B of the second spacer 164B.

在本實施方式中,如圖1及圖2B所示,畫素電極180可透過第二保護層192的接觸窗O2以及第一保護層191的接觸窗O1而電性連接至第二導電層172。如前文所述,第二導電層172透過第一導電層170而電性連接至第一汲極D1,故畫素電極180透過第二導電層172及第一導電層170而電性連接至第一汲極D1,以接收來自第一主動元件TFT1的電壓或驅動訊號。在上述的設置下,共用電極COM與畫素電極180之間可以產生驅動電場。也就是說,陣列基板10可以採用邊緣場切換(Fringe Field Switching,FFS)技術或橫向電場(In-Plane-Switching,IPS)技術驅動液晶。然而,本發明不以此為限。在其他實施方式中,陣列基板10可以採用扭轉向列(Twisted Nematic,TN)技術驅動液晶。換言之,陣列基板10例如為液晶顯示面板(Liquid Crystal Display,LCD)的主動元件陣列基板(active device array substrate),但本發明不以此為限。在本實施方式中,共用電極層COM與畫素電極180的材質包括透明導電材料,例如是銦錫氧化物、銦鋅氧化物、鋁錫氧化物、鋁鋅氧化物、銦鎵鋅氧化物或其他合適的氧化物或者是上述至少二者之堆疊層,但本發明不以此為限。In this embodiment, as shown in FIGS. 1 and 2B, the pixel electrode 180 can be electrically connected to the second conductive layer 172 through the contact window O2 of the second protective layer 192 and the contact window O1 of the first protective layer 191 . As described above, the second conductive layer 172 is electrically connected to the first drain electrode D1 through the first conductive layer 170, so the pixel electrode 180 is electrically connected to the first drain electrode through the second conductive layer 172 and the first conductive layer 170. A drain D1 is used to receive the voltage or driving signal from the first active device TFT1. Under the above arrangement, a driving electric field can be generated between the common electrode COM and the pixel electrode 180. In other words, the array substrate 10 can use fringe field switching (Fringe Field Switching, FFS) technology or lateral electric field (In-Plane-Switching, IPS) technology to drive the liquid crystal. However, the present invention is not limited to this. In other embodiments, the array substrate 10 may use a twisted nematic (TN) technology to drive the liquid crystal. In other words, the array substrate 10 is, for example, an active device array substrate (Liquid Crystal Display, LCD), but the invention is not limited to this. In this embodiment, the material of the common electrode layer COM and the pixel electrode 180 includes a transparent conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide or Other suitable oxides or stacked layers of at least two of the above, but the invention is not limited thereto.

如前文所述,電性連接於第一汲極D1的第一導電層170能夠順著第一凸起物162向較高的地形延伸,且畫素電極180透過第二導電層172及第一導電層170而電性連接至第一汲極D1,藉此在陣列基板10中,畫素電極180能經由一較高的地形而與第一汲極D1電性連接。如此一來,可避免畫素電極180於形成的過程中產生缺口或斷線。從另一觀點而言,在本實施方式中,第一凸起物162可做為能使畫素電極180電性連接至第一汲極D1的搭接結構。As mentioned above, the first conductive layer 170 electrically connected to the first drain electrode D1 can extend to a higher terrain along the first protrusion 162, and the pixel electrode 180 penetrates the second conductive layer 172 and the first The conductive layer 170 is electrically connected to the first drain electrode D1, so that in the array substrate 10, the pixel electrode 180 can be electrically connected to the first drain electrode D1 through a higher topography. In this way, the pixel electrode 180 can be prevented from being chipped or disconnected during the forming process. From another point of view, in this embodiment, the first protrusion 162 can be used as an overlap structure that enables the pixel electrode 180 to be electrically connected to the first drain electrode D1.

在一些實施方式中,陣列基板10也可以不包括第二導電層172。此時,畫素電極180可透過接觸窗O1、接觸窗O2及開口262而電性連接至第一導電層170,以接收來自第一主動元件TFT1的電壓或驅動訊號。In some embodiments, the array substrate 10 may not include the second conductive layer 172. At this time, the pixel electrode 180 can be electrically connected to the first conductive layer 170 through the contact window O1, the contact window O2, and the opening 262 to receive the voltage or driving signal from the first active device TFT1.

值得說明的是,由於陣列基板10可透過一道圖案化製程而形成包括高度不同的第一凸起物162以及第二凸起物164的第一絕緣層160,因此在陣列基板10的製造過程中所使用的光罩之數量可減少,達成簡化製程、減少製程時間並降低製作成本的功效。It is worth noting that since the array substrate 10 can form the first insulating layer 160 including the first protrusions 162 and the second protrusions 164 with different heights through a patterning process, during the manufacturing process of the array substrate 10 The number of masks used can be reduced, achieving the effects of simplifying the manufacturing process, reducing the manufacturing time and reducing the manufacturing cost.

此外,在陣列基板10中,第二凸起物164可作用為間隙物,且與第二凸起物164屬於同一膜層的第一凸起物162可提供一較高的地形並做為能使畫素電極180電性連接至第一汲極D1的搭接結構,藉以避免畫素電極180於形成的過程中產生缺口或斷線。如此一來,陣列基板10不但具備簡化製程、減少製程時間並降低製作成本的優勢,還適用COA的技術。In addition, in the array substrate 10, the second protrusions 164 can function as spacers, and the first protrusions 162 belonging to the same film layer as the second protrusions 164 can provide a higher topography and serve as an energy source. The pixel electrode 180 is electrically connected to the overlap structure of the first drain electrode D1, so as to prevent the pixel electrode 180 from being chipped or disconnected during the formation process. In this way, the array substrate 10 not only has the advantages of simplifying the manufacturing process, reducing the manufacturing time and reducing the manufacturing cost, but also applies COA technology.

下述實施方式沿用前述實施方式的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,關於省略了相同技術內容的部分說明可參考前述實施方式,下述實施方式中不再重複贅述。The following embodiments follow the component numbers and part of the content of the previous embodiments, wherein the same numbers are used to represent the same or similar components. For the omission of the same technical content, please refer to the aforementioned embodiments. The following embodiments will not Repeat it.

圖3為本發明另一實施方式的陣列基板的局部剖面示意圖。本實施方式所示的陣列基板10A與圖2A所示的陣列基板10類似,主要的差異在於:第二間隙物164B’的高度H3大於第一間隙物164A’的高度H2。詳細而言,第一間隙物164A’的高度H2可被定義為層間絕緣層140的表面141至第一間隙物164A’的頂面1641A’之間的距離。第二間隙物164B’的高度H3可被定義為層間絕緣層140的表面141至第二間隙物164B’的頂面1641B’之間的距離。換言之,如圖3所示,第一間隙物164A’與第二間隙物164B’具有不同的高度。從另一觀點而言,在本實施方式中,第一間隙物164A’的頂面1641A’與第二間隙物164B’的頂面1641B’不切齊。在上述的設置下,第一間隙物164A’例如可作用為次要的間隙物,而第二間隙物164B’則可作用為主要的間隙物,但本發明不以此為限。此外,第一間隙物164A’與第二間隙物164B’的高度H2、H3均大於第一凸起物162的高度H1。如此,陣列基板10A可獲致與上述實施方式類似的技術功效。其餘部分請參考前述實施方式,在此不贅述。3 is a schematic partial cross-sectional view of an array substrate according to another embodiment of the present invention. The array substrate 10A shown in this embodiment is similar to the array substrate 10 shown in FIG. 2A. The main difference is that the height H3 of the second spacer 164B' is greater than the height H2 of the first spacer 164A'. In detail, the height H2 of the first spacer 164A' may be defined as the distance from the surface 141 of the interlayer insulating layer 140 to the top surface 1641A' of the first spacer 164A'. The height H3 of the second spacer 164B' may be defined as the distance from the surface 141 of the interlayer insulating layer 140 to the top surface 1641B' of the second spacer 164B'. In other words, as shown in FIG. 3, the first spacer 164A' and the second spacer 164B' have different heights. From another point of view, in this embodiment, the top surface 1641A' of the first spacer 164A' is not aligned with the top surface 1641B' of the second spacer 164B'. Under the above arrangement, the first spacer 164A' can function as a secondary spacer, and the second spacer 164B' can function as a main spacer, but the invention is not limited thereto. In addition, the heights H2 and H3 of the first spacer 164A' and the second spacer 164B' are both greater than the height H1 of the first protrusion 162. In this way, the array substrate 10A can achieve similar technical effects as the above-mentioned embodiments. For the rest, please refer to the foregoing implementation manners, and will not be repeated here.

圖4為本發明又一實施方式的陣列基板的局部剖面示意圖。本實施方式所示的陣列基板10B與圖2A所示的陣列基板10類似,主要的差異在於:第二絕緣層260A除了覆蓋第一凸起物162外,還可以覆蓋第一間隙物164A以及第二間隙物164B。在本實施方式中,於垂直基板100的方向上,第二絕緣層260具有對應重疊第一間隙物164A的第一頂面263A以及對應重疊第二間隙物164B的第二頂面264A。如圖4所示,第一頂面263A與第一間隙物164A之間的距離k1以及第二頂面264A與第二間隙物164B之間的距離k2相同。詳細而言,距離k1可被定義為,於垂直基板100的方向上,第一頂面263A至第一間隙物164A的頂面1641A之間的距離。距離k2可被定義為,於垂直基板100的方向上,第二頂面264A至第二間隙物164B的頂面1641B之間的距離。從另一觀點而言,在本實施方式中,第一頂面263A與第二頂面264A切齊。如此,陣列基板10B可獲致與上述實施方式類似的技術功效。其餘部分請參考前述實施方式,在此不贅述。4 is a schematic partial cross-sectional view of an array substrate according to another embodiment of the present invention. The array substrate 10B shown in this embodiment is similar to the array substrate 10 shown in FIG. 2A. The main difference is that in addition to covering the first protrusion 162, the second insulating layer 260A can also cover the first spacer 164A and the first spacer 164A. Two spacers 164B. In this embodiment, in the direction perpendicular to the substrate 100, the second insulating layer 260 has a first top surface 263A corresponding to the first spacer 164A and a second top surface 264A corresponding to the second spacer 164B. As shown in FIG. 4, the distance k1 between the first top surface 263A and the first spacer 164A and the distance k2 between the second top surface 264A and the second spacer 164B are the same. In detail, the distance k1 can be defined as the distance between the first top surface 263A and the top surface 1641A of the first spacer 164A in a direction perpendicular to the substrate 100. The distance k2 may be defined as the distance between the second top surface 264A and the top surface 1641B of the second spacer 164B in the direction perpendicular to the substrate 100. From another point of view, in this embodiment, the first top surface 263A is aligned with the second top surface 264A. In this way, the array substrate 10B can achieve similar technical effects as the above-mentioned embodiments. For the rest, please refer to the foregoing implementation manners, and will not be repeated here.

圖5為本發明又一實施方式的陣列基板的局部剖面示意圖。本實施方式所示的陣列基板10C與圖4所示的陣列基板10B類似,主要的差異在於:對應重疊第一間隙物164A的第一頂面263A與第一間隙物164A之間的距離k1以及對應重疊第二間隙物164B的第二頂面264B與第二間隙物164B之間的距離k2’不同。詳細而言,距離k1可被定義為,於垂直基板100的方向上,第一頂面263A至第一間隙物164A的頂面1641A之間的距離。距離k2’可被定義為,於垂直基板100的方向上,第二頂面264B至第二間隙物164B的頂面1641B之間的距離。從另一觀點而言,在本實施方式中,第一頂面263A與第二頂面264B不切齊。在上述的設置下,即使第一間隙物164A與第二間隙物164B的高度相同,第一間隙物164A仍可透過第二絕緣層260B而作用為次要的間隙物。第二間隙物164B則可透過第二絕緣層260B而作用為主要的間隙物,但本發明不以此為限。如此,陣列基板10C可獲致與上述實施方式類似的技術功效。其餘部分請參考前述實施方式,在此不贅述。FIG. 5 is a schematic partial cross-sectional view of an array substrate according to another embodiment of the present invention. The array substrate 10C shown in this embodiment is similar to the array substrate 10B shown in FIG. 4, with the main difference being: the distance k1 between the first top surface 263A and the first spacer 164A corresponding to the overlapped first spacer 164A and The distance k2' between the second top surface 264B corresponding to the overlapping second spacer 164B and the second spacer 164B is different. In detail, the distance k1 can be defined as the distance between the first top surface 263A and the top surface 1641A of the first spacer 164A in a direction perpendicular to the substrate 100. The distance k2' can be defined as the distance from the second top surface 264B to the top surface 1641B of the second spacer 164B in the direction perpendicular to the substrate 100. From another point of view, in this embodiment, the first top surface 263A and the second top surface 264B are not aligned. Under the above arrangement, even if the heights of the first spacer 164A and the second spacer 164B are the same, the first spacer 164A can still pass through the second insulating layer 260B and act as a secondary spacer. The second spacer 164B can function as a main spacer through the second insulating layer 260B, but the invention is not limited thereto. In this way, the array substrate 10C can achieve similar technical effects to the above-mentioned embodiments. For the rest, please refer to the foregoing implementation manners, and will not be repeated here.

圖6為本發明再一實施方式的陣列基板的局部剖面示意圖。本實施方式所示的陣列基板10D與圖3所示的陣列基板10A類似,主要的差異在於:第二絕緣層260C可以覆蓋第一間隙物164A’以及第二間隙物164B’。在本實施方式中,於垂直基板100的方向上,第二絕緣層260C具有對應重疊第一間隙物164A’的第一頂面263C以及對應重疊第二間隙物164B’的第二頂面264C。如圖6所示,第一頂面263C與第一間隙物164A’之間的距離k1以及第二頂面264C與第二間隙物164B’之間的距離k2相同。詳細而言,距離k1可被定義為,於垂直基板100的方向上,第一頂面263C至第一間隙物164A’的頂面1641A’之間的距離。距離k2可被定義為,於垂直基板100的方向上,第二頂面264C至第二間隙物164B’的頂面1641B’之間的距離。從另一觀點而言,在本實施方式中,第一間隙物164A’與第二間隙物164B’具有不同的高度,且第一頂面263C與第二頂面264C位於不同的水平面上。因此第一頂面263C與第二頂面264C不切齊。在上述的設置下,即使在分別具有不同高度的第一間隙物164A’與第二間隙物164B’上設置第二絕緣層260C,第一間隙物164A仍可被應用為次要的間隙物。第二間隙物164B則可被應用為主要的間隙物,但本發明不以此為限。如此,陣列基板10D可獲致與上述實施方式類似的技術功效。其餘部分請參考前述實施方式,在此不贅述。FIG. 6 is a schematic partial cross-sectional view of an array substrate according to still another embodiment of the present invention. The array substrate 10D shown in this embodiment is similar to the array substrate 10A shown in FIG. 3, and the main difference is that the second insulating layer 260C can cover the first spacer 164A' and the second spacer 164B'. In this embodiment, in the direction perpendicular to the substrate 100, the second insulating layer 260C has a first top surface 263C corresponding to the overlap of the first spacer 164A' and a second top surface 264C corresponding to the overlap of the second spacer 164B'. As shown in FIG. 6, the distance k1 between the first top surface 263C and the first spacer 164A' and the distance k2 between the second top surface 264C and the second spacer 164B' are the same. In detail, the distance k1 can be defined as the distance between the first top surface 263C and the top surface 1641A' of the first spacer 164A' in a direction perpendicular to the substrate 100. The distance k2 can be defined as the distance from the second top surface 264C to the top surface 1641B' of the second spacer 164B' in the direction perpendicular to the substrate 100. From another point of view, in this embodiment, the first spacer 164A' and the second spacer 164B' have different heights, and the first top surface 263C and the second top surface 264C are located on different horizontal planes. Therefore, the first top surface 263C is not aligned with the second top surface 264C. With the above arrangement, even if the second insulating layer 260C is provided on the first spacer 164A' and the second spacer 164B' having different heights, the first spacer 164A can still be used as a secondary spacer. The second spacer 164B can be used as the main spacer, but the invention is not limited to this. In this way, the array substrate 10D can achieve similar technical effects as the above-mentioned embodiments. For the rest, please refer to the foregoing implementation manners, and will not be repeated here.

圖7A為本發明另一實施方式的陣列基板的上視示意圖。圖7B為圖7A沿剖面線D-D’的局部剖面示意圖。為了方便說明及觀察,圖7A僅示意性地繪示部分構件,而省略繪示基板100、絕緣層120、閘絕緣層130、層間絕緣層140、第二絕緣層260、共用電極層COM、第一保護層191及第二保護層192。本實施方式所示的陣列基板10E與圖1所示的陣列基板10類似,主要的差異在於:第二主動元件TFT2設置於基板100上,且與第一主動元件TFT1相鄰設置。詳細而言,如圖7A及圖7B所示,第二主動元件TFT2設置於第一主動元件TFT1的右側,並對應彩色濾光圖案CF2設置,但本發明不以此為限。在本實施方式中,第一絕緣層160’的第一凸起物162’於基板100上的垂直投影部分重疊多條資料線DL中的至少一者於基板100上的垂直投影。藉此,第一凸起物162’可以橫跨資料線DL,並同時重疊第一主動元件TFT1的第一汲極D1以及第二主動元件TFT2的第二汲極D2。FIG. 7A is a schematic top view of an array substrate according to another embodiment of the present invention. Fig. 7B is a schematic partial cross-sectional view of Fig. 7A along the section line D-D'. For the convenience of description and observation, FIG. 7A only schematically illustrates some components, while omitting to illustrate the substrate 100, the insulating layer 120, the gate insulating layer 130, the interlayer insulating layer 140, the second insulating layer 260, the common electrode layer COM, and the first insulating layer. A protective layer 191 and a second protective layer 192. The array substrate 10E shown in this embodiment is similar to the array substrate 10 shown in FIG. 1. The main difference is that the second active device TFT2 is disposed on the substrate 100 and is disposed adjacent to the first active device TFT1. In detail, as shown in FIGS. 7A and 7B, the second active device TFT2 is disposed on the right side of the first active device TFT1 and is disposed corresponding to the color filter pattern CF2, but the invention is not limited to this. In this embodiment, the vertical projection of the first protrusion 162' of the first insulating layer 160' on the substrate 100 partially overlaps the vertical projection of at least one of the plurality of data lines DL on the substrate 100. Thereby, the first bump 162' can cross the data line DL and overlap the first drain D1 of the first active device TFT1 and the second drain D2 of the second active device TFT2 at the same time.

如圖1及圖7A所示,第二主動元件TFT2與第一主動元件TFT1的材料及結構相似,故不多贅述。簡單而言,第二主動元件TFT2與第一主動元件TFT1可以電性連接至相同的掃描線SL。第二主動元件TFT2與第一主動元件TFT1則分別電性連接至不同的資料線DL。第二主動元件TFT2包括第二閘極G2、第二半導體層CH2以及與第二半導體層CH2電性連接之第二源極S2與第二汲極D2。如圖7A及圖7B所示,第二閘極G2與第二半導體層CH2重疊,且第二閘極G2與第二半導體層CH2之間夾有閘絕緣層130。第二閘極G2與掃描線SL電性連接,且屬於同一膜層,但本發明不以此為限。第二源極S2以及第二汲極D2位於層間絕緣層140上。第二源極S2與資料線DL電性連接,且屬於同一膜層,但本發明不以此為限。As shown in FIG. 1 and FIG. 7A, the material and structure of the second active device TFT2 and the first active device TFT1 are similar, so no further description will be given. In short, the second active device TFT2 and the first active device TFT1 can be electrically connected to the same scan line SL. The second active device TFT2 and the first active device TFT1 are respectively electrically connected to different data lines DL. The second active device TFT2 includes a second gate electrode G2, a second semiconductor layer CH2, and a second source electrode S2 and a second drain electrode D2 electrically connected to the second semiconductor layer CH2. As shown in FIGS. 7A and 7B, the second gate electrode G2 overlaps the second semiconductor layer CH2, and a gate insulating layer 130 is sandwiched between the second gate electrode G2 and the second semiconductor layer CH2. The second gate G2 is electrically connected to the scan line SL and belongs to the same film layer, but the invention is not limited to this. The second source S2 and the second drain D2 are located on the interlayer insulating layer 140. The second source S2 is electrically connected to the data line DL and belongs to the same film layer, but the invention is not limited to this.

如圖7A及圖7B所示,第一凸起物162’橫跨資料線DL設置,而對應重疊相鄰兩個主動元件TFT1、TFT2的汲極D1、D2。詳細而言,第一凸起物162’於基板100上的垂直投影部分重疊於第一主動元件TFT1的第一汲極D1於基板100上的垂直投影以及第二主動元件TFT2的第二汲極D2於基板100上的垂直投影。另外,如圖7A及圖7B所示,於垂直基板100的方向上,第一凸起物162’部分地重疊對應第一汲極D1的接觸窗132及部分地重疊對應第二汲極D2的接觸窗132,但本發明並不限於此。在其他實施方式中,於垂直基板100的方向上,第一凸起物162’可完全重疊對應第一汲極D1的接觸窗132及完全重疊對應第二汲極D2的接觸窗132。在本實施方式中,第一凸起物162’部分地重疊接觸窗134並設置於第一源極S1上,但本發明不以此為限。As shown in FIG. 7A and FIG. 7B, the first protrusion 162' is arranged across the data line DL and correspondingly overlaps the drain electrodes D1 and D2 of the two adjacent active devices TFT1 and TFT2. In detail, the vertical projection of the first protrusion 162' on the substrate 100 partially overlaps the vertical projection of the first drain D1 of the first active device TFT1 on the substrate 100 and the second drain of the second active device TFT2. The vertical projection of D2 on the substrate 100. In addition, as shown in FIGS. 7A and 7B, in the direction perpendicular to the substrate 100, the first protrusion 162' partially overlaps the contact window 132 corresponding to the first drain D1 and partially overlaps the contact window 132 corresponding to the second drain D2. Contact window 132, but the invention is not limited to this. In other embodiments, in a direction perpendicular to the substrate 100, the first protrusion 162' can completely overlap the contact window 132 corresponding to the first drain electrode D1 and completely overlap the contact window 132 corresponding to the second drain electrode D2. In this embodiment, the first protrusion 162' partially overlaps the contact window 134 and is disposed on the first source S1, but the invention is not limited to this.

在本實施方式中,相鄰的第一導電層170A、170B可以設置於相同的第一凸起物162’上。如圖7A及圖7B所示,對應第一主動元件TFT1的第一導電層170A設置於層間絕緣層140上,並且覆蓋部分第一凸起物162’以及部分第一汲極D1。同樣地,對應第二主動元件TFT2的第一導電層170B則覆蓋部分第一凸起物162’以及部分第二汲極D2。在上述的設置下,第一導電層170A以及第一導電層170B能夠順著第一凸起物162’向較高的地形延伸。換言之,第一導電層170A、第一導電層170B與第一凸起物162’一起於層間絕緣層140上構成一較高的地形。In this embodiment, the adjacent first conductive layers 170A, 170B may be disposed on the same first protrusion 162'. As shown in FIGS. 7A and 7B, the first conductive layer 170A corresponding to the first active device TFT1 is disposed on the interlayer insulating layer 140, and covers a part of the first protrusion 162' and a part of the first drain electrode D1. Similarly, the first conductive layer 170B corresponding to the second active device TFT2 covers a part of the first protrusion 162' and a part of the second drain electrode D2. With the above arrangement, the first conductive layer 170A and the first conductive layer 170B can extend to a higher terrain along the first protrusion 162'. In other words, the first conductive layer 170A, the first conductive layer 170B, and the first protrusion 162' together form a higher topography on the interlayer insulating layer 140.

在本實施方式中,第一導電層170A可以電性連接至第一汲極D1,且第一導電層170B可以電性連接至第二汲極D2。如圖7A及圖7B所示,第二導電層172通過開口262而電性連接至第一導電層170A以及第一導電層170B。如前文所述,電性連接於第一汲極D1的第一導電層170A以及電性連接於第二汲極D2的第一導電層170B能夠順著第一凸起物162’向較高的地形延伸,故第一凸起物162’係作為第一導電層170A以及第一導電層170B的搭接結構,以使第一導電層170A從第一汲極D1(第一導電層170B則從第二汲極D2)向上延伸至第二導電層172。從另一觀點而言,第二導電層172係透過第一導電層170A而電性連接至第一汲極D1(透過第一導電層170B而電性連接至第二汲極D2)。換言之,第一凸起物162’可被相鄰設置的第一導電層170A以及第一導電層170B共用,但本發明不以此為限。藉此,第一凸起物162’可以應用於具有高解析度需求的陣列基板10E上,提升性能及顯示品質。在一些實施方式中,第一凸起物162’也可以重疊更多條資料線DL,被相鄰的三個、四個或更多個第一導電層170A共用。藉此,更可以進一步簡化製程、減少製程時間並降低製作成本。In this embodiment, the first conductive layer 170A may be electrically connected to the first drain electrode D1, and the first conductive layer 170B may be electrically connected to the second drain electrode D2. As shown in FIGS. 7A and 7B, the second conductive layer 172 is electrically connected to the first conductive layer 170A and the first conductive layer 170B through the opening 262. As mentioned above, the first conductive layer 170A electrically connected to the first drain electrode D1 and the first conductive layer 170B electrically connected to the second drain electrode D2 can follow the first protrusion 162' to a higher direction. The topography extends, so the first protrusion 162' is used as the overlapping structure of the first conductive layer 170A and the first conductive layer 170B, so that the first conductive layer 170A is from the first drain D1 (the first conductive layer 170B is from The second drain electrode D2) extends upward to the second conductive layer 172. From another point of view, the second conductive layer 172 is electrically connected to the first drain D1 through the first conductive layer 170A (and is electrically connected to the second drain D2 through the first conductive layer 170B). In other words, the first protrusion 162' can be shared by the adjacent first conductive layer 170A and the first conductive layer 170B, but the present invention is not limited thereto. Thereby, the first protrusion 162' can be applied to the array substrate 10E with high-resolution requirements to improve performance and display quality. In some embodiments, the first protrusion 162' may also overlap more data lines DL, which are shared by three, four or more adjacent first conductive layers 170A. In this way, the manufacturing process can be further simplified, the manufacturing time can be reduced, and the manufacturing cost can be reduced.

另外,如圖7A所示,彩色濾光層CF以及遮光層BM不重疊遮蔽層110以及掃描線SL,但本發明不以此為限。如圖7A及圖7B所示,多個第二凸起物164可以對應地重疊資料線DL以及掃描線SL設置,但本發明不以此為限。此外,如圖7B所示,第一保護層191及第二保護層192覆蓋第二凸起物164,但本發明不以此為限。從另一觀點而言,在本實施方式中,第二凸起物164未凸出於第一保護層191以及第二保護層192。如此,陣列基板10E可獲致與上述實施方式類似的技術功效。其餘部分請參考前述實施方式,在此不贅述。In addition, as shown in FIG. 7A, the color filter layer CF and the light shielding layer BM do not overlap the shielding layer 110 and the scan line SL, but the invention is not limited to this. As shown in FIG. 7A and FIG. 7B, a plurality of second protrusions 164 can be arranged correspondingly to overlap the data line DL and the scan line SL, but the invention is not limited thereto. In addition, as shown in FIG. 7B, the first protection layer 191 and the second protection layer 192 cover the second protrusion 164, but the present invention is not limited thereto. From another point of view, in this embodiment, the second protrusion 164 does not protrude from the first protective layer 191 and the second protective layer 192. In this way, the array substrate 10E can achieve similar technical effects as the above-mentioned embodiments. For the rest, please refer to the foregoing implementation manners, and will not be repeated here.

圖8為應用本發明一實施方式的陣列基板之顯示面板的局部剖面示意圖。請參考圖1及圖8,在本實施方式中,顯示面板1除了包括如圖1及圖2A所示的陣列基板10,還包括對向基板300設置於陣列基板10的對向。在本實施方式中,對向基板300的材質可以是玻璃、石英、有機聚合物、或是其它可適用的材料,本發明不以此為限。在一些實施方式中,陣列基板10與對向基板300之間還可以包括液晶分子LC,但本發明不以此為限。換言之,顯示面板1例如為液晶顯示面板,但本發明不以此為限。FIG. 8 is a schematic partial cross-sectional view of a display panel using an array substrate according to an embodiment of the present invention. Please refer to FIGS. 1 and 8. In this embodiment, the display panel 1 includes the array substrate 10 shown in FIGS. 1 and 2A, and also includes an opposite substrate 300 disposed opposite to the array substrate 10. In this embodiment, the material of the counter substrate 300 can be glass, quartz, organic polymer, or other applicable materials, and the present invention is not limited thereto. In some embodiments, liquid crystal molecules LC may also be included between the array substrate 10 and the counter substrate 300, but the present invention is not limited thereto. In other words, the display panel 1 is, for example, a liquid crystal display panel, but the invention is not limited to this.

在本實施方式中,對向基板300上設置有第一支撐物310以及第二支撐物320。第一支撐物310是對應於第一間隙物164A設置,而第二支撐物320是對應於第二間隙物164B設置。在本實施方式中,第一支撐物310與第二支撐物320的厚度不同。具體而言,第二支撐物320的厚度大於第一支撐物310的厚度。從另一角度而言,顯示面板1例如是將間隙物(photospacer,PS)設置於對向基板300上。如圖8所示,於垂直基板100的方向上,第一支撐物310重疊第一間隙物164A,而第二支撐物320重疊第二間隙物164B。第二間隙物164B可以抵頂至第二支撐物320,以提供顯示面板1所需的支撐以及液晶間距。第一間隙物164A則不抵頂至第一支撐物310,但本發明不以此為限。在一些實施方式中,第一間隙物164A與第二間隙物164B均可以分別抵頂至第一支撐物310及第二支撐物320。在另一些實施方式中,第一間隙物164A與第二間隙物164B也可以均不抵頂至第一支撐物310及第二支撐物320。In this embodiment, a first support 310 and a second support 320 are provided on the counter substrate 300. The first support 310 is arranged corresponding to the first spacer 164A, and the second support 320 is arranged corresponding to the second spacer 164B. In this embodiment, the thickness of the first support 310 and the second support 320 are different. Specifically, the thickness of the second support 320 is greater than the thickness of the first support 310. From another perspective, for the display panel 1, for example, a spacer (photospacer, PS) is disposed on the opposite substrate 300. As shown in FIG. 8, in the direction perpendicular to the substrate 100, the first support 310 overlaps the first spacer 164A, and the second support 320 overlaps the second spacer 164B. The second spacer 164B can be pressed against the second support 320 to provide the support required by the display panel 1 and the liquid crystal spacing. The first spacer 164A does not push against the first support 310, but the invention is not limited to this. In some embodiments, the first spacer 164A and the second spacer 164B can both be pressed against the first support 310 and the second support 320, respectively. In other embodiments, the first spacer 164A and the second spacer 164B may not be against the first support 310 and the second support 320.

如前文所述,由於包括高度不同的第一凸起物162以及第二凸起物164的第一絕緣層160可透過一道圖案化製程而形成,因此在顯示面板1的製造過程中所使用的光罩之數量可減少,達成簡化製程、減少製程時間並降低製作成本的功效。As mentioned above, since the first insulating layer 160 including the first protrusions 162 and the second protrusions 164 with different heights can be formed through a patterning process, the method used in the manufacturing process of the display panel 1 The number of masks can be reduced, achieving the effects of simplifying the manufacturing process, reducing the manufacturing time and reducing the manufacturing cost.

此外,在顯示面板1中,第一凸起物162可提供一較高的地形並做為能使畫素電極180電性連接至第一汲極D1的搭接結構,藉此可避免畫素電極180於形成的過程中產生缺口或斷線,並使顯示面板1提供優良的顯示品質。In addition, in the display panel 1, the first protrusion 162 can provide a higher topography and serve as a lap structure that enables the pixel electrode 180 to be electrically connected to the first drain electrode D1, thereby avoiding pixel The electrode 180 is notched or broken during the forming process, and the display panel 1 provides excellent display quality.

在一些實施方式中,陣列基板10或對向基板300上還可以設置配向層(未繪示)。舉例而言,配向層可設置於對向基板300上,位於支撐物310、320與對向基板300之間,但不以此為限。其餘部分請參考前述實施方式,在此不贅述。In some embodiments, an alignment layer (not shown) may be further provided on the array substrate 10 or the counter substrate 300. For example, the alignment layer may be disposed on the opposite substrate 300 between the supports 310 and 320 and the opposite substrate 300, but not limited to this. For the rest, please refer to the foregoing implementation manners, and will not be repeated here.

圖9為應用本發明另一實施方式的陣列基板之顯示面板的局部剖面示意圖。本實施方式所示的顯示面板2與圖8所示的顯示面板1類似,主要的差異在於:第一支撐物310與第二支撐物320A具有相同的厚度。此外,第二間隙物164B’的高度大於第一間隙物164A’的高度。從另一角度而言,顯示面板2例如是將間隙物(photospacer,PS)設置於陣列基板10A上。換言之,第一間隙物164A’例如可作用為次要的間隙物,而第二間隙物164B’則可作用為主要的間隙物。在上述的設置下,第二間隙物164B’可以抵頂至第二支撐物320A,以提供顯示面板1A所需的支撐以及液晶間距。第一間隙物164A’則不抵頂至第一支撐物310,但本發明不以此為限。在一些實施方式中,第一間隙物164A’與第二間隙物164B’均可以分別抵頂至第一支撐物310及第二支撐物320A。在另一些實施方式中,第一間隙物164A’與第二間隙物164B’也可以均不抵頂至第一支撐物310及第二支撐物320A。其餘部分請參考前述實施方式,在此不贅述。9 is a schematic partial cross-sectional view of a display panel using an array substrate of another embodiment of the present invention. The display panel 2 shown in this embodiment is similar to the display panel 1 shown in FIG. 8. The main difference is that the first support 310 and the second support 320A have the same thickness. In addition, the height of the second spacer 164B' is greater than the height of the first spacer 164A'. From another perspective, for the display panel 2, for example, a spacer (photospacer, PS) is disposed on the array substrate 10A. In other words, the first spacer 164A' can function as a secondary spacer, and the second spacer 164B' can function as a primary spacer. Under the above arrangement, the second spacer 164B' can be pressed against the second support 320A to provide the support and liquid crystal spacing required by the display panel 1A. The first spacer 164A' does not reach the first support 310, but the invention is not limited to this. In some embodiments, both the first spacer 164A' and the second spacer 164B' can abut against the first support 310 and the second support 320A, respectively. In other embodiments, the first spacer 164A' and the second spacer 164B' may not be against the first support 310 and the second support 320A. For the rest, please refer to the foregoing implementation manners, and will not be repeated here.

綜上所述,本發明一實施方式的陣列基板可透過一道圖案化製程而形成包括高度不同的第一凸起物以及第二凸起物的第一絕緣層,藉此在陣列基板的製造過程中所使用的光罩之數量可減少,達成簡化製程、減少製程時間並降低製作成本的功效。In summary, the array substrate according to an embodiment of the present invention can form a first insulating layer including first protrusions and second protrusions with different heights through a patterning process, thereby in the manufacturing process of the array substrate The number of masks used can be reduced, achieving the effects of simplifying the manufacturing process, reducing the manufacturing time and reducing the manufacturing cost.

此外,在本發明一實施方式的陣列基板中,第二凸起物可作用為間隙物,且與第二凸起物屬於同一膜層的第一凸起物可提供一較高的地形並做為能使畫素電極電性連接至第一汲極的搭接結構,藉以避免畫素電極於形成的過程中產生缺口或斷線。如此一來,本發明一實施方式的陣列基板不但具備簡化製程、減少製程時間並降低製作成本的優勢,還適用COA的技術。In addition, in the array substrate of an embodiment of the present invention, the second protrusions can function as spacers, and the first protrusions that belong to the same film layer as the second protrusions can provide a higher topography and do In order to enable the pixel electrode to be electrically connected to the lap structure of the first drain electrode, so as to avoid the pixel electrode from being chipped or disconnected during the forming process. In this way, the array substrate of an embodiment of the present invention not only has the advantages of simplifying the manufacturing process, reducing the manufacturing time and reducing the manufacturing cost, but also applies the COA technology.

此外,在本發明一實施方式的陣列基板中,第一凸起物的設置使得可避免畫素電極於形成的過程中產生缺口或斷線,因此包括所述陣列基板的顯示面板得以具有優良的顯示品質。In addition, in the array substrate according to an embodiment of the present invention, the arrangement of the first protrusions makes it possible to prevent the pixel electrodes from being chipped or disconnected during the formation process, so the display panel including the array substrate can have excellent performance. Display quality.

再者,在本發明一實施方式的陣列基板中,第一凸起物可被相鄰設置的第一導電層所共用,藉此陣列基板可達成高解析度的需求。Furthermore, in the array substrate of an embodiment of the present invention, the first protrusions can be shared by the adjacent first conductive layers, so that the array substrate can meet the requirements of high resolution.

雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

1、2:顯示面板 10、10A、10B、10C、10D、10E:陣列基板 100:基板 110:遮蔽層 120:絕緣層 130:閘絕緣層 132、134、O1、O2:接觸窗 140:層間絕緣層 141:表面 160、160’:第一絕緣層 162、162’:第一凸起物 1621、1641A、1641A’、1641B、1641B’:頂面 164:第二凸起物 164A、164A’:第一間隙物 164B、164B’:第二間隙物 170、170A、170B:第一導電層 172:第二導電層 180:畫素電極 191:第一保護層 192:第二保護層 260、260A、260B、260C:第二絕緣層 262:開口 263A、263C:第一頂面 264A、264B、264C:第二頂面 300:對向基板 310:第一支撐物 320、320A:第二支撐物 A-A’、B-B’、C-C’、D-D’:剖面線 BM:遮光層 CH1:第一半導體層 CH2:第二半導體層 CH3:第三半導體層 CF:彩色濾光層 CF1、CF2、CF3:彩色濾光圖案 COM:共用電極層 D1:第一汲極 D2:第二汲極 DL:資料線 G1:第一閘極 G2:第二閘極 H1、H2、H3:高度 k1、k2、k2’:距離 LC:液晶分子 TFT1:第一主動元件 TFT2:第二主動元件 TFT3:第三主動元件 S1:第一源極 S2:第二源極 S3:第三源極 SL:掃描線1, 2: Display panel 10, 10A, 10B, 10C, 10D, 10E: array substrate 100: substrate 110: Masking layer 120: insulating layer 130: gate insulation 132, 134, O1, O2: contact window 140: Interlayer insulation 141: Surface 160, 160’: first insulating layer 162, 162’: the first protrusion 1621, 1641A, 1641A’, 1641B, 1641B’: top surface 164: second protrusion 164A, 164A’: first spacer 164B, 164B’: second spacer 170, 170A, 170B: first conductive layer 172: second conductive layer 180: pixel electrode 191: The first protective layer 192: second protective layer 260, 260A, 260B, 260C: second insulating layer 262: open 263A, 263C: the first top surface 264A, 264B, 264C: second top surface 300: Opposite substrate 310: first support 320, 320A: second support A-A’, B-B’, C-C’, D-D’: Section line BM: shading layer CH1: The first semiconductor layer CH2: second semiconductor layer CH3: Third semiconductor layer CF: Color filter layer CF1, CF2, CF3: color filter pattern COM: common electrode layer D1: The first drain D2: second drain DL: Data line G1: first gate G2: second gate H1, H2, H3: height k1, k2, k2’: distance LC: Liquid crystal molecules TFT1: the first active element TFT2: the second active element TFT3: The third active element S1: first source S2: second source S3: third source SL: scan line

圖1為本發明一實施方式的陣列基板的上視示意圖。 圖2A為圖1沿剖面線A-A’的局部剖面示意圖。 圖2B為圖1沿剖面線B-B’的局部剖面示意圖。 圖2C為圖1沿剖面線C-C’的局部剖面示意圖。 圖3為本發明另一實施方式的陣列基板的局部剖面示意圖。 圖4為本發明又一實施方式的陣列基板的局部剖面示意圖。 圖5為本發明又一實施方式的陣列基板的局部剖面示意圖。 圖6為本發明再一實施方式的陣列基板的局部剖面示意圖。 圖7A為本發明另一實施方式的陣列基板的上視示意圖。 圖7B為圖7A沿剖面線D-D’的局部剖面示意圖。 圖8為應用本發明一實施方式的陣列基板之顯示面板的局部剖面示意圖。 圖9為應用本發明另一實施方式的陣列基板之顯示面板的局部剖面示意圖。FIG. 1 is a schematic top view of an array substrate according to an embodiment of the invention. Fig. 2A is a schematic partial cross-sectional view of Fig. 1 along the section line A-A'. Fig. 2B is a schematic partial cross-sectional view of Fig. 1 along the section line B-B'. Fig. 2C is a schematic partial cross-sectional view of Fig. 1 along the section line C-C'. 3 is a schematic partial cross-sectional view of an array substrate according to another embodiment of the present invention. 4 is a schematic partial cross-sectional view of an array substrate according to another embodiment of the present invention. FIG. 5 is a schematic partial cross-sectional view of an array substrate according to another embodiment of the present invention. FIG. 6 is a schematic partial cross-sectional view of an array substrate according to still another embodiment of the present invention. FIG. 7A is a schematic top view of an array substrate according to another embodiment of the present invention. Fig. 7B is a schematic partial cross-sectional view of Fig. 7A along the section line D-D'. FIG. 8 is a schematic partial cross-sectional view of a display panel using an array substrate according to an embodiment of the present invention. 9 is a schematic partial cross-sectional view of a display panel using an array substrate of another embodiment of the present invention.

10:陣列基板 10: Array substrate

100:基板 100: substrate

110:遮蔽層 110: Masking layer

120:絕緣層 120: insulating layer

130:閘絕緣層 130: gate insulation

132、O1、O2:接觸窗 132, O1, O2: contact window

140:層間絕緣層 140: Interlayer insulation

141:表面 141: Surface

160:第一絕緣層 160: first insulating layer

162:第一凸起物 162: The first protrusion

1621、1641A、1641B:頂面 1621, 1641A, 1641B: top surface

164:第二凸起物 164: second protrusion

164A:第一間隙物 164A: First spacer

164B:第二間隙物 164B: second spacer

170:第一導電層 170: first conductive layer

172:第二導電層 172: second conductive layer

180:畫素電極 180: pixel electrode

191:第一保護層 191: The first protective layer

192:第二保護層 192: second protective layer

260:第二絕緣層 260: second insulating layer

262:開口 262: open

A-A’:剖面線 A-A’: Section line

CH1:第一半導體層 CH1: The first semiconductor layer

CH3:第三半導體層 CH3: Third semiconductor layer

CF2、CF3:彩色濾光圖案 CF2, CF3: Color filter pattern

COM:共用電極層 COM: common electrode layer

D1:第一汲極 D1: The first drain

DL:資料線 DL: Data line

H1、H2:高度 H1, H2: height

SL:掃描線 SL: scan line

Claims (13)

一種陣列基板,包括: 一基板; 一第一主動元件,設置於該基板上,該第一主動元件包括一第一半導體層以及與該第一半導體層電性連接之一第一源極與一第一汲極;以及 一第一絕緣層,設置於該基板上,該第一絕緣層包括: 一第一凸起物,設置於該基板上,其中該第一凸起物於該基板上的垂直投影部分重疊於該第一汲極於該基板上的垂直投影;以及 多個第二凸起物,設置於該基板上,其中該些第二凸起物的高度大於該第一凸起物的高度。An array substrate, including: A substrate; A first active device disposed on the substrate, the first active device including a first semiconductor layer and a first source and a first drain electrically connected to the first semiconductor layer; and A first insulating layer is disposed on the substrate, and the first insulating layer includes: A first protrusion disposed on the substrate, wherein the vertical projection of the first protrusion on the substrate partially overlaps the vertical projection of the first drain on the substrate; and A plurality of second protrusions are arranged on the substrate, wherein the height of the second protrusions is greater than the height of the first protrusion. 如申請專利範圍第1項所述的陣列基板,更包括多條資料線設置於該基板上,且該些第二凸起物於該基板上的垂直投影部分重疊於該些資料線於該基板上的垂直投影。The array substrate described in claim 1 further includes a plurality of data lines disposed on the substrate, and the vertical projections of the second protrusions on the substrate partially overlap the data lines on the substrate Vertical projection on the. 如申請專利範圍第1項所述的陣列基板,更包括一第二絕緣層設置於該基板上,覆蓋該第一凸起物,其中該第二絕緣層具有一開口,該開口於該基板上的垂直投影部分重疊於該第一凸起物於該基板上的垂直投影。The array substrate described in item 1 of the scope of the patent application further includes a second insulating layer disposed on the substrate to cover the first protrusion, wherein the second insulating layer has an opening on the substrate The vertical projection part overlaps the vertical projection of the first protrusion on the substrate. 如申請專利範圍第3項所述的陣列基板,更包括一彩色濾光層,設置於該基板與該第二絕緣層之間。As described in item 3 of the scope of patent application, the array substrate further includes a color filter layer disposed between the substrate and the second insulating layer. 如申請專利範圍第3項所述的陣列基板,更包括: 一第一導電層,覆蓋該第一凸起物,且電性連接至該第一汲極;以及 一第二導電層,設置於該第二絕緣層上,且通過該開口以電性連接至該第一導電層。The array substrate described in item 3 of the scope of patent application further includes: A first conductive layer covering the first protrusion and electrically connected to the first drain; and A second conductive layer is disposed on the second insulating layer and is electrically connected to the first conductive layer through the opening. 如申請專利範圍第5項所述的陣列基板,更包括: 一共用電極層,設置於該第二絕緣層上,且不重疊該第一絕緣層;以及 一畫素電極,設置於該共用電極層上,且電性連接至該第二導電層。The array substrate described in item 5 of the scope of patent application further includes: A common electrode layer disposed on the second insulating layer without overlapping the first insulating layer; and A pixel electrode is arranged on the common electrode layer and is electrically connected to the second conductive layer. 如申請專利範圍第1項所述的陣列基板,其中該些第二凸起物包括一第一間隙物以及一第二間隙物,該第一間隙物的高度與該第二間隙物的高度相同。The array substrate according to claim 1, wherein the second protrusions include a first spacer and a second spacer, and the height of the first spacer is the same as the height of the second spacer . 如申請專利範圍第7項所述的陣列基板,更包括一第二絕緣層設置於該基板上,覆蓋該第一凸起物、該第一間隙物以及該第二間隙物,其中該第二絕緣層具有對應重疊該第一間隙物的一第一頂面以及對應重疊該第二間隙物的一第二頂面,且於垂直該基板的方向上,該第一頂面至該第一間隙物的距離與該第二頂面至該第二間隙物的距離相同。The array substrate described in item 7 of the scope of patent application further includes a second insulating layer disposed on the substrate, covering the first protrusion, the first spacer and the second spacer, wherein the second insulating layer The insulating layer has a first top surface corresponding to the overlap of the first spacer and a second top surface corresponding to the overlap of the second spacer, and in the direction perpendicular to the substrate, the first top surface to the first gap The distance of the object is the same as the distance from the second top surface to the second spacer. 如申請專利範圍第7項所述的陣列基板,更包括一第二絕緣層設置於該基板上,覆蓋該第一凸起物、該第一間隙物以及該第二間隙物,其中該第二絕緣層具有重疊該第一間隙物的一第一頂面以及重疊該第二間隙物的一第二頂面,且於垂直該基板的方向上,該第一頂面至該第一間隙物的距離與該第二頂面至該第二間隙物的距離不同。The array substrate described in item 7 of the scope of patent application further includes a second insulating layer disposed on the substrate, covering the first protrusion, the first spacer and the second spacer, wherein the second insulating layer The insulating layer has a first top surface overlapping the first spacer and a second top surface overlapping the second spacer, and in a direction perpendicular to the substrate, from the first top surface to the first spacer The distance is different from the distance from the second top surface to the second spacer. 如申請專利範圍第1項所述的陣列基板,其中該些第二凸起物包括一第一間隙物以及一第二間隙物,該第一間隙物的高度與該第二間隙物的高度不同。The array substrate according to claim 1, wherein the second protrusions include a first spacer and a second spacer, and the height of the first spacer is different from the height of the second spacer . 如申請專利範圍第10項所述的陣列基板,更包括一第二絕緣層設置於該基板上,覆蓋該第一凸起物、該第一間隙物以及該第二間隙物,其中該第二絕緣層具有對應重疊該第一間隙物的一第一頂面以及對應重疊該第二間隙物的一第二頂面,且於垂直該基板的方向上,該第一頂面至該第一間隙物的距離與該第二頂面至該第二間隙物的距離相同。The array substrate described in item 10 of the scope of the patent application further includes a second insulating layer disposed on the substrate, covering the first protrusion, the first spacer and the second spacer, wherein the second insulating layer The insulating layer has a first top surface corresponding to the overlap of the first spacer and a second top surface corresponding to the overlap of the second spacer, and in the direction perpendicular to the substrate, the first top surface to the first gap The distance of the object is the same as the distance from the second top surface to the second spacer. 如申請專利範圍第1項所述的陣列基板,更包括: 一第二主動元件,設置於該基板上,且與該第一主動元件相鄰設置,其中該第二主動元件包括一第二半導體層以及與該第二半導體層電性連接之一第二源極與一第二汲極,以及該第一凸起物於該基板上的垂直投影部分重疊於該第一汲極於該基板上的垂直投影以及部分重疊該第二汲極於該基板上的垂直投影。The array substrate described in item 1 of the scope of patent application further includes: A second active device is disposed on the substrate and adjacent to the first active device, wherein the second active device includes a second semiconductor layer and a second source electrically connected to the second semiconductor layer Pole and a second drain, and the vertical projection of the first protrusion on the substrate partially overlaps the vertical projection of the first drain on the substrate and partially overlaps the second drain on the substrate Vertical projection. 如申請專利範圍第12項所述的陣列基板,更包括多條資料線設置於該基板上,其中該第一凸起物於該基板上的垂直投影部分重疊於該些資料線中的至少一者於該基板上的垂直投影。The array substrate described in item 12 of the scope of the patent application further includes a plurality of data lines disposed on the substrate, wherein the vertical projection of the first protrusion on the substrate partially overlaps at least one of the data lines The vertical projection on the substrate.
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