CN110854017A - Integration method of germanium-based detector - Google Patents

Integration method of germanium-based detector Download PDF

Info

Publication number
CN110854017A
CN110854017A CN201911157635.1A CN201911157635A CN110854017A CN 110854017 A CN110854017 A CN 110854017A CN 201911157635 A CN201911157635 A CN 201911157635A CN 110854017 A CN110854017 A CN 110854017A
Authority
CN
China
Prior art keywords
layer
substrate
germanium
silicon nitride
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201911157635.1A
Other languages
Chinese (zh)
Other versions
CN110854017B (en
Inventor
熊文娟
亨利·H·阿达姆松
王桂磊
赵雪薇
孔真真
林鸿霄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201911157635.1A priority Critical patent/CN110854017B/en
Publication of CN110854017A publication Critical patent/CN110854017A/en
Application granted granted Critical
Publication of CN110854017B publication Critical patent/CN110854017B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Light Receiving Elements (AREA)
  • Optical Integrated Circuits (AREA)

Abstract

The invention provides an integration method of a germanium-based detector, which comprises the following steps: providing a first substrate, and forming a silicon nitride waveguide structure on the first substrate; providing a second substrate, carrying out epitaxial growth on germanium on the second substrate to form a germanium thin film layer, continuing epitaxial growth on the germanium thin film layer to form a germanium-based epitaxial layer, and carrying out chemical mechanical polishing; depositing a high-k metal oxide on the germanium-based epitaxial layer to form a high-k metal oxide layer; bonding the high-k metal oxide layer of the second substrate to the first substrate; thinning the second substrate to a first thickness, and etching off the second substrate with the first thickness; chemical mechanical polishing to remove the germanium thin film layer; and preparing and forming the germanium-based detector on the germanium-based epitaxial layer. The invention improves the performance of a subsequently formed photoelectric device because the low-quality germanium film layer is removed.

Description

Integration method of germanium-based detector
Technical Field
The invention relates to the technical field of semiconductor integration, in particular to an integration method of a germanium-based detector.
Background
The silicon-based material provides a foundation for realizing the monolithic integration of photonic components (such as silicon waveguide gratings and silicon nitride waveguide gratings) and electronic devices (such as silicon-based photodetectors and germanium-based photodetectors). At present, monolithic integration of waveguide grating and photodetector has been realized on CMOS process line, and a germanium-based epitaxial layer is generally epitaxially formed on single crystal silicon by using a selective epitaxy technique, and then selective etching, ion implantation and annealing are performed to form a germanium-based photodetector. Before germanium is epitaxial, a low-temperature low-quality germanium film layer needs to grow on monocrystalline silicon in advance, so that a high-quality germanium-based epitaxial layer is ensured to be epitaxial on the basis. However, low temperature, low quality germanium thin film layers have a detrimental effect on the performance of germanium-based detectors formed by selective etching, ion implantation and annealing on germanium-based epitaxial layers.
Therefore, it is desirable to provide an integration method of a germanium-based detector that can avoid the defects of the germanium-based epitaxial layer during the growth process.
Disclosure of Invention
In view of the above problems, it is an object of the present invention to provide an integration method of a germanium-based detector capable of improving the performance of a germanium-based photodetector.
In order to achieve the above object, the present invention adopts the following technical solution, and an integration method of a germanium-based detector includes the following steps:
providing a first substrate, and forming a silicon nitride waveguide structure on the first substrate;
providing a second substrate, carrying out epitaxial growth on germanium on the second substrate to form a germanium thin film layer, continuing epitaxial growth on the germanium thin film layer to form a germanium-based epitaxial layer, and carrying out chemical mechanical polishing;
depositing a high-k metal oxide on the germanium-based epitaxial layer to form a high-k metal oxide layer;
bonding the high-k metal oxide layer of the second substrate to the first substrate;
thinning the second substrate to a first thickness, and etching off the second substrate with the first thickness;
chemical mechanical polishing to remove the germanium thin film layer;
and preparing and forming the germanium-based detector on the germanium-based epitaxial layer.
Preferably, the step of forming a silicon nitride waveguide structure on the first substrate comprises:
sequentially forming a first dielectric layer and a silicon nitride layer on a first substrate;
etching downwards from the top layer of the silicon nitride layer by adopting photoetching and etching processes to form a silicon nitride waveguide structure;
and depositing a second dielectric layer on the first substrate with the first dielectric layer and the silicon nitride waveguide structure, and chemically and mechanically polishing.
Preferably, the step of forming a silicon nitride waveguide structure on the first substrate comprises:
depositing a first dielectric layer on a first substrate, and forming a plurality of grooves from the top layer of the first dielectric layer by adopting photoetching and etching processes;
depositing silicon nitride on the formed structure for the first time;
depositing silicon nitride on the formed structure for the second time, and chemically and mechanically polishing to remove the silicon nitride deposited on the first dielectric layer to form a silicon nitride waveguide structure;
and depositing a second dielectric layer on the first substrate with the first dielectric layer and the silicon nitride waveguide structure, and chemically and mechanically polishing.
Preferably, the first dielectric layer, the second dielectric layer and the silicon nitride layer are formed by a plasma enhanced chemical vapor deposition method.
Preferably, atomic layer deposition is used to form the high-k metal oxide layer.
Preferably, the high-k metal oxide layer is Al2O3Layer(s)
Preferably, the first thickness is 20-30 microns.
Preferably, the second substrate of the first thickness is etched away using a tetramethylammonium hydroxide etchant.
Preferably, the first substrate and the second substrate are both silicon substrates or SOI substrates.
Preferably, the first dielectric layer and the second dielectric layer are both silicon dioxide dielectric layers.
In summary, the present invention forms a silicon nitride waveguide structure on a first substrate, i.e., forms a photonic device on the first substrate. And additionally, providing a second substrate, sequentially forming a germanium-based epitaxial layer and a high-k metal oxide layer which is easily bonded with a second medium layer on the first substrate on the second substrate, bonding the high-k metal oxide layer of the second substrate with the second medium layer of the first substrate, thinning the back surface of the second substrate to a certain thickness by adopting a thinning process, corroding the rest second substrate by adopting a corrosive liquid corrosion mode to expose a germanium thin layer formed on the second substrate for forming the high-quality germanium-based epitaxial layer conveniently, continuously removing the low-temperature deposited germanium thin layer by adopting a chemical mechanical polishing process, and only leaving the high-quality germanium-based epitaxial layer for preparing the photoelectric device. Compared with the existing monolithic integration process of the silicon waveguide grating and the germanium-based detector, the method has the advantages that the performance of a subsequently formed photoelectric device is improved because the low-quality germanium film layer is removed.
Drawings
FIG. 1 is a flow chart of a method of integrating a germanium-based detector according to one embodiment of the present invention;
fig. 2-15 are structural variations corresponding to each step in the method for integrating a ge-based detector according to the present invention.
The structure comprises a first substrate 10, a silicon nitride waveguide structure 11, a first dielectric layer 12, a groove 120, a silicon nitride layer 13 and a second dielectric layer 14;
20. a second substrate, 21, a germanium thin film layer, 22, a germanium-based epitaxial layer, 23, a high-k metal oxide layer.
Detailed Description
The following describes an embodiment according to the present invention with reference to the drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
The invention provides an integration method of a germanium-based detector, aiming at solving the technical problem that a germanium-based epitaxial layer has defects in the growth process.
Fig. 1 shows an embodiment of the integration method of a germanium-based detector provided by the invention, which comprises the following steps:
s10, referring specifically to fig. 2, providing a first substrate 10, forming a silicon nitride waveguide structure 11 on the first substrate 10;
the silicon nitride waveguide structure 11 has an effect of emitting laser light of a certain wavelength at an emission angle determined according to the design of the micro-nano structure, and has an advantage of small optical transmission loss compared with a silicon waveguide structure in the prior art.
The first substrate 10 is preferably a silicon substrate, but may of course be an SOI substrate having a top silicon, a back substrate and a buried oxide layer therebetween.
In this step, there are two methods of forming the silicon nitride waveguide structure 11 on the first substrate 10, the first method including the steps of:
S100A, referring to fig. 3 in particular, a first dielectric layer 12 and a silicon nitride layer 13 are sequentially deposited on the first substrate 10 by a plasma enhanced chemical vapor deposition method, wherein the first dielectric layer 12 is silicon dioxide, and the silicon nitride layer 13 is a base for forming the silicon nitride waveguide structure 11. The thicknesses of the first dielectric layer 12 and the silicon nitride layer 13 are determined according to specific requirements, and are not limited to specific values or ranges.
S101A, and referring to fig. 4 in particular, etching downward from the top layer of the silicon nitride layer 13 by using photolithography and etching processes to form the silicon nitride waveguide structure 11.
The method comprises the following steps: the silicon nitride waveguide structures 11 are spaced apart columnar structures.
S102A, with particular reference to fig. 2 and 5, a second dielectric layer 14 is deposited on the first substrate 10 with the first dielectric layer 12 and the silicon nitride waveguide structure 11, and chemical mechanical polishing.
In this step, the second dielectric layer 14 is sequentially deposited by using a plasma enhanced chemical vapor deposition method, the second dielectric layer 14 completely covers the silicon nitride waveguide structure 11, and after the second dielectric layer 14 is formed, a bulge is generated above the silicon nitride waveguide structure 11 due to the existence of the silicon nitride waveguide structure 11, so as to avoid the influence of the bulge on the subsequent bonding process, and therefore, after the second dielectric layer 14 is formed, chemical mechanical polishing is performed to planarize the top layer of the second dielectric layer 14.
A second method of forming a silicon nitride waveguide structure 11 on a first substrate 10 comprises the steps of:
S100B, referring to fig. 6 in particular, depositing a first dielectric layer 12 on a first substrate 10, and forming a plurality of grooves 120 from the top layer of the first dielectric layer 12 by photolithography and etching processes;
in this step, the groove 120 is a space for forming the silicon nitride waveguide structure 11, and the cross-sectional shape, area and height thereof are designed according to actual needs and are not particularly limited herein.
The first dielectric layer 12 is silicon dioxide, and the thickness of the first dielectric layer 12 is determined according to specific requirements, and is not limited to specific values or ranges.
S101B, specifically referring to fig. 7, depositing silicon nitride for the first time on the formed structure;
in this step, a first deposition of silicon nitride may be performed on the structure having the recess 120 by using a plasma enhanced chemical vapor deposition method, and after the first deposition of silicon nitride, silicon nitride may be deposited on the bottom and walls of the recess 120 and the top layer of the first dielectric layer 12.
S102B, referring to fig. 8 and 9 in particular, depositing silicon nitride for the second time on the formed structure, and performing chemical mechanical polishing to remove the silicon nitride deposited on the first dielectric layer 12;
in this step, a second deposition of silicon nitride on the structure with the recess 120 by plasma enhanced chemical vapor deposition may be used to fill the recess 120, and similarly, silicon nitride may be deposited on the first dielectric layer 12, so that after the second deposition of silicon nitride, the top layer of the formed structure is chemically and mechanically polished to remove the silicon nitride deposited on the first dielectric layer 12.
S103B, with particular reference to fig. 10, a second dielectric layer 14 is deposited on the first substrate 10 having the first dielectric layer 12 and the silicon nitride waveguide structure 11, and chemical mechanical polishing is performed.
In this step, a second dielectric layer 14 is sequentially deposited by a plasma enhanced chemical vapor deposition method, the second dielectric layer 14 completely covers the silicon nitride waveguide structure 11, and after the second dielectric layer 14 is deposited, chemical mechanical polishing is performed to planarize a top layer of the second dielectric layer 14.
S11, referring specifically to fig. 11, providing a second substrate 20, epitaxially growing germanium on the second substrate 20 to form a germanium thin film layer 21, continuing to epitaxially grow germanium on the germanium thin film layer 21 to form a germanium-based epitaxial layer 22, and chemical mechanical polishing;
in this step, the material and size of the second substrate 20 are preferably the same as those of the first substrate 10.
Preferably, before the germanium is epitaxially grown on the second substrate 20 to form the germanium-based epitaxial layer 22, a low-temperature low-quality germanium thin film layer 21 can be epitaxially grown on the top layer of the second substrate 20, and the germanium thin film layer 21 can be epitaxially formed on the basis of the low-temperature low-quality germanium thin film layer 21 to form the germanium-based epitaxial layer 22 with good quality.
After the formation of the germanium thin film layer 21, the germanium-based epitaxial layer 22 is formed by continuing epitaxy based on the germanium thin film layer 21, and the top layer of the germanium-based epitaxial layer 22 is polished by adopting a chemical mechanical polishing process.
S13, referring specifically to fig. 12, depositing on the germanium-based epitaxial layer 22 to form a high-k metal oxide layer 23;
in this step, a high-k metal oxide layer 23 is deposited on the germanium-based epitaxial layer 22, preferably by atomic layer deposition, and the high-k metal oxide layer 23 can be bonded to the second dielectric 14 layer.
The high-k metal oxide layer 23 may be Al2O3And (3) a layer.
S14, referring specifically to fig. 13 and 14, bonding the high-k metal oxide layer 23 of the second substrate 20 with the second dielectric layer 14 of the first substrate 10;
in this step, any one of the existing bonding processes is used to fasten the germanium thin film layer 21, the germanium-based epitaxial layer 22 and the high-k metal oxide layer 23 carried by the second substrate 20 to the top layer of the second dielectric layer 14.
S15, thinning the second substrate 20 to a first thickness, and etching off the second substrate 20 with the first thickness;
in this step, a thinning process is used to thin the backside of the second substrate 20 to a first thickness, which may be a thickness convenient for subsequent etching, such as 20-30 microns. Thereafter, the remaining second substrate 20 is etched away using a tetramethylammonium hydroxide etchant to expose the germanium thin film layer 21.
S16, see fig. 15 in particular, chemical mechanical polishing to remove the germanium thin film layer 21.
Prior to this step, the germanium-based thin film layer 21 has been exposed, and the chemical mechanical polishing process continues to remove the low-quality germanium-based thin film layer 21, leaving only the high-quality germanium-based epitaxial layer 22.
And S17, preparing and forming the germanium-based photoelectric detector on the germanium-based epitaxial layer.
The high-quality germanium-based epitaxial layer 22 is selectively etched to form a germanium structure (not shown in the figure), the germanium structure is subjected to ion implantation and annealing to form a germanium-based detector (not shown in the figure), the low-quality germanium thin film layer 21 is removed, and the performance of the germanium-based detector formed on the high-quality germanium-based epitaxial layer 22 can be improved.
In summary, the present invention forms a silicon nitride waveguide structure 11 on a first substrate 10, i.e., forms a photonic component on the first substrate 10. Providing a second substrate 20, sequentially forming a germanium-based epitaxial layer 22 and a high-k metal oxide layer 23 which is easy to bond with the first substrate 10 on the second substrate 20, bonding the high-k metal oxide layer 23 of the second substrate 20 with the first substrate 10, thinning the back surface of the second substrate 20 to a certain thickness by adopting a thinning process, etching away the rest of the second substrate 20 by adopting an etching solution corrosion mode to expose the germanium thin layer 21 formed on the second substrate 20 for forming the high-quality germanium-based epitaxial layer 22, and continuously removing the low-temperature deposited germanium thin layer 21 by adopting a chemical mechanical polishing process to only leave the high-quality germanium-based epitaxial layer 22 for preparing the photoelectric device. Compared with the existing monolithic integration process of the silicon waveguide grating and the germanium-based photodetector, the performance of the subsequently formed photoelectric device is improved because the low-quality germanium thin film layer 21 is removed.
In addition, according to the invention, the germanium-based epitaxial layer 22 is not directly epitaxially grown on the silicon nitride layer 13, but the high-k metal oxide layer 23 is bonded with the second medium layer 14 wrapped outside the silicon nitride grating 11, so that the problem that the silicon nitride layer 13 is not easily bonded with the germanium-based epitaxial layer 22 can be effectively solved.
It should be further noted that the method for integrating a germanium-based detector on a silicon nitride layer disclosed by the present invention is also applicable to the integration of a germanium-based detector on other semiconductor layers with high tensile stress characteristics.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A method of integrating a germanium-based detector, comprising the steps of:
providing a first substrate, and forming a silicon nitride waveguide structure on the first substrate;
providing a second substrate, carrying out epitaxial growth on germanium on the second substrate to form a germanium thin film layer, carrying out epitaxial growth on germanium on the germanium thin film layer to form a germanium-based epitaxial layer, and carrying out chemical mechanical polishing;
depositing a high-k metal oxide on the germanium-based epitaxial layer to form a high-k metal oxide layer;
bonding the high-k metal oxide layer of the second substrate to the first substrate;
thinning the second substrate to a first thickness, and etching off the second substrate with the first thickness;
chemical mechanical polishing to remove the germanium thin film layer;
and preparing and forming a germanium-based detector on the germanium-based epitaxial layer.
2. The method of claim 1, wherein forming a silicon nitride waveguide structure on the first substrate comprises:
sequentially forming a first dielectric layer and a silicon nitride layer on the first substrate;
etching downwards from the top layer of the silicon nitride layer by adopting photoetching and etching processes to form the silicon nitride waveguide structure;
and depositing a second dielectric layer on the first substrate with the first dielectric layer and the silicon nitride waveguide structure, and chemically and mechanically polishing.
3. The method of claim 1, wherein forming a silicon nitride waveguide structure on the first substrate comprises:
depositing a first dielectric layer on the first substrate, and forming a plurality of grooves from the top layer of the first dielectric layer by adopting photoetching and etching processes;
depositing silicon nitride on the formed structure for the first time;
depositing silicon nitride on the formed structure for the second time, and chemically and mechanically polishing to remove the silicon nitride deposited on the first dielectric layer to form the silicon nitride waveguide structure;
and depositing a second dielectric layer on the first substrate with the first dielectric layer and the silicon nitride waveguide structure, and chemically and mechanically polishing.
4. The method of claim 2, wherein the first dielectric layer, the second dielectric layer, and the silicon nitride layer are formed by a plasma enhanced chemical vapor deposition process.
5. The integrated method of a germanium-based detector according to claim 1, wherein the high-k metal oxide layer is deposited using atomic layer deposition.
6. The method of claim 5, wherein the high-k metal oxide layer is Al2O3And (3) a layer.
7. The method of claim 1, wherein the first thickness is 20-30 microns.
8. The method of claim 1 wherein the second substrate of the first thickness is etched away using a tetramethylammonium hydroxide etchant.
9. The method of claim 1, wherein the first and second substrates are both silicon substrates or SOI substrates.
10. The method of claim 2 or 3, wherein the first and second dielectric layers are silicon dioxide dielectric layers.
CN201911157635.1A 2019-11-22 2019-11-22 Integration method of germanium-based detector Active CN110854017B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911157635.1A CN110854017B (en) 2019-11-22 2019-11-22 Integration method of germanium-based detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911157635.1A CN110854017B (en) 2019-11-22 2019-11-22 Integration method of germanium-based detector

Publications (2)

Publication Number Publication Date
CN110854017A true CN110854017A (en) 2020-02-28
CN110854017B CN110854017B (en) 2022-07-12

Family

ID=69601935

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911157635.1A Active CN110854017B (en) 2019-11-22 2019-11-22 Integration method of germanium-based detector

Country Status (1)

Country Link
CN (1) CN110854017B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111446309A (en) * 2020-03-23 2020-07-24 中国科学院微电子研究所 Waveguide integrated photoelectric detector and manufacturing method thereof
CN111933753A (en) * 2020-08-14 2020-11-13 中国科学院微电子研究所 Waveguide type photoelectric detector and manufacturing method thereof
CN112186075A (en) * 2020-10-10 2021-01-05 中国科学院微电子研究所 Waveguide type photoelectric detector and manufacturing method thereof
CN112289892A (en) * 2020-11-02 2021-01-29 联合微电子中心有限责任公司 Photoelectric detector and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104882368A (en) * 2013-12-20 2015-09-02 加州大学董事会 Bonding of heterogeneous material grown on silicon to a silicon photonic circuit
CN106463566A (en) * 2014-03-10 2017-02-22 科锐安先进科技有限公司 Germanium metal-contact-free near-ir photodetector
CN108231803A (en) * 2017-12-26 2018-06-29 中国电子科技集团公司第五十五研究所 Silicon nitride fiber waveguide device and graphene detector integrated chip and preparation method thereof
CN109686658A (en) * 2018-12-13 2019-04-26 中国科学院微电子研究所 Semiconductor devices and its production method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104882368A (en) * 2013-12-20 2015-09-02 加州大学董事会 Bonding of heterogeneous material grown on silicon to a silicon photonic circuit
CN106463566A (en) * 2014-03-10 2017-02-22 科锐安先进科技有限公司 Germanium metal-contact-free near-ir photodetector
CN108231803A (en) * 2017-12-26 2018-06-29 中国电子科技集团公司第五十五研究所 Silicon nitride fiber waveguide device and graphene detector integrated chip and preparation method thereof
CN109686658A (en) * 2018-12-13 2019-04-26 中国科学院微电子研究所 Semiconductor devices and its production method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111446309A (en) * 2020-03-23 2020-07-24 中国科学院微电子研究所 Waveguide integrated photoelectric detector and manufacturing method thereof
CN111446309B (en) * 2020-03-23 2022-04-29 中国科学院微电子研究所 Waveguide integrated photoelectric detector and manufacturing method thereof
CN111933753A (en) * 2020-08-14 2020-11-13 中国科学院微电子研究所 Waveguide type photoelectric detector and manufacturing method thereof
CN112186075A (en) * 2020-10-10 2021-01-05 中国科学院微电子研究所 Waveguide type photoelectric detector and manufacturing method thereof
CN112186075B (en) * 2020-10-10 2023-05-23 中国科学院微电子研究所 Waveguide type photoelectric detector and manufacturing method thereof
CN112289892A (en) * 2020-11-02 2021-01-29 联合微电子中心有限责任公司 Photoelectric detector and manufacturing method thereof

Also Published As

Publication number Publication date
CN110854017B (en) 2022-07-12

Similar Documents

Publication Publication Date Title
CN110854017B (en) Integration method of germanium-based detector
US9568674B2 (en) Photonic device structure and method of manufacture
JP5969811B2 (en) Method for co-integrating photonic devices on a silicon photonics platform
TWI454765B (en) Vertical mirror in a silicon photonic circuit
CN106164722B (en) Edge coupled device fabrication
US7354840B1 (en) Method for opto-electronic integration on a SOI substrate
US9368579B2 (en) Selective area growth of germanium and silicon-germanium in silicon waveguides for on-chip optical interconnect applications
US8383489B2 (en) SOI wafer and method for forming the same
TW202410265A (en) Wafer-level etching methods for planar photonics circuits and devices
WO2009058470A1 (en) Method for fabricating butt-coupled electro-absorptive modulators
US7402477B2 (en) Method of making a multiple crystal orientation semiconductor device
US11508870B2 (en) Process for fabricating at least one tensilely strained planar photodiode
US11011409B2 (en) Devices with backside metal structures and methods of formation thereof
JP2017520936A (en) Method for manufacturing germanium-on-insulator substrate
US10325804B2 (en) Method of wafer thinning and realizing backside metal structures
JP7332158B2 (en) Semiconductor-on-insulator structures, particularly for front-side imaging devices, and methods of making such structures
KR101645256B1 (en) Optical waveguide device using bulk silicon wafer and fabrication method thereof
JP2022518001A (en) Ultra-thin integrated chip and its manufacturing method
TW200839330A (en) Low-loss optical device structure
US20190081139A1 (en) Devices having substrates with selective airgap regions
CN111785679A (en) Semiconductor device and method for manufacturing the same
WO2024110940A1 (en) Silicon-on-insulator (soi) carrier chip and methods of manufacture thereof
JP2024117354A (en) Germanium semiconductor device and its manufacturing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant