TW200839330A - Low-loss optical device structure - Google Patents

Abstract

A method of fabrication and a structure for a low-loss optical device. The optical device structure includes a waveguide that is formed within a device layer of an SOI substrate. A cladding region is formed beneath the waveguide and a BOX layer of the SOI substrate. The cladding region may comprise an air cavity or a cavity that is filled or at least partially filled with a dielectric material. Because the cladding region is formed in the bottom side, it supplements the BOX layer cladding. Consequently, a thinner BOX layer may be used for both electronic and optical devices, which facilitates optoelectronic IC processing and design.

Description

200839330 IX. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to optoelectronic integrated circuits and, more particularly, to low-loss opticals for low-loss optical devices using an insulator-on-insulator (S0I) substrate. Structure and manufacturing method. [Prior Art] A photoelectron integrated circuit (IC) includes both an electron and an optical element in a single wafer. Typical electronic components include field effect transistors (fet), capacitor resistors, and typical optical components include waveguides, filters, modulators, and photodetectors. Within a given photoelectron 1 (:, some of the π pieces of the electronic components may be dedicated to tasks such as data storage and signal processing. Other electronic components may be dedicated to controlling or modulating the optical components. The inclusion of two types of components on a single wafer provides several advantages, including reduced layout area, cost, and operational overhead. In addition, such integration produces a hybrid device such as an optical isolator. Φ Current semiconductor processing The maturity of technology has greatly facilitated the integration of optical and electronic components. For example, conventional processing techniques can be adapted to produce germanium, waveguides, and other optical devices. In general, photoelectrons are fabricated in SOI-based substrates. Ic. Advantageously, the S〇1 substrate provides a thin device layer on top of a buried oxide (B〇X) layer. Both electron and optical devices can be formed in or on the device layer. In a purely electronic device, such as a FET device, the germanium layer can be used to electrically isolate the device layer from the body layer. In an optical device, the germanium layer can be used as a cladding layer. In general, in both electronic and optical devices, 126566.doc 200839330 A thicker BOX layer promotes electrical isolation in an electronic device and optical limitations in an optical device. However, unfortunately, thick Β χ layer (greater than 2500 angstroms) also increases the likelihood of wafer bowing before or during manufacturing. In particular, larger wafers (eg, 8 inch or 12 inch wafers) are more susceptible to wafer bending. A thick B〇X layer also reduces the capacitance of the electronic device and changes the operational characteristics of the circuit', which necessitates the generation of alternative material-specific device models and circuit cell libraries for integrated optoelectronic product designs. [SUMMARY] Therefore, a low loss is illustrated. Optical device structure. In one example, the structure includes a SOI substrate and a cladding region in one of the body layers of the 801 substrate. The SOI substrate includes a device layer including an optical device region. Formed adjacent to the B0X layer of the SOI substrate and below the optical device region. Further, the germanium cladding region has an associated width greater than the optical device region Associated width. The cladding φ region can be formed by etching a cavity and/or a trench in the body layer. If a cavity is formed, the cavity has a width greater than a width of one of the optical device regions. Forming a trench, the trench has a width extending beyond the width of the optical device region. The cavity and/or trench may be an air cavity. Alternatively, for example, a dielectric material (eg, an oxide) may be used. Filling or at least partially filling the cavity and/or trench. - by depositing a masking layer on the body layer, patterning the masking layer to define a region of the cavity and/or trench and using an etching process to The pattern associated with the I and/or the trench is transferred into the body layer to form the cladding region. For example, the mask layer may include a photoresist mask layer and/or a hard mask layer of 126566.doc 200839330. In another example, the optical device structure can include a waveguide and/or a turn. The waveguide may be located on the front side of the SO] [substrate and the prism may be located on one of the bottom sides of the SOI substrate. The BOX layer can provide the so-called substrate - one of the front side and the bottom side is dissipated | These and other aspects and advantages will be apparent to those skilled in the art from reading the following detailed description. In addition, it is to be understood that the invention is not intended to limit the scope of the claimed invention. [Embodiment] In one form or another, various embodiments illustrate a low loss optical I structure and a manufacturing method. The method includes forming a cladding region under an optical device and adjacent a buried oxide region of one of the SOI substrates. The illustrated cladding area compensates for a thin layer of germanium. Thus, for example, a combination of a layer of germanium and the cladding region serves as a structure for the bottom cladding of an optical device (e.g., a waveguide). In general, the optical device structures described below are implemented in a variety of conventional semiconductor programs and combinations thereof, including: lithography, engraving, thin film deposition, and anti-reflective coatings. For the sake of simplicity, the following description and related drawings illustrate an optical device structure comprising - a stone-base waveguide comprising a single crystal layer. However, in the alternative examples, the illustrated cladding regions can be used to reduce various optical devices: optical losses and are not limited to a particular type of optical device or optical light-weight configuration. For example, the illustrated cladding area can be used to reduce optical losses in devices such as beamsplitters, mirrors, gratings, resonators, and modulators. 126566.doc 200839330 Also: White As explained below, the optical element can comprise a variety of materials and a plurality of: two specific characteristics for each individual layer (ie doping, thickness, ::n. For example, the thickness of a waveguide can be Customized to adapt to one or more modes of transmission. In addition, although the specific implementation described below 歹1 uses Shi Xiji optical components, other types of high refractive index materials (ie, Shishen gallium 1 bismuth clock, phosphorus Indium, etc.) may take the cutting element. In addition, unless otherwise stated, the elements may have various shapes and sizes.

Referring now to the drawings, the drawings are taken in the length direction of an optical device structure. The optical device structure is formed on a substrate 10, the substrate comprising a device layer 12, a layer of work 14, and a body layer 16. The device layer 12 is on the top side of the S?I substrate 10 and the body layer 16 is on the bottom side of the substrate. The further layer 14 is substantially located between the device layer 12 and the body layer 16. The device layer 12 includes a waveguide 18' which can be customized to various thicknesses to achieve the desired optical characteristics of the waveguide (e.g., mode selection). The BOX layer 14 can be used for various purposes. For example, the layer 丨4 is A microelectronic device (e.g., a FET 19) provides electrical isolation. The germanium layer 14 also facilitates optical confinement within the waveguide 18. Additionally, the BOX layer 14 can also be used as one of the top sides of the SOI substrate 1 Dissipative coupling between the bottom sides. For example, to introduce a beam into the waveguide 18 or to direct light away from the waveguide 18, the layer 14 acts as a spacer. As a spacer, the BOX layer 14 The distance between a prism 20 and the waveguide 18 is precisely set and thus the efficient and reproducible coupling of light into and out of the waveguide 18 is enabled. Figures 2A and 2B show at least two operations of the optical coupling structure of Figure 1. 126566.doc 200839330. In order to bring light into the waveguide 18, Figure 2A shows a beam 22 that enters the crucible 20 and is refracted. The BOX layer 14 assists in merging the beam 22 to the waveguide 18. To separate the light f Wave '18, Figure 2B shows the exit from the waveguide 18 and through the layer 14 Beam input to the Prism 2〇 23. It should be noted that the waveguide at least a portion of the Prism 18 and 20 may be used to couple light into and out of the waveguide 18.

The dissipative coupling of light through a BOX layer is further illustrated in the co-pending U.S. Patent Application Serial No. 11/412,738, the disclosure of which is incorporated herein by reference. To be used as a spacer and also to prevent wafer bowing during fabrication, the BOX layer 14 should be less than about 25 angstroms or less in thickness. However, to cover the waveguide 18 and thereby efficiently direct the beam, the waveguide 18 should be surrounded by a cladding having a low index of refraction and a sufficient thickness. To coat the top of the waveguide 18, an oxide layer 26 is grown or thermally deposited onto the waveguide 18. In one example the oxide layer 26 should have a thickness of about i um or more. φ However, to cover the bottom of the waveguide 18, a BOX layer 14 may not be sufficient to adequately confine the beam within the waveguide 18. Therefore, under the waveguide 18, a cladding region is formed. In general, the cladding region 24 serves to increase the cladding thickness of the BOX layer 14. Preferably, the cladding region 24 is an air cavity that is inherently a low index of refraction. However, a dielectric material (e.g., an oxide, a nitride, a polymer film, or a combination thereof) may also be used to fill the cladding region 24. More details regarding filling the cladding area will be explained with reference to FIG. 6B. FIG. 1 also shows an optical device 28 located adjacent the waveguide 18. It should be noted that various other microelectronic 'microelectromechanical and/or optical components may be present within, above or below the 126566.doc -10- 200839330 SOI substrate 10. For example, the optical device 28 can include a modulator that adjusts the optical characteristics of the waveguide 18. Figure 3A shows a top view of an SOI substrate 40. The substrate 40 includes a waveguide 42 formed in a device layer and an optical device 44 formed on top of the device layer, which may be, for example, a modulator. The substrate 40 may also include a pen device 'which is generally not an FET. Below the substrate 40, an optical device 46 and a cavity 48 may be formed in one of the body layers of the SOI substrate 40. The optical device 46 can be, for example, a turn or a grating that can be used to carry light into or out of the waveguide 42 (i.e., via a BOX layer). To prevent loss within the waveguide 42, the cavity 48 acts as a cladding region. Preferably, the chamber 48 is an air chamber or a chamber filled with a dielectric material or at least partially filled. The dielectric material should have a continuous index of refraction that is less than the refractive index of the waveguide 42 and less than or equal to the refractive index of a BOX layer. Moreover, to facilitate optical confinement, it is preferred that the cavity 48 have a width 5 大于 greater than the visibility 52 of the waveguide 42. For example, the cavity 48 can be patterned and etched with φ such that the cavity 48 sufficiently overlaps the waveguide and a portion of the substrate 40. Alternatively, a trench or a trench may be formed instead of a cavity. Figure 33 shows the trenches, wood 56 that have been formed on the bottom side of the SOI substrate 58, for example, in a body layer. The trench 56 extends beyond a width 62 of one of the waveguides 60. The trenches 6 also pass under other optical devices and thus also provide cladding to the devices. Fig. 4 shows a longitudinal sectional view of the SOI substrate 1 (see Fig. 1) before the formation of the cladding region 24. The cladding region can be formed at any point in a semiconductor process, such as in the SOI substrate 10 to produce a microelectronic device 126566.doc • 11· 200839330 Le or later. Further, the cladding region 24 may be formed before or after any photoelectron device is produced in the S 01 substrate 1 . Preferably, however, if the cladding region 24 comprises an air cavity (i.e., the cladding region is not filled with a dielectric material), the cladding region is formed after the formation of the microelectronics and optoelectronic device. For example, trenches or trenches in the bottom side of the wafer may make it difficult to adapt the wafer to various types of semiconductor tools. Fig. 5A is a cross-sectional view showing the longitudinal direction of the SOI substrate 1A after the cladding region 24 has been formed. It should be noted that a 稜鏡 or other type of optical engagement device may be formed in the body layer 16 (see, for example, Figure D. If a ridge is formed, care should be taken to form the coating before or after the formation of the raft) Area 24. In addition, a stack or other type of optical device can be mounted on the bottom side of a substrate. In this example, the size of a cladding area can be adjusted to accommodate the device (refer to Figure 7 to 8 further illustrates.) Figure 5B shows a cross-sectional view of the width of the sI substrate 1 after the cladding region 24. It should be noted that one of the cladding regions 24 has a width 64 greater than a width 66 of the waveguide 18. In general, the cladding region 24 can be produced in a variety of ways, preferably by an etch step (ie, a wet or dry etch) by a lithography process. Figure 6A is shown for use on a SOI substrate. A flow chart of an exemplary procedure for forming a cladding region within a body layer. It can be applied during front-end processing (ie, before metal is rendered on a wafer) 'applying during back-end processing or after finished back-end processing Flow chart in A. An SOI substrate is provided at step 70. A hard masking layer is deposited on the body layer of the bottom side of the substrate of the sI substrate in step 72. The hard mask layer can be, for example, 126566.doc 200839330. A photoresist mask layer is deposited over the hard mask layer at step 74. In step 76, a mask is aligned with a front side of the SOI substrate and the mask is used to pattern the photoresist mask layer. As noted above, a cladding area should be aligned beneath the optical device to be coated. Further, the cladding area can be aligned such that the cladding area is wider than the device to be coated. For example, the package The coverage area should be designed to be wider than an optical device area, wherein the optical device area represents an optical device system or an area in which the system will be positioned.

To align the cladding area, a mask aligner (e.g., a stepper) can use a camera to, for example, align a mask to features on the top side of the SOI substrate. The cladding region can be aligned with the device itself or various other features on the front side of the substrate. Other alignment methods other than cameras include the use of an IR (infrared) source to detect and align the front side features using a bottom side mask. In such an example, the alignment mask that can be identified by the mask aligner can be patterned into a suitable layer of the device to enable registration of a back side pattern to a front side (or vice versa). . The cavity and/or trench pattern is transferred to the hard mask layer via step 78' via, for example, a wet or dry chemical etch. In step 8, a wet or dry chemical (4) procedure can be used to transfer the cavity and/or trench pattern to the body layer. The cavity and/or trench may be left in place until the layer of germanium is exposed. Alternatively, the remainder procedure may be customized such that a thin portion of the stone is held between the layer, the [and/or the trench. This remaining helium can be subsequently oxidized and thus filled with cavities and/or trenches using a thermal oxide.

One step explanation). A is on the order of hundreds of μm), since the body layer can be substantially thicker (ie, at 126566.doc -13-200839330, the hard mask ensures that the photoresist mask is not transferred to the layer in the pattern A failure occurs during the process. Therefore, it is not necessary to perform a continuous etching step or a two-step etching process hard masking layer in step 78, for example, the photoresist may be sufficiently resistant to: transfer to the body The period during the layer remains intact. " may be during the etching process of step 78 or after the etch 4 in step 80

The photoresist mask is removed after the program is inscribed. The photoresist mask can be removed by, for example, ashing and/or a wet cleaning. The hard mask layer can be removed by etching with HF (hydrofluoric acid) or hot phosphorous. The type of hard mask strip can depend on the type of hard mask layer used. As described above, a dielectric material can be used to fill or partially fill a cladding region. The dielectric material can be used to - the specific optical device or application = the refractive index of the cladding region. Figure 6 is a flow chart showing an exemplary procedure for filling a cavity or trench with a dielectric material. At step 82, a cavity or trench to be filled is provided. In the step, a dielectric material is used to fill the cavity and/or trench. For example, a chemical vapor deposition (CVD) or a plasma enhanced CVD (PECVD) procedure can be used to deposit an oxide layer and completely fill or at least partially fill the cavity and/or trench. It will also be appreciated that a thermal diffusion process can also be used to grow a dielectric layer within the cavity and/or trench. The dielectric layer can be grown to a preferred thickness that completely fills or at least partially fills the cavity and/or trench. Moreover, as mentioned above, the chamber and/or the trench may include a remaining number of turns. This ruthenium can be oxidized during, for example, a wet or dry oxidation. In some examples, it may be preferable to perform a high temperature dielectric deposition step prior to forming the microelectronic device, as such temperatures may affect the diffusion profile of such devices. Figure 6C shows the cavity 24 of Figure 5A filled with a dielectric material 86. It should be understood that the dielectric material can be further processed in a variety of ways. For example, the dielectric material can be planarized via a chemical mechanical polishing or other type of polishing operation. 6 As described above, various optical devices can be mounted on the bottom side of a substrate. Thus, a cavity and/or trench can be customized to accommodate this installation. Figure 7 shows a top view of the SOI substrate 90. An optical device 92 is attached to the bottom side of the 〇1 substrate 90. Therefore, one length of one cavity/ditch is designed so that the optical device can be mounted on the 〇1 substrate. Fig. 8 is a longitudinal sectional view showing the SOI substrate 90 and the optical device 92. In general, the cladding region allows for a thinner layer of germanium for photoelectron 1C processing and design layout. For example, a layer having a thickness of less than 25 angstroms can be used for electrical isolation. However, the cladding area ensures that the optoelectronic device is sufficiently coated. However, it should be understood that the illustrated examples and the description are merely exemplary and are not intended to limit the scope of the invention. The above methods and structures are not limited to a particular type of optical device. Other optical devices can be coated by the methods described above. Further, although the disclosure uses the lithographic substrate, various other semiconductor substrates and films such as 〇仏8 and Ga^nP can be used instead of, for example, shi shi and yttria. Material ' can be customized for the folding of any of the above films. For example, a cavity can be filled with a dielectric material having a preferred refractive index. The scope of application for patents* should be understood to be limited to the description or component, unless otherwise stated for utility 126566.doc •15· 200839330. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE INVENTION [0012] The specific exemplary embodiments have been described with reference to the drawings, in which like reference numerals indicate like elements in the various figures, and wherein: Fig. 1 is an optical device structure according to an example Length direction section Γη3 · Figure,

2 and 2 show a longitudinal cross-sectional view of a beam of light beam dissipatively coupled into and out of a waveguide according to an example; FIG. 3 and FIG. 3 contain a waveguide on the top side of the substrate and the bottom of the substrate. FIG. 4 is a longitudinal cross-sectional view of an SOI substrate according to an example; FIG. 5A has a cladding region located in the main body layer according to an example; Another lengthwise cross-sectional view of an SOI substrate; FIG. 5B is a widthwise cross section of the SOI substrate of FIG. 5 according to an example.

Figure 6A and Figure 6B are flow diagrams for forming a cladding region in a body layer of a SOI substrate; Figure 6C is a longitudinal direction of a soi substrate having a cavity filled with a dielectric material. FIG. 7 is a plan view showing an SOI substrate including a waveguide on the top side of the SOI substrate and a cladding region on the bottom side of the NMOS substrate and an optical device; FIG. 8 is based on a specific A longitudinal cross-sectional view of an SOI substrate having a cladding region on an underside 126566.doc -16 - 200839330 of the SOI substrate and an optical device. [Main component symbol description] 10 SOI substrate &lt; 12 device layer 14 BOX layer 16 body layer 18 waveguide • 19 FET 20 稜鏡 24 cladding region / cavity 26 oxide layer 28 optical device 40 SOI substrate 42 waveguide 10 44 optical device 46 Optical device 48 Cavity 56 Ditch 60 Waveguide 86 Dielectric material 90 SOI substrate 92 Optical device 96 Cavity/ditch 126566.doc -17·

Claims (1)

200839330 X. Patent Application Range: 1. A low loss optical device structure comprising: an insulator upper substrate comprising a device layer and a body layer, wherein a buried oxide layer is inserted into the device layer and Between the body layers, and wherein the device layer includes an optical device region; and a cladding region of the body layer, wherein the cladding region is adjacent to the buried oxide layer and positioned under the optical device region And wherein the cladding region has an associated width greater than a width associated with the optical device region. 2. The optical device structure of claim 1, wherein the cladding region is formed by a process of etching a cavity in the body layer, wherein the cavity is adjacent to the buried oxide layer and positioned at the Below the optical device region, and wherein the cavity has a width that is greater than the width associated with the optical device region. 3. The optical device structure of claim 2, wherein the program further comprises causing the cavity to be filled with a dielectric material. 4. The optical device structure of claim 2, wherein the program further comprises growing a dielectric layer in the cavity. 5. The optical device structure of claim 1, wherein the cladding region is formed by a process comprising etching a trench in the body layer, wherein the trench is adjacent to the buried oxide layer and positioned The optical device region is ''and wherein the trench has a width that extends beyond the width associated with the optical device region. 6. A method for fabricating a low loss optical device structure, the method package 126566.doc 200839330 comprising: providing an insulator upper substrate comprising a device layer and a body layer, wherein gamma 曰/, a buried An oxide layer is interposed between the device layer and the body layer and wherein the device layer includes a waveguide region; and a cladding region is formed in the body layer, wherein the cladding region is opposite to the buried oxide layer Adjacent and positioned below the waveguide region. A method of claim 6 $, +, wherein the cladding region has an associated width that is greater than a width associated with a waveguide to be formed in the waveguide region. The method of claim 6, further comprising forming a waveguide in the waveguide region, wherein the cladding region has an associated width greater than a width associated with the waveguide. Forming the cladding region in the body of the substrate, wherein the cavity is adjacent to the buried oxide layer and positioned below the waveguide region. The method of claim 9 wherein the body Etching the cavity in the layer comprises: depositing a masking layer on the body layer; patterning the masking layer to define a location of the cavity; and using an etching process to transfer a pattern associated with the cavity to the body The method of claim 1 wherein the masking layer comprises at least one of a photoresist masking layer and a hard masking layer. 12. The method of claim 9, wherein the covering region is further formed A dielectric material is deposited in the cavity. 126566.doc -2- 200839330 13. The method of claim 9 wherein forming the cladding region further comprises growing a dielectric layer in the cavity. Loss optical device junction The method includes: an insulator upper substrate comprising a device layer and a body layer, wherein a buried oxide layer is interposed between the device layer and the body layer; an optical device is formed on the device layer Wherein the optical device has an associated width; and a cladding region formed in the body layer and opposite the buried oxide layer, wherein the edge cladding region has a width greater than the width of the optical device An associated optical device structure, wherein the optical device structure of claim 14 wherein a portion of the buried oxide layer facilitates an optical coupling between a bottom side and a front side of one of the upper substrate of the insulator. The optical device structure of claim 14, wherein the cladding region comprises a dielectric material. The optical device structure of claim 14, wherein the cladding region comprises an air cavity formed in the body layer, wherein the air cavity is adjacent to the buried oxide layer and positioned under the optical device, and wherein The air cavity has an associated width that is greater than the width of the optical device. The optical device structure of claim 17, further comprising a coupling to one of the buried oxide layers, wherein the prism is positioned within the air cavity. 19. The optical device structure of claim 14, wherein the optical device comprises a wave 126566.doc 200839330. 20. The optical device structure of claim 19, further comprising one of the body layers formed therein, wherein The crucible is adjacent to the cladding. 126566.doc