CN110852029B - Semiconductor chip and layout design method and device thereof - Google Patents
Semiconductor chip and layout design method and device thereof Download PDFInfo
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- CN110852029B CN110852029B CN201810845616.7A CN201810845616A CN110852029B CN 110852029 B CN110852029 B CN 110852029B CN 201810845616 A CN201810845616 A CN 201810845616A CN 110852029 B CN110852029 B CN 110852029B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000013461 design Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 123
- 230000009466 transformation Effects 0.000 claims description 5
- 238000013519 translation Methods 0.000 claims description 5
- 238000004590 computer program Methods 0.000 claims description 3
- 238000004378 air conditioning Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 230000000295 complement effect Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
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Abstract
The invention relates to a semiconductor chip and a layout design method and device thereof, wherein the layout design method comprises the following steps: obtaining a layout data file of a semiconductor chip, and extracting a through hole layer file containing through hole information from the layout data file; generating a metal interconnection layer file according to the through hole information in the through hole layer file; adding corresponding additional metal patterns in the region corresponding to at least one through hole in the metal interconnection layer file; and generating a metal connection pattern in the metal interconnection layer file according to the user requirement. By implementing the technical scheme of the invention, the problem of failure caused by metal overflow can be avoided, so that the yield of the semiconductor chip is ensured.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor chip and a layout design method and apparatus thereof.
Background
In the manufacturing process of the semiconductor device, firstly, various functional devices are manufactured by a semiconductor front-pass process, and after the device layer where the functional devices are located is manufactured, a metal interconnection layer is manufactured on the device layer. Referring to fig. 1 and 2A, metal 1 is a metal line disposed on a first metal layer, including metal lines 11, 12, 13, and 14, metal 2 is a metal line disposed on a metal interconnection layer, including metal lines 21 and 22, and the metal interconnection layer is disposed on the first metal layer, and through holes 31, 32, 33, and 34 are respectively used to connect the corresponding metal 1 and the corresponding metal 2. In many scenarios, the metal 2 is not covered over the via in order to obtain a very small layout area, such as a common embedded read-only memory. When it is desired to realize connection of the metal line 13 to the metal line 21, it is necessary to provide a metal connection pattern 35 in the metal interconnect layer of the layout data file, the metal connection pattern 35 electrically connecting the metal line 13 to the metal line 21 through the via hole 33. However, during actual production, because the method is limited by the precision of the photomask machine of the foundry, the photomask production formula and the limitation of the actual production flow, the metal connection pattern may overflow, for example, in combination with fig. 2A and fig. 2B, during production, the metal connection pattern 35' overflows compared with the metal connection pattern 35 in the layout data file, and contacts with the adjacent through holes 32, so that a certain yield risk exists, which can be found only by manual visual inspection during verification of the photomask platemaking file, and the efficiency and the finding probability are very low.
Disclosure of Invention
The invention aims to solve the technical problem of low yield in the prior art and provides a semiconductor chip and a layout design method and device thereof.
The technical scheme adopted for solving the technical problems is as follows: a layout design method for constructing a semiconductor chip comprises the following steps:
obtaining a layout data file of a semiconductor chip, and extracting a through hole layer file containing through hole information from the layout data file;
generating a metal interconnection layer file according to the through hole information in the through hole layer file;
adding corresponding additional metal patterns in the region corresponding to at least one through hole in the metal interconnection layer file;
and generating a metal connection pattern in the metal interconnection layer file according to the user requirement.
Preferably, the positions of the additional metal patterns are the same as the positions of the corresponding through holes.
Preferably, the additional metal pattern is identical to the shape of the corresponding via hole.
Preferably, the additional metal pattern is the same size as the corresponding via hole.
Preferably, adding a corresponding additional metal pattern in a region corresponding to the at least one through hole includes:
and performing scaling processing in a specific proportion according to the size of the corresponding through hole, performing translation processing in a specific proportion according to the position of the corresponding through hole, performing transformation processing in a specific proportion according to the shape of the corresponding through hole, and adding corresponding additional metal patterns according to the processing result.
The invention also constructs a layout design device of the semiconductor chip, which comprises a memory and a processor, wherein the processor is used for realizing the steps of the layout design method when executing the computer program stored in the memory.
The present invention also constructs a semiconductor chip fabricated using the above layout design method, including a metal interconnect layer including:
at least one additional metal pattern disposed on a region corresponding to the at least one via hole; a kind of electronic device with high-pressure air-conditioning system
And generating a metal connection graph according to the requirements of the user.
Preferably, the positions of the additional metal patterns are the same as the positions of the corresponding through holes; or alternatively, the first and second heat exchangers may be,
the shape of the additional metal pattern is the same as that of the corresponding through hole; or alternatively, the first and second heat exchangers may be,
the additional metal pattern is the same size as the corresponding via hole.
Preferably, there is a scaling of the size of the additional metal pattern with respect to the size of the corresponding via hole or a translation of the position of the additional metal pattern with respect to the position of the corresponding via hole with a characteristic ratio or a particular transformation of the shape of the additional metal pattern with respect to the shape of the corresponding via hole.
By implementing the technical scheme of the invention, the additional metal patterns are generated on the metal interconnection layer based on the existing through hole information, and the additional metal patterns can be used for solving the problem of metal overflow caused by foundry reasons, so that the failure problem caused by the metal overflow can be avoided, and the yield of the semiconductor chip is ensured. This technique is widely used, for example, the layout design of the above-mentioned embedded read-only memory ROM, the layout design of the chip version number, and the like.
Drawings
In order to more clearly illustrate the embodiments of the present invention, the drawings that are required for the description of the embodiments will be briefly described below, it being apparent that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art. In the accompanying drawings:
FIG. 1 is a schematic layout of a semiconductor chip;
FIG. 2A is a schematic illustration of a metal connection pattern in the area A of FIG. 1 under normal conditions;
FIG. 2B is a schematic illustration of the metal connection pattern in the event of metal overflow in area A of FIG. 1;
FIG. 3 is a flow chart of a layout design method of a semiconductor chip according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the layout of FIG. 1 with additional metal patterns added thereto;
fig. 5 is a schematic layout diagram after the metal connection pattern is generated in fig. 1.
Detailed Description
Fig. 3 is a flowchart of a layout design method of an embodiment of a semiconductor chip of the present invention, the layout design method of the embodiment comprising the steps of:
s11, obtaining a layout data file of a semiconductor chip, and extracting a through hole layer file containing through hole information from the layout data file;
in this step, after a layout data file (GDS) file is acquired, a via layer file including information of positions, shapes, sizes, and the like of all vias may be extracted.
S12, generating a metal interconnection layer file according to the through hole information in the through hole layer file;
s13, adding corresponding additional metal patterns in the region corresponding to the through hole in the metal interconnection layer file;
in this step, respective additional metal patterns are added in the metal interconnect layer in the areas corresponding to all vias (whether or not connection is required). In connection with fig. 4, for the vias 31, 32, 33, 34, whether or not they need to be connected, additional metal patterns need to be added on the corresponding areas in the metal interconnection layer, however, in other embodiments, additional metal patterns may be added only for the areas corresponding to one or a part of the vias.
And S14, generating a metal connection pattern in the metal interconnection layer file according to the user requirement.
In this step, the vias and metal lines connected as needed complement the corresponding metal connection patterns. Referring to fig. 5, if it is necessary to connect the metal line 21 with the metal line 13, a metal connection pattern 35 may be added; if it is desired to connect the metal line 22 to the metal line 12, a metal connection pattern 36 may be added.
By implementing the technical scheme of the embodiment, the additional metal patterns are generated on the metal interconnection layer based on the existing through hole information, and the additional metal patterns can be used for solving the problem of metal overflow caused by foundry reasons, so that the failure problem caused by the metal overflow can be avoided, and the yield of the semiconductor chip is ensured.
In a preferred embodiment, the positions of the additional metal patterns are the same as the positions of the corresponding vias. It should be understood that the location refers to a location on a plane formed by the superposition of the metal interconnect layer where the additional metal pattern is located and the via layer where the via is located.
In a preferred embodiment, the additional metal patterns are the same shape as the corresponding vias, e.g., are all square.
In a preferred embodiment, the additional metal pattern is the same size as the corresponding via.
In a preferred embodiment, in step S13, adding a corresponding additional metal pattern in the region corresponding to the via hole includes:
and performing scaling treatment of a specific proportion according to the size of the through hole, or performing translation treatment of a specific proportion according to the position of the through hole, or performing specific transformation treatment according to the shape of the through hole, and adding a corresponding additional metal pattern according to a treatment result.
In this embodiment, the position of the additional metal pattern is slightly deviated from the position of the corresponding via hole, or the size of the additional metal pattern is slightly larger or smaller than the corresponding via hole, or the shape of the additional metal pattern is approximately changed with respect to the shape of the via hole.
The invention also constructs a layout design device of the semiconductor chip, which comprises a memory and a processor, wherein the processor is used for realizing the steps of the layout design method when executing the computer program stored in the memory. The layout design device can be applied to an EDA tool.
The present invention also constructs a semiconductor chip manufactured using the layout design method of the above-described embodiments, and the semiconductor chip includes a metal interconnection layer, and the metal interconnection layer includes at least one additional metal pattern and a metal connection pattern, wherein the at least one additional metal pattern is disposed on a region corresponding to the at least one corresponding via hole, and the metal connection pattern is generated according to a user's demand.
In a preferred embodiment, the positions of the additional metal patterns are the same as the positions of the corresponding through holes; or, the additional metal pattern is the same as the shape of the corresponding via hole; or, the additional metal pattern is the same as the size of the corresponding through hole.
In a preferred embodiment, there is a scaling of the size of the additional metal pattern relative to the size of the via or a translation of the location of the additional metal pattern relative to the location of the via with a characteristic ratio or a specific transformation of the shape of the additional metal pattern relative to the shape of the via, such that the location of the additional metal pattern is slightly offset from the location of the corresponding via or the additional metal pattern is slightly larger or smaller than the corresponding via or the shape of the additional metal pattern is approximately transformed relative to the shape of the corresponding via.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any such modifications, equivalents, and improvements that fall within the spirit and principles of the present invention are intended to be covered by the following claims.
Claims (7)
1. A layout design method of a semiconductor chip is characterized by comprising the following steps:
obtaining a layout data file of a semiconductor chip, and extracting a through hole layer file containing through hole information from the layout data file;
generating a metal interconnection layer file according to the through hole information in the through hole layer file;
adding corresponding additional metal patterns in the region corresponding to at least one through hole in the metal interconnection layer file; performing scaling treatment of a specific proportion according to the size of the corresponding through hole, performing translation treatment of a specific proportion according to the position of the corresponding through hole, performing transformation treatment according to the shape of the corresponding through hole, and adding a corresponding additional metal pattern according to a treatment result;
and generating a metal connection pattern in the metal interconnection layer file according to the user requirement.
2. The layout design method of a semiconductor chip according to claim 1, wherein,
the positions of the additional metal patterns are the same as the positions of the corresponding through holes.
3. The layout design method of a semiconductor chip according to claim 1, wherein the additional metal pattern is identical to the shape of the corresponding via hole.
4. The layout design method of a semiconductor chip according to claim 1, wherein,
the additional metal pattern is the same size as the corresponding via hole.
5. A layout design apparatus for a semiconductor chip, comprising a memory and a processor for implementing the steps of the layout design method according to any one of claims 1-4 when executing a computer program stored in the memory.
6. A semiconductor chip fabricated using the layout design method of claim 1, comprising a metal interconnect layer, and wherein the metal interconnect layer comprises:
at least one additional metal pattern disposed on a region corresponding to the at least one via hole; a kind of electronic device with high-pressure air-conditioning system
And generating a metal connection graph according to the requirements of the user.
7. The semiconductor chip of claim 6, wherein the semiconductor chip comprises a plurality of semiconductor chips,
the positions of the additional metal patterns are the same as the positions of the corresponding through holes; or, the additional metal pattern is the same as the shape of the corresponding via hole; or alternatively, the first and second heat exchangers may be,
the additional metal pattern is the same size as the corresponding via hole.
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| CN201810845616.7A CN110852029B (en) | 2018-07-27 | 2018-07-27 | Semiconductor chip and layout design method and device thereof |
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| CN103049611A (en) * | 2012-12-21 | 2013-04-17 | 西安华芯半导体有限公司 | Identifiable chip and method for adding graphs for same |
| CN104091800A (en) * | 2014-07-25 | 2014-10-08 | 上海华力微电子有限公司 | Forming method for SRAM detection structure map |
| CN104091769A (en) * | 2014-07-25 | 2014-10-08 | 上海华力微电子有限公司 | Method for detecting etching insufficiency of through hole |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7759787B2 (en) * | 2007-11-06 | 2010-07-20 | International Business Machines Corporation | Packaging substrate having pattern-matched metal layers |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2007273871A (en) * | 2006-03-31 | 2007-10-18 | Toshiba Corp | Method and program for generating design data, and manufacturing method of semiconductor device |
| CN101290904A (en) * | 2007-04-20 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Method for correcting layout design for correcting metallic coating of contact hole |
| CN101533811A (en) * | 2008-03-13 | 2009-09-16 | 力成科技股份有限公司 | Structure of semiconductor chip with silicon through hole and stacking assembly thereof |
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