JP2004253655A - Method and program of timing verification - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timing verification method wherein the influence of a dummy metal can be surely taken into account in a design stage regardless of an actually generated pattern of the dummy metal. <P>SOLUTION: The verification method includes the following stages that a first RC information is extracted from layout information on the basis of a first RC extraction rule corresponding to a case when the number of dummy metals is a maximum, a second RC information is extracted from a layout information on the basis of a second RC extraction rule corresponding to a case when the number of dummy metals is a minimum, a first timing verification is conducted on the basis of the first RC information, a second timing verification is conducted on the basis of the second RC information, and the layout is judged according to a result obtained from the first and second timing verifications. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to timing verification in layout design of a semiconductor device, and more particularly to timing verification in layout design of a semiconductor device into which a dummy metal is inserted.
[Prior art]
In the case of manufacturing a large-scale semiconductor integrated circuit, if the wiring density greatly differs depending on the position on the substrate, the optimum etching conditions differ depending on the position, and there is a problem that the effect of the etching process is not uniform. As a result, when the wiring density is low, the resist disappears to cause disconnection, or the wiring width is narrowed and constricted, resulting in a remarkable increase in wiring resistance. Also, there is a possibility that the wiring may fall down in a greatly constricted place.
[0002]
In order to prevent this and to etch wirings of various thicknesses with desired accuracy, it is necessary to set the area ratio of the resist pattern to the wafer area at an appropriate predetermined ratio. Therefore, in a portion where the area ratio of the wiring pattern to the wafer region is small, the area ratio of the resist pattern is set to be substantially constant regardless of the portion on the wafer by inserting a dummy metal (dummy pattern).
[0003]
FIG. 1 is a diagram illustrating a process of automatically generating a dummy metal pattern.
[0004]
In LSI design such as ASIC, a floating dummy metal is generally automatically generated after design. As shown in FIG. 1, a staggered pattern 11 composed of a plurality of square dummy metals 10 is superimposed on a wiring pattern 12, and a dummy metal is not arranged at a position where the wiring pattern 12 exists and in the vicinity thereof, thereby forming a square pattern. The dummy metal 10 is generated. This automatic generation processing is executed by superimposing the zigzag pattern 11 on the coordinate system of the wafer after the completion of the logic design and the layout design.
[0005]
If the square dummy metals 10 are regularly arranged in a grid pattern, the difference between the case where a large amount of dummy metal occurs and the case where a small amount of the dummy metal occurs between the wirings is remarkable according to the relative positional relationship between the wiring pattern and the grid pattern. And a large variation occurs in the number of square dummy metals 10. On the other hand, if a zigzag pattern as shown in FIG. 1 is used, there is little difference between a case where a large amount of dummy metal is generated and a case where a small amount of dummy metal is generated between wirings, and a uniform pattern can be generated.
[0006]
However, since the relative positional relationship between the staggered pattern 11 and the wiring pattern 12 in the coordinate system on the wafer is not known at the design stage, it is necessary to grasp how the dummy metal is actually inserted at the design stage. Can not.
[0007]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2002-149739 [Problems to be Solved by the Invention]
Since the generated dummy metal is coupled to the circuit wiring as a parasitic capacitance, the performance may be degraded due to the RC delay. Therefore, it is desirable to design the timing in consideration of the parasitic capacitance of the dummy metal at the design stage. However, as described above, it is not possible to know the actual occurrence pattern at the design stage. Even if it can be known, it is not realistic to perform RC (resistance and capacitance) extraction in consideration of each dummy metal because the dummy metal has a huge data amount.
[0008]
Conventionally, an RC extraction rule is created assuming a dummy metal insertion amount corresponding to a wiring interval, and timing verification is executed based on the RC extraction rule. In this method, since the influence of the dummy metal cannot be accurately considered, it is necessary to secure a margin for the influence. As a result, the conditions are stricter than the actual conditions for the entire net, and there is a problem that it is difficult to adjust the timing in the layout.
[0009]
Further, it is also possible to provide a shield made of wiring connected to a power supply or the like in advance at the layout stage to suppress the influence of the dummy metal. However, this method is applied to only some critical nets because the number of layout steps increases.
[0010]
As another method, Patent Document 1 discloses a method of extracting a parasitic element in consideration of the degree of wiring congestion. However, this method performs an average calculation based on the degree of wiring congestion, and cannot completely guarantee the effect of the dummy metal generation in accordance with the individual wiring intervals. Therefore, there is a need for a timing verification method that can accurately guarantee the effect of the dummy metal on timing.
[0011]
In view of the above, an object of the present invention is to provide a timing verification method capable of reliably considering the influence of a dummy metal at a design stage regardless of a pattern of a dummy metal actually generated. .
[Means for Solving the Problems]
According to a timing verification method for a semiconductor integrated circuit layout according to the present invention, first RC information is extracted from layout information based on a first RC extraction rule corresponding to a case where the number of dummy metals is maximum, and the number of dummy metals is reduced. The second RC information is extracted from the layout information based on the second RC extraction rule corresponding to the minimum case, the first timing verification is performed based on the first RC information, and the second RC information is extracted. , A second timing verification is performed on the basis of the first timing verification and the second timing verification, and a layout determination is performed based on the results of both the first timing verification and the second timing verification.
[0012]
In the above timing verification method, RC extraction rules are set for both the maximum number and the minimum number of generated dummy metals, and the RC extraction from the target layout is performed for both the maximum and minimum cases of the dummy effect. By performing timing verification, the layout is determined while determining whether or not there is a timing problem with respect to the upper and lower limits of the influence of the dummy. Therefore, no matter what arrangement of actually generated dummy metals, the layout design of a logic circuit that can operate reliably can be performed. In addition, by setting RC extraction rules in advance for the case where the dummy effect is the maximum and the case where the dummy effect is the minimum, efficient processing can be realized without calculating the dummy metal and the capacitance coupling for each wiring layout. can do.
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0013]
In the present invention, as a RC extraction rule for extracting a resistance and a capacitance, a rule indicating a coupling capacitance when a maximum number of dummy metals are inserted and a minimum And a rule indicating the coupling capacity when the dummy metal is inserted. The rule when the maximum number of dummy metals is inserted is a rule with a large effect of the dummy metal, and the rule when a minimum number of dummy metals is inserted is a rule with a small effect of the dummy metal.
[0014]
Using the rule for maximum dummy influence and the RC extraction rule for minimum dummy effect created for each of a plurality of different wiring intervals in this manner, RC extraction is performed on the wiring pattern to be subjected to timing verification. Thereby, the wiring RC information under the condition of the maximum dummy influence and the wiring RC information under the condition of the minimum dummy effect are obtained. For each of the wiring RC information, the timing when the condition such as the driving capability of the transistor is the best and the timing when the condition is the worst are calculated.
[0015]
Under both the condition of the maximum dummy influence and the condition of the minimum dummy effect, it is determined whether or not there is a timing problem. If there is a problem, the layout is corrected and the timing calculation is executed again. When there is no problem under both the condition with the maximum dummy effect and the condition with the minimum dummy effect, the layout at that time is determined as the final result of the layout design.
[0016]
As described above, according to the present invention, RC extraction rules are set for both the maximum number and the minimum number of generated dummy metals, and the RC layout is set based on the target layout for both the maximum and minimum dummy effects. By extracting and verifying the timing, the layout is determined while determining whether or not there is a timing problem with respect to the upper and lower limits of the influence of the dummy. Therefore, no matter what arrangement of actually generated dummy metals, the layout design of a logic circuit that can operate reliably can be performed. In addition, by setting RC extraction rules in advance for the case where the dummy effect is the maximum and the case where the dummy effect is the minimum, efficient processing can be realized without calculating the dummy metal and the capacitance coupling for each wiring layout. can do.
[0017]
FIG. 2 is a diagram for explaining a case where a maximum number of dummy metals are generated between wirings at a predetermined interval and a case where a minimum number of dummy metals are generated.
[0018]
As described above, a rule indicating the coupling capacitance when the maximum number of dummy metals are inserted and a rule indicating the coupling capacitance when the minimum number of dummy metals are inserted are created in advance for a predetermined wiring interval. . To this end, it is necessary to calculate the coupling capacitance by performing the capacitance analysis for the case where the maximum number of dummy metals is generated and the case where the minimum number of dummy metals are generated for a predetermined wiring interval.
[0019]
It is assumed that two wires 20 and 21 arranged at an interval S are provided as shown in FIG. When the square dummy metal 10 arranged in a staggered pattern is generated between the wirings 20 and 21, the square dummy metal 10 is not generated near the wiring within a distance L from the wiring. Further, the length of one side of the square dummy metal 10 is W, and the shift (arrangement pitch) between the square dummy metals 10 adjacent to each other in the direction perpendicular to the wiring is D. In this case, the maximum number Nmax and the minimum number Nmin of the dummy metal are:
Nmax = (S−2L−W) / D + 1
Nmin = (S-2L-W) / D
It becomes. In the above equation, the fractional part is omitted.
[0020]
In order to maximize the number of generated dummy metals, a reference point for generating a dummy pattern is set at a position separated from the wiring 20 by a distance L, and Nmax squares are set based on a dummy pattern generation rule for realizing a staggered pattern. The dummy metal 10 is generated. After that, by conducting a capacitance analysis, a coupling capacitance in consideration of the square dummy metal 10 is obtained for the wiring at the interval S. Thus, in the case where wirings of a predetermined width are arranged at the interval S in the same wiring layer, an RC extraction rule under the condition of the maximum dummy influence is obtained.
[0021]
In order to minimize the number of generated dummy metals, a reference point for generating a dummy pattern is set at a position separated from the wiring 21 by a distance L, and Nmin squares are set based on a dummy pattern generation rule for realizing a staggered pattern. The dummy metal 10 is generated. After that, by conducting a capacitance analysis, a coupling capacitance in consideration of the square dummy metal 10 is obtained for the wiring at the interval S. As a result, in the case where wirings having a predetermined width are arranged at intervals S in the same wiring layer, an RC extraction rule with the condition of the minimum dummy influence is obtained.
[0022]
When the wiring interval S is sufficiently small, the square dummy metal 10 may not be generated at all. In this case, the coupling capacity of the RC extraction rule with the maximum dummy effect is the same as the coupling capacity of the RC extraction rule with the minimum dummy effect. If the wiring interval S is sufficiently large, a large number of square dummy metals 10 will be generated. In this case, there is no large difference between the coupling capacity of the RC extraction rule having the largest dummy effect and the coupling capacity of the RC extraction rule having the smallest dummy effect.
[0023]
FIG. 3A is an example of an RC extraction rule with a minimum dummy effect, and FIG. 3B is an example of an RC extraction rule with a maximum dummy effect.
[0024]
As shown in FIGS. 3A and 3B, the RC extraction rule is that, for example, in the same wiring layer METAL1, two wirings are arranged at intervals of 0.3, 0.9, 1.5, 2.1. The coupling capacity is specified for each of the intervals of 2.7 and 2.7.
[0025]
Generally, an RC extraction rule is created by analyzing a basic wiring model using a tool called a field solver. In the RC extraction rule, information such as a fringe capacitance component in addition to the coupling capacitance component is described according to conditions such as a wiring interval, a wiring width, and a wiring layer. In the present invention, as shown in FIG. 3, an RC extraction rule with the maximum effect of the dummy metal and an RC extraction rule with the minimum effect of the dummy metal are created.
[0026]
As can be seen by comparing FIGS. 3A and 3B, when the two wirings are arranged at intervals of 0.3, the coupling capacitance is 100 and the same. This corresponds to the case where the square dummy metal 10 is not generated at all, as described above. When the two wirings are at 2.7 intervals, the coupling capacitance is 25 and the same. This corresponds to the case where a large number of square dummy metals 10 are generated as described above. At wiring intervals other than these two, the coupling capacitance of the RC extraction rule with the minimum dummy effect of (a) is smaller than the coupling capacitance of the RC extraction rule with the maximum dummy effect of (b). ing.
[0027]
FIG. 4 is a flowchart showing the procedure of the timing verification method according to the present invention.
[0028]
After the logic design of the circuit to be designed is completed, the layout of the circuit to be designed is created by determining the arrangement of the cells constituting the circuit and the wiring between the cells (step ST1). Thereby, layout data is generated. This layout data is data relating to the arrangement of each cell and wiring between cells.
[0029]
In step ST2, the resistance and capacitance of the wiring are extracted and the RC information is generated based on the RC extraction rule with the minimum dummy effect obtained as described above. The RC information is obtained by alternately connecting a series of resistors R and capacitors C, and is used to calculate a delay of a target wiring. The RC information is generated, for example, in the SPEF format, which is an industry standard RC description file.
[0030]
In step ST3, the timing of the circuit to be designed is verified. This timing verification includes delay calculation and delay determination. In the delay calculation, a signal delay is calculated for the entire circuit in consideration of a delay of each circuit element (cell) in a logic circuit and a delay of a wiring between each circuit element. In the delay determination, based on the result obtained by the delay calculation, it is checked whether or not there is a circuit part having a timing problem such as a delay larger than a desired value. Specifically, the delay calculation is performed for both the case where the conditions such as the driving capability of each circuit element are the best and the case where those conditions are the worst, and the delay determination is performed for both the best case and the worst case. I do.
[0031]
Further, in step ST4, the resistance and the capacitance of the wiring are extracted and the RC information is generated based on the RC extraction rule having the maximum dummy influence obtained as described above. Since the influence of the dummy metal is the largest, the coupling capacity of the extracted RC information is larger than in the case of step ST2.
[0032]
In step ST5, the timing of the circuit to be designed is verified. Similar to the case of step ST3, in the delay calculation, the delay of each cell and the delay of each wiring are calculated for the entire circuit, and in the delay determination, there is a problem in timing based on the result obtained in the delay calculation. Check if the circuit part exists.
[0033]
In step ST6, a determination is made on the timing verification result of the current layout. That is, it is determined whether or not there is an error in the verification result for both the timing verification result in step ST3 when the dummy effect is minimum and the timing verification result in step ST5 when the dummy effect is maximum. If there is a problem, the layout is corrected, and the RC extraction process and the timing verification and determination are executed again. When there is no problem in the determination in step ST6, the layout at that time is set as a final result, and the process ends.
[0034]
As described above, the timing verification and the layout change are repeated, and the layout is converged so that there is no problem in timing.
[0035]
In the above timing verification, the RC extraction rules prepared for both the maximum number and the minimum number of dummy metals are used to extract the RC from the target layout for both the maximum case and the minimum case of the dummy effect. By performing timing verification, the layout is determined while judging whether or not there is a timing problem with respect to the upper and lower limits of the influence of the dummy. Therefore, no matter what arrangement of actually generated dummy metals, the layout design of a logic circuit that can operate reliably can be performed. In addition, by setting RC extraction rules in advance for the case where the dummy effect is the maximum and the case where the dummy effect is the minimum, efficient processing can be realized without calculating the dummy metal and the capacitance coupling for each wiring layout. can do.
[0036]
FIG. 5 is a diagram showing a configuration of an apparatus for executing the processing of the timing verification method according to the present invention.
[0037]
As shown in FIG. 5, an apparatus for executing the timing verification method according to the present invention is realized by a computer such as a personal computer or an engineering workstation. 5 includes a computer 510, a display device 520 connected to the computer 510, a communication device 523, and an input device. The input device includes, for example, a keyboard 521 and a mouse 522. The computer 510 includes a CPU 511, a RAM 512, a ROM 513, a secondary storage device 514 such as a hard disk, a replaceable medium storage device 515, and an interface 516.
[0038]
The keyboard 521 and the mouse 522 provide an interface with the user, and input various commands for operating the computer 510, a user response to requested data, and the like. The display device 520 displays a result processed by the computer 510 and the like, and performs various data displays to enable a dialogue with a user when operating the computer 510. The communication device 523 performs communication with a remote place, and includes, for example, a modem and a network interface.
[0039]
The timing verification method according to the present invention is provided as a computer program executable by the computer 510. This computer program is stored in a storage medium M that can be mounted on the exchangeable medium storage device 515, and is loaded from the storage medium M to the RAM 512 or the secondary storage device 514 via the exchangeable medium storage device 515. Alternatively, the computer program is stored in a storage medium (not shown) at a remote location, and is loaded from the storage medium to the RAM 512 or the secondary storage device 514 via the communication device 523 and the interface 516.
[0040]
When a program execution instruction is issued from the user via the keyboard 521 and / or the mouse 522, the CPU 511 loads the program from the storage medium M, the remote storage medium, or the secondary storage device 514 to the RAM 512. The CPU 511 uses the free storage space of the RAM 512 as a work area, executes the program loaded in the RAM 512, and proceeds with the process while appropriately interacting with the user. The RAM 512 or the secondary storage device 514 stores layout information relating to cell arrangement positions and the like. Note that a control program for controlling the basic operation of the computer 510 is stored in the ROM 513.
[0041]
By executing the computer program, the timing verification method is executed as described in the above embodiment.
[0042]
As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the claims.
【The invention's effect】
In the timing verification method described above, an RC extraction rule is provided for both the maximum number and the minimum number of generated dummy metals, and both the maximum and the minimum dummy effects are determined from the target layout. By extracting RC and performing timing verification, the layout is determined while judging whether or not there is a timing problem with respect to the upper and lower limits of the influence of the dummy. Therefore, no matter what arrangement of actually generated dummy metals, the layout design of a logic circuit that can operate reliably can be performed.
[0043]
Also, by setting RC extraction rules in advance for the case where the dummy effect is the largest and the case where the dummy effect is the smallest, efficient processing can be realized without performing calculation of dummy metal and capacitance coupling for each wiring layout. can do.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a process of automatically generating a dummy metal pattern.
FIG. 2 is a diagram for explaining a case where a maximum number of dummy metals are generated between wirings at a predetermined interval and a case where a minimum number of dummy metals are generated.
3A is an example of an RC extraction rule with a minimum dummy effect, and FIG. 3B is an example of an RC extraction rule with a maximum dummy effect.
FIG. 4 is a flowchart showing a procedure of a timing verification method according to the present invention.
FIG. 5 is a diagram showing a configuration of an apparatus that executes processing of a timing verification method according to the present invention.
[Explanation of symbols]
10 Square dummy metal 11 Staggered pattern 12 Wiring patterns 20, 21 Wiring

Claims (10)

Extracting the first RC information from the layout information based on the first RC extraction rule corresponding to the case where the number of dummy metals inserted between the wiring patterns is the largest;
Extracting second RC information from the layout information based on a second RC extraction rule corresponding to the case where the number of the dummy metals is a minimum,
Performing a first timing verification based on the first RC information;
Performing a second timing verification based on the second RC information;
A timing verification method for a semiconductor integrated circuit layout, comprising: a step of determining a layout based on results of both the first timing verification and the second timing verification. The method further includes generating the first RC extraction rule corresponding to the case where the number of the dummy metals is the maximum, and generating the second RC extraction rule corresponding to the case where the number of the dummy metals is the minimum. The timing verification method according to claim 1, wherein: Generating the first RC extraction rule includes:
Generate the maximum number of dummy metals between wiring patterns at predetermined intervals,
Generating each of the second RC extraction rules includes a step of obtaining a coupling capacitance between the wiring patterns in consideration of the maximum number of dummy metals;
Generating a minimum number of dummy metals between the wiring patterns at the predetermined interval;
3. The timing verification method according to claim 2, further comprising the steps of obtaining a coupling capacitance between the wiring patterns in consideration of the minimum number of dummy metals. 4. The timing verification method according to claim 1, wherein the dummy metals are arranged in a staggered pattern. Each of the step of performing the first timing verification and the step of performing the second timing verification execute a timing calculation when the timing is the worst and a timing calculation when the timing is the best. The timing verification method according to claim 1. Extracting the first RC information from the layout information based on the first RC extraction rule corresponding to the case where the number of dummy metals inserted between the wiring patterns is the largest;
Extracting second RC information from the layout information based on a second RC extraction rule corresponding to the case where the number of the dummy metals is a minimum,
Performing a first timing verification based on the first RC information;
Performing a second timing verification based on the second RC information;
A timing verification program for a semiconductor integrated circuit layout, comprising: controlling a computer to execute each step of determining a layout based on the results of both the first timing verification and the second timing verification. The method further includes generating the first RC extraction rule corresponding to the case where the number of the dummy metals is the maximum, and generating the second RC extraction rule corresponding to the case where the number of the dummy metals is the minimum. The timing verification program according to claim 6, wherein: Generating the first RC extraction rule includes:
Generate the maximum number of dummy metals between wiring patterns at predetermined intervals,
Generating each of the second RC extraction rules includes a step of obtaining a coupling capacitance between the wiring patterns in consideration of the maximum number of dummy metals;
Generating a minimum number of dummy metals between the wiring patterns at the predetermined interval;
8. The timing verification program according to claim 7, further comprising each step of obtaining a coupling capacitance between the wiring patterns in consideration of the minimum number of dummy metals. 9. The timing verification program according to claim 6, wherein the dummy metals are arranged in a staggered pattern. Each of the step of performing the first timing verification and the step of performing the second timing verification execute a timing calculation when the timing is the worst and a timing calculation when the timing is the best. A timing verification program according to claim 6.

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