CN112232013A - OPC treatment method for improving coverage rate between metal layer and through hole layer - Google Patents
OPC treatment method for improving coverage rate between metal layer and through hole layer Download PDFInfo
- Publication number
- CN112232013A CN112232013A CN202010833535.2A CN202010833535A CN112232013A CN 112232013 A CN112232013 A CN 112232013A CN 202010833535 A CN202010833535 A CN 202010833535A CN 112232013 A CN112232013 A CN 112232013A
- Authority
- CN
- China
- Prior art keywords
- layout
- layer
- coverage
- coverage rate
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000012545 processing Methods 0.000 claims abstract description 35
- 230000003321 amplification Effects 0.000 claims abstract description 6
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 6
- 238000003672 processing method Methods 0.000 claims description 17
- 238000012937 correction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 238000012546 transfer Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Architecture (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides an OPC treatment method for improving the coverage rate between a metal layer and a through hole layer, which comprises the following steps: inputting an original layout of a metal layer, and performing line width amplification processing on the original layout to obtain a first layout; carrying out de-bulging treatment and curvilinearization treatment on the first layout to obtain a second layout; calculating the coverage rate between the second layout and the through hole layer, and dividing the second layout into a plurality of regions according to the coverage rate; selecting convex angles with the distance between the first layout and the through hole layer being a set value and corresponding to each region of the second layout, and performing edge expansion processing with different amplitudes on the edges of the convex angles; combining the first layout and the first layout after the edge expanding treatment to obtain a third layout; and if the coverage rate between the third layout and the through hole layer reaches the standard, outputting the third layout. The third layout improves the coverage rate between the metal layer and the through hole layer, and meanwhile, the process window of the space between the metal lines cannot be reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an OPC (optical proximity correction) processing method for improving the coverage rate between a metal layer and a through hole layer.
Background
The connection of the back-end metal layer and the through hole layer in the integrated circuit manufacturing process plays a crucial role in device performance, if the coverage rate of the metal layer and the through hole layer does not reach the standard, the conduction performance between different metal layers is poor, even the conduction performance is invalid, and finally the yield of products is reduced.
However, due to the existence of the Optical Proximity effect, there is a certain difference between the circuit layout design and the patterns actually produced on the wafer, and in the background of the rising of the technology nodes, the introduction of the Optical Proximity Correction (OPC) technology can compensate for this. The coverage rate of the convex angle position of the line end and the through hole layer is reduced due to the influence of the fillet effect in the metal layer layout design, the traditional correction method is to carry out uniform edge expansion on the edge where the convex angle is located, but the environments around the convex angle are different, lines at some places can be dense, and therefore the uniform edge expansion can reduce the process window of the Space (Space) between partial metal lines.
Disclosure of Invention
The invention aims to provide an OPC treatment method for improving the coverage rate between a metal layer and a through hole layer, which can improve the coverage rate between the metal layer and the through hole layer and simultaneously can not reduce a process window of a space between metal lines.
In order to achieve the above object, the present invention provides an OPC processing method for improving coverage between a metal layer and a via layer, comprising:
s11: inputting an original layout of a metal layer, and performing line width amplification processing on the original layout to obtain a first layout;
s12: carrying out de-bulging treatment and curvilinearization treatment on the first layout to obtain a second layout;
s13: calculating the coverage rate between the second layout and the through hole layer, and dividing the second layout into a plurality of regions according to the coverage rate;
s14: selecting convex angles with the distance between the first layout and the through hole layer being a set value and corresponding to each region of the second layout, and performing edge expansion processing with different amplitudes on the edges of the convex angles;
s15: combining the first layout and the first layout after the edge expanding treatment to obtain a third layout;
s16: and if the coverage rate between the third layout and the through hole layer reaches the standard, outputting the third layout.
Optionally, in the OPC processing method for improving the coverage between the metal layer and the via layer, if the coverage between the third layout and the via layer does not meet the standard, the steps S13, S14, S15, and S16 are repeated until the coverage meets the standard.
Optionally, in the OPC processing method for improving the coverage between the metal layer and the via layer, in S16, the method for determining that the coverage meets the standard is that the coverage is at least 95%.
Optionally, in the OPC processing method for improving the coverage between the metal layer and the via layer, performing de-bumping processing and profiling processing on the first layout includes:
and carrying out de-bulging treatment on the first layout, and then carrying out curvilinearization treatment.
Optionally, in the OPC processing method for improving the coverage between the metal layer and the via layer, performing a de-protrusion process on the first layout includes:
and convex shapes are arranged on the edges of the lines of the removed first layout, so that the edges of the lines are straight lines.
Optionally, in the OPC processing method for improving the coverage between the metal layer and the via layer, the method for performing the curve processing includes:
the control points are arranged on the lines subjected to the de-bulging treatment, and the connecting lines between the control points are pulled to enable the right-angle lines of the first layout to be changed into curve lines.
Optionally, in the OPC processing method for improving the coverage between the metal layer and the via layer, the plurality of regions include: a first region, a second region, and a third region; the coverage rate between the first region and the via layer is less than 80%; the coverage rate between the second region and the through hole layer is 80% -90%; and the coverage rate between the third region and the through hole layer is 90-95%.
Optionally, in the OPC processing method for improving the coverage between the metal layer and the via layer, a convex angle, of which the distance between the first layout and the via layer is a set value, corresponding to each region of the second layout is selected, and the method of performing edge expansion processing with different amplitudes on the edge of each convex angle includes:
selecting a convex angle with a distance between the first layout and the through hole layer corresponding to the first region as a set value, and carrying out edge expansion processing of a first amplitude on the edge of the convex angle; selecting a convex angle with a set value of the distance between the first layout and the through hole layer corresponding to the second region, and performing edge expansion processing of a second amplitude on the edge of the convex angle; and selecting a convex angle with a distance between the first layout and the through hole layer corresponding to the third area as a set value, and performing edge expansion processing of a third amplitude on the edge of the convex angle.
Optionally, in the OPC processing method for improving the coverage between the metal layer and the via layer, the first amplitude is 15nm, the second amplitude is 10nm, and the third amplitude is 5 nm.
Optionally, in the OPC processing method for improving the coverage between the metal layer and the via layer, the set value is a value of one third of the line width of the original layout.
In the OPC processing method for improving the coverage rate between the metal layer and the through hole layer, the original layout of the metal layer is processed to obtain a first layout and a second layout, the second layout is divided into a plurality of areas according to the coverage rate of the second layout and the through hole layer, the edges of convex angles, the distance between the first layout and the through hole layer, which correspond to each area, reaches a set value are respectively subjected to edge expansion with different amplitudes, the first layout and the first layout after edge expansion are fused to form a third layout, and the third layout is output, so that the coverage rate between the metal layer and the through hole layer is improved by the third layout, and meanwhile, a process window of the distance between metal wires cannot be reduced.
Drawings
FIG. 1 is a flow chart of a method of OPC processing to improve coverage between metal and via layers in an embodiment of the present invention;
fig. 2 to fig. 8 are layout diagrams of an OPC processing method for improving coverage between a metal layer and a via layer according to an embodiment of the present invention;
in the figure: 110-first layout, 110A-first layout after de-bulging processing, 111-bulge, 112-control point, 120-second layout, 121-first region, 122-second region, 123-third region, edge of 121A-convex angle, 130-through hole layer and 140-third layout.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
The communication between metal level and the metal level is by the via layer, if the coverage between via layer and the metal level, the coverage refers to the ratio of the coincidence area between via layer and metal level and via layer again. Therefore, if the coverage is too low, it proves that the overlapping area between the via layer and the metal layer is too low, which results in the connection performance between the metal layer and the metal layer being reduced, even the connection fails, and finally the yield of the product is reduced. The reason why the coverage rate is underground may be that, although the coverage rate on the original layout may reach the standard, when the metal wire is transferred onto the wafer, the moving direction of the transferred metal wire is changed due to the optical proximity effect, so that the coverage rate is changed. Therefore, the invention carries out OPC treatment before the transfer so as to lead the coverage rate after the transfer to reach the standard. From many experiments or experiences, most of the places where the coverage after transfer is not up to standard are the metal wire salient angle (corner) positions of the metal layer. In the prior art, the layout of the metal layer is subjected to uniform edge expansion, so that the coverage rate of the via layer and the metal layer is increased, however, the uniform edge expansion may cause that the distance between metal lines in some places is too small, and the subsequent process is influenced.
Referring to fig. 1, the present invention provides an OPC processing method for improving coverage between a metal layer and a via layer, comprising:
s11: inputting an original layout of a metal layer, and performing line width amplification processing on the original layout to obtain a first layout;
s12: carrying out de-bulging treatment and curvilinearization treatment on the first layout to obtain a second layout;
s13: calculating the coverage rate between the second layout and the through hole layer, and dividing the second layout into a plurality of regions according to the coverage rate;
s14: selecting convex angles with the distance between the first layout and the through hole layer being a set value and corresponding to each region of the second layout, and performing edge expansion processing with different amplitudes on the edges of the convex angles;
s15: combining the first layout and the first layout after the edge expanding treatment to obtain a third layout;
s16: and if the coverage rate between the third layout and the through hole layer reaches the standard, outputting the third layout.
Specifically, an original layout (not shown in the figure) of the metal layer is input, and the original layout is subjected to line width amplification to obtain a first layout 110, as shown in fig. 2. The original layout is formed by a plurality of layout patterns formed by a plurality of lines, and the lines have line widths, and in step S11, the line width amplification processing is performed on the original layout, which is the prior art and is not described herein again.
Next, the first layout 110 is subjected to a de-bulging 111 treatment, specifically, the shape of the bulge 111 on the edge of the line of the first layout 110 is removed within a certain range, so that the edge of the line is a straight line, and fig. 2 and fig. 3 are compared with each other, and fig. 3 is the first layout 110A after the de-bulging treatment. For example, there are some protrusions in the first version 110 that are particularly small in size, typically 2nm to 3nm in size, which can have an effect during OPC correction.
Next, referring to fig. 4, a curve processing is performed on the first layout 110A after the de-protrusion processing, specifically, the control points 112 are arranged on the lines after the de-protrusion processing, and the connection lines between the control points 112 are pulled to change the right-angle lines of the first layout 110 into curve lines, so as to obtain a second layout 120, as shown in fig. 5, it can be seen that the lines of the second layout 120 have been subjected to the curve processing. The pitch of the control points 112 is usually set to 50nm-80nm, and it is also the prior art to draw a straight line into a curved line, which is not described herein.
Next, referring to fig. 6, a via layer 130 is introduced into the second layout 120, and the coverage rates of the via layer 130 and the second layout 120 are calculated, that is, the ratio of the overlapping area between the via layer 130 and the second layout 120 to the via layer 130 is calculated, but because the via layer has a plurality of through holes, the coverage rates of the via layer and the second layout have a plurality of values, some coverage rates are larger, and some coverage rates are smaller, therefore, if the coverage rate does not reach the standard, the line width is uniformly amplified to increase the coverage rate, which may cause the distance between some lines to be too small, and the process window is affected. Therefore, the second layout is divided into a plurality of areas according to different coverage rates. Specifically, in the embodiment of the present invention, three regions are divided, that is, a first region 121, a second region 122, and a third region 123; the coverage between the first region 121 and the via layer is less than 80%; the coverage rate between the second region 122 and the via layer is 80% -90%; the coverage between the third region 123 and the via layer is 90% -95%. In other embodiments of the present invention, the coverage rate may be divided into more areas, and the coverage rate of each area may have other values.
Then, with reference to fig. 6, selecting a convex angle, the distance between which and the through hole layer in the first layout corresponding to each region of the second layout is a set value, and performing edge expansion processing with different amplitudes on the edge of each convex angle, that is, after the second layout is divided into three regions according to the coverage rate, in each region, calculating the distance between the first layout and the through hole layer, and if the nearest distance between the line edge of a certain convex angle of the first layout and the adjacent through hole layer reaches the set value, processing the edge of the convex angle. The set value may be one third of the line width of the original layout. For example, a convex angle with a set value of the distance between the first layout and the via layer corresponding to the first region 121 is selected, and edge expansion processing of a first amplitude is performed on the edge of the convex angle, wherein the first amplitude is 15 nm; selecting a convex angle with a set value of the distance between the first layout and the through hole layer corresponding to the second region 122, and performing edge expansion processing on the edge of the convex angle with a second amplitude of 10 nm; and selecting a convex angle with the distance between the first layout and the through hole layer corresponding to the third area 123 as a set value, and performing edge expansion processing on the edge of the convex angle with a third amplitude of 5 nm. It can also be seen that the coverage of the first area 121 is less than the coverage of the second area 122 and less than the coverage of the third area 123, and therefore the first amplitude is greater than the second amplitude, which is greater than the third amplitude. Selecting the first region as an example, as shown in fig. 7, if the nearest distance from the side 121A of the convex corner in the first region 121 to the via layer 130 reaches a set value, the side 121A of the convex corner is subjected to an edge expansion process, and the expanded amplitude is 15nm, i.e., the distance is 15nm outward. The methods for expanding the edges of other regions, such as the second region and the third region, are similar to those of the first region, and are not described herein again.
Then, referring to fig. 8, combining the first layout and the plurality of first layouts after the edge expanding processing to obtain a third layout 140; and if the coverage rate between the third layout and the through hole layer reaches the standard, outputting a third layout, and 140. Preferably, the method for judging the coverage rate to reach the standard is that the coverage rate reaches at least 95 percent. In other embodiments of the present invention, the coverage up to reach may be set to other values.
Further, if the coverage rate between the third layout and the via layer does not reach the standard, the steps S13, S14, S15 and S16 are continuously repeated until the coverage rate reaches the standard. Namely, if the coverage rate still does not reach the standard after the first OPC processing, the edge expanding processing is performed again until the coverage rate reaches the standard. The embodiment of the invention circulates the edge expansion for three times at most, and increases the processing time if the edge expansion is carried out for too many times, thereby influencing the efficiency.
In summary, in the OPC processing method for improving the coverage rate between the metal layer and the via layer according to the embodiment of the present invention, the original layout of the metal layer is processed to obtain the first layout and the second layout, the second layout is divided into a plurality of regions according to the coverage rate of the second layout and the via layer, the sides of the convex corners, where the distance between the first layout and the via layer corresponding to each region reaches the set value, are respectively subjected to edge expansion with different amplitudes, the first layout and the edge expanded first layout are fused to form the third layout, and the third layout is output.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. An OPC treatment method for improving coverage rate between a metal layer and a through hole layer is characterized by comprising the following steps:
s11: inputting an original layout of a metal layer, and performing line width amplification processing on the original layout to obtain a first layout;
s12: carrying out de-bulging treatment and curvilinearization treatment on the first layout to obtain a second layout;
s13: calculating the coverage rate between the second layout and the through hole layer, and dividing the second layout into a plurality of regions according to the coverage rate;
s14: selecting convex angles with the distance between the first layout and the through hole layer being a set value and corresponding to each region of the second layout, and performing edge expansion processing with different amplitudes on the edges of the convex angles;
s15: combining the first layout and the first layout after the edge expanding treatment to obtain a third layout;
s16: and if the coverage rate between the third layout and the through hole layer reaches the standard, outputting the third layout.
2. The OPC treatment method of claim 1 for improving coverage between the metal layer and the via layer, wherein if the coverage between the third layout and the via layer does not meet the standard, the steps S13, S14, S15 and S16 are repeated until the coverage meets the standard.
3. The OPC treatment method of claim 1 wherein the coverage is determined to be at least 95% at S16.
4. The OPC treatment method of claim 1 for improving coverage between a metal layer and a via layer wherein the de-bumping and the profiling of the first layout comprises:
and carrying out de-bulging treatment on the first layout, and then carrying out curvilinearization treatment.
5. The OPC treatment method of claim 4 wherein the first de-bumping of the first layout comprises:
and convex shapes are arranged on the edges of the lines of the removed first layout, so that the edges of the lines are straight lines.
6. The OPC treatment method of improving coverage between a metal layer and a via layer according to claim 5, wherein the method of performing the curvilinearization treatment comprises:
the control points are arranged on the lines subjected to the de-bulging treatment, and the connecting lines between the control points are pulled to enable the right-angle lines of the first layout to be changed into curve lines.
7. The OPC treatment method of claim 1 wherein the plurality of regions comprise: a first region, a second region, and a third region; the coverage rate between the first region and the via layer is less than 80%; the coverage rate between the second region and the through hole layer is 80% -90%; and the coverage rate between the third region and the through hole layer is 90-95%.
8. The OPC processing method for improving the coverage between a metal layer and a via layer according to claim 7, wherein the convex angle of which the distance from the first layout to the via layer is a set value and which corresponds to each region of the second layout is selected, and the method of performing the edge expansion processing of different amplitudes on the edge of each convex angle comprises:
selecting a convex angle with a distance between the first layout and the through hole layer corresponding to the first region as a set value, and carrying out edge expansion processing of a first amplitude on the edge of the convex angle; selecting a convex angle with a set value of the distance between the first layout and the through hole layer corresponding to the second region, and performing edge expansion processing of a second amplitude on the edge of the convex angle; and selecting a convex angle with a distance between the first layout and the through hole layer corresponding to the third area as a set value, and performing edge expansion processing of a third amplitude on the edge of the convex angle.
9. The OPC treatment method of claim 8 wherein the first amplitude is 15nm, the second amplitude is 10nm, and the third amplitude is 5 nm.
10. The OPC processing method of improving coverage between a metal layer and a via layer according to claim 1, wherein the set value is a value of one third of a line width of the original layout.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010833535.2A CN112232013A (en) | 2020-08-18 | 2020-08-18 | OPC treatment method for improving coverage rate between metal layer and through hole layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010833535.2A CN112232013A (en) | 2020-08-18 | 2020-08-18 | OPC treatment method for improving coverage rate between metal layer and through hole layer |
Publications (1)
Publication Number | Publication Date |
---|---|
CN112232013A true CN112232013A (en) | 2021-01-15 |
Family
ID=74116862
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010833535.2A Pending CN112232013A (en) | 2020-08-18 | 2020-08-18 | OPC treatment method for improving coverage rate between metal layer and through hole layer |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN112232013A (en) |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150114378A (en) * | 2014-04-01 | 2015-10-12 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Revising layout design through opc to reduce corner rounding effect |
JP2017021671A (en) * | 2015-07-13 | 2017-01-26 | Alitecs株式会社 | Design layout data correction method, design layout data correction program, and design layout data correction device |
CN106444273A (en) * | 2016-10-10 | 2017-02-22 | 上海华力微电子有限公司 | Addition and processing method of small-size redundant graphs for metal wire layers |
US20180070452A1 (en) * | 2016-09-06 | 2018-03-08 | Unimicron Technology Corp. | Manufacturing method of circuit substrate and mask structure and manufacturing method thereof |
CN107908893A (en) * | 2017-11-29 | 2018-04-13 | 上海华力微电子有限公司 | The domain processing method of missing technique hot spot at the top of a kind of metal layer photoresist |
CN109407460A (en) * | 2018-12-05 | 2019-03-01 | 上海华力集成电路制造有限公司 | Expose secondary graphics adding method |
CN109494185A (en) * | 2018-10-31 | 2019-03-19 | 上海华力微电子有限公司 | A kind of optical adjacent correction method optimizing via layer switching performance |
CN109614705A (en) * | 2018-12-12 | 2019-04-12 | 上海华力集成电路制造有限公司 | The generation method of metal layer device secondary graphics |
CN110058485A (en) * | 2019-05-09 | 2019-07-26 | 上海华力微电子有限公司 | OPC modification method and OPC update the system |
CN110852029A (en) * | 2018-07-27 | 2020-02-28 | 熠芯(珠海)微电子研究院有限公司 | Semiconductor chip and layout design method and device thereof |
CN110929470A (en) * | 2019-11-28 | 2020-03-27 | 上海华力微电子有限公司 | Layout optimization method |
CN111025841A (en) * | 2019-12-30 | 2020-04-17 | 上海集成电路研发中心有限公司 | Method for optimizing metal wire optical proximity correction process window |
US20200150530A1 (en) * | 2018-11-12 | 2020-05-14 | Beijing Boe Display Technology Co., Ltd. | Mask and method of manufacturing the same, evaporation apparatus and display device |
CN111199132A (en) * | 2019-12-30 | 2020-05-26 | 上海集成电路研发中心有限公司 | Method for adding metal redundant graph |
-
2020
- 2020-08-18 CN CN202010833535.2A patent/CN112232013A/en active Pending
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150114378A (en) * | 2014-04-01 | 2015-10-12 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Revising layout design through opc to reduce corner rounding effect |
JP2017021671A (en) * | 2015-07-13 | 2017-01-26 | Alitecs株式会社 | Design layout data correction method, design layout data correction program, and design layout data correction device |
US20180070452A1 (en) * | 2016-09-06 | 2018-03-08 | Unimicron Technology Corp. | Manufacturing method of circuit substrate and mask structure and manufacturing method thereof |
CN106444273A (en) * | 2016-10-10 | 2017-02-22 | 上海华力微电子有限公司 | Addition and processing method of small-size redundant graphs for metal wire layers |
CN107908893A (en) * | 2017-11-29 | 2018-04-13 | 上海华力微电子有限公司 | The domain processing method of missing technique hot spot at the top of a kind of metal layer photoresist |
CN110852029A (en) * | 2018-07-27 | 2020-02-28 | 熠芯(珠海)微电子研究院有限公司 | Semiconductor chip and layout design method and device thereof |
CN109494185A (en) * | 2018-10-31 | 2019-03-19 | 上海华力微电子有限公司 | A kind of optical adjacent correction method optimizing via layer switching performance |
US20200150530A1 (en) * | 2018-11-12 | 2020-05-14 | Beijing Boe Display Technology Co., Ltd. | Mask and method of manufacturing the same, evaporation apparatus and display device |
CN109407460A (en) * | 2018-12-05 | 2019-03-01 | 上海华力集成电路制造有限公司 | Expose secondary graphics adding method |
CN109614705A (en) * | 2018-12-12 | 2019-04-12 | 上海华力集成电路制造有限公司 | The generation method of metal layer device secondary graphics |
CN110058485A (en) * | 2019-05-09 | 2019-07-26 | 上海华力微电子有限公司 | OPC modification method and OPC update the system |
CN110929470A (en) * | 2019-11-28 | 2020-03-27 | 上海华力微电子有限公司 | Layout optimization method |
CN111025841A (en) * | 2019-12-30 | 2020-04-17 | 上海集成电路研发中心有限公司 | Method for optimizing metal wire optical proximity correction process window |
CN111199132A (en) * | 2019-12-30 | 2020-05-26 | 上海集成电路研发中心有限公司 | Method for adding metal redundant graph |
Non-Patent Citations (3)
Title |
---|
XU XIAOQING 等: "Redundant Local-Loop Insertion for Unidirectional Routing", 《IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS》, vol. 36, no. 07, 31 July 2017 (2017-07-31) * |
任俊香;: "SoC芯片版图的设计与验证", 《科技与创新》, no. 19, 5 October 2015 (2015-10-05) * |
韩晓霞;韩雁;: "填充辅助多晶硅图形的参数成品率版图优化", 《浙江大学学报(工学版)》, no. 12, 15 December 2015 (2015-12-15) * |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3327394B2 (en) | Optical proximity correction method | |
CN107450266B (en) | Optical proximity effect correction method and system | |
CN109614705B (en) | Method for generating auxiliary pattern of metal layer device | |
CN109407460B (en) | Exposure auxiliary pattern adding method | |
CN109669319B (en) | OPC correction method for improving line end size uniformity of polycrystalline silicon layer | |
CN107908893B (en) | Layout processing method for missing process hot spot on top of metal layer photoresist | |
WO2023284065A1 (en) | Semiconductor integrated circuit design method and apparatus | |
US9530731B2 (en) | Method of optical proximity correction for modifying line patterns and integrated circuits with line patterns modified by the same | |
CN105807555A (en) | Method for improving OPC (optical proximity correction) precision | |
CN112232013A (en) | OPC treatment method for improving coverage rate between metal layer and through hole layer | |
CN101290904A (en) | Method for correcting layout design for correcting metallic coating of contact hole | |
CN111624855B (en) | Pre-processing method before optical proximity correction and optical proximity correction method | |
CN109459910B (en) | Sub-resolution auxiliary graph setting method for metal layer process hot spots | |
JP2014174288A (en) | Integrated circuit device and method of creating mask layout | |
US9047658B2 (en) | Method of optical proximity correction | |
CN116594256A (en) | Optical proximity correction method for improving electroplating hole filling capability | |
CN110716385A (en) | Optical proximity correction method | |
WO2022147997A1 (en) | Method for manufacturing semiconductor mark, and semiconductor mark | |
US7337423B2 (en) | Mask pattern generating method and mask pattern generating apparatus | |
WO2021203550A1 (en) | Optical proximity correction method for curve pattern | |
CN102486606A (en) | Photoetching method | |
US10474026B2 (en) | Method for correcting bevel corners of a layout pattern | |
CN113050365A (en) | Optical proximity correction method and system, mask, equipment and medium | |
US20230010293A1 (en) | Semiconductor integrated circuit design method and apparatus | |
CN111781801B (en) | Dual direct-writing method for mask manufacturing and laser direct-writing photoetching |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |