CN110850372B - Perimeter defending radar signal processor - Google Patents
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- CN110850372B CN110850372B CN201911058847.4A CN201911058847A CN110850372B CN 110850372 B CN110850372 B CN 110850372B CN 201911058847 A CN201911058847 A CN 201911058847A CN 110850372 B CN110850372 B CN 110850372B
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- 238000001514 detection method Methods 0.000 claims abstract description 16
- 230000007123 defense Effects 0.000 claims abstract description 9
- 230000009977 dual effect Effects 0.000 claims abstract description 4
- 238000005070 sampling Methods 0.000 claims description 48
- 230000001360 synchronised effect Effects 0.000 claims description 6
- 238000005259 measurement Methods 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000006870 function Effects 0.000 abstract description 2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
Abstract
The invention discloses a radar signal processor for perimeter defense, which comprises a main processor, an external instruction memory, an external data memory, an operational amplifier and a data transmission chip, wherein the main processor is connected with the external instruction memory; the external instruction memory, the external data memory, the operational amplifier and the data transmission chip are respectively connected with the main processor. The radar signal processor adopts two-dimensional FFT processing, the main processor has dual cores, the operation efficiency is high, the fault detection function for the radio frequency front end is increased, and the clock of the signal processor is provided by the radio frequency front end.
Description
Technical Field
The invention relates to the technical field of radar signal processing, in particular to a radar signal processor for perimeter defense.
Background
Radar signal processing is a core part of a radar system, and its main functions are: providing time sequence for the whole machine, and controlling the front end of the radio frequency to emit the required waveform; and sampling the radar echo signals, and outputting a processing result to the upper computer. In the existing low-cost miniaturized radar signal processor, the following defects mainly exist:
1. radio frequency front end failure is difficult to detect
The existing low-cost miniaturized signal processor transmits an instruction to the radio frequency front end through the SPI interface to control the radio frequency front end to transmit a required high-frequency signal, if the radio frequency front end fails, the signal processor cannot judge, so that the failure of the radio frequency front end cannot be known, a spectrometer is required to be used for testing whether the 24G high-frequency signal is output or not, and the testing process is troublesome.
2. Failure to detect stationary targets
The existing low-cost miniaturized signal processor only has one-dimensional speed resolution, the distance is calculated by means of frequency difference and phase difference of signals with different frequencies, for all stationary targets, the stationary targets are mixed with ground clutter at zero frequency, no proper clutter removal method is available, stationary target information cannot be effectively extracted from the ground clutter, and if the ground clutter is filtered, the stationary targets are filtered, so that the stationary targets are difficult to detect.
3. Noise caused by crystal oscillator chip is large
Because of the synchronization reason of the radar complete machine, the clock of the radio frequency front end is led by the crystal oscillator chip in the signal processor through the internal bus, the synchronization of the whole system can be ensured, but the radio frequency front end is a high-frequency signal, the clock is inevitably interfered by wiring, the radar starting point is interfered, when the signal is transmitted to the signal processor, the noise is increased, and the detection of a target with small intensity or a long-distance weak signal is difficult.
4. Long running time
The existing low-cost miniaturized signal processor has only one core, and the existing TMS320F28377D has two cores, so that the original speed is doubled. The primary frequency of the original signal processor is 150M, the primary frequency of the current signal processor is 200M, and the running speed is 30% slower than the current running speed.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a radar signal processor with perimeter defense, which adopts two-dimensional FFT processing, and has dual cores and high operation efficiency.
In order to achieve the above purpose, the present invention adopts the following technical scheme, including:
a radar signal processor for perimeter defense, comprising: the device comprises a main processor, an external instruction memory, an external data memory, an operational amplifier and a data transmission chip;
the main processor is a dual-core DSP signal processor, and an AD module, namely an analog-to-digital conversion module, is arranged in the dual-core DSP signal processor;
the external instruction memory is a FLASH memory chip for storing radar configuration parameters, and the FLASH memory chip can be powered down to reserve the radar configuration parameters;
the external data memory is an SRAM memory chip and is used for storing echo data;
the operational amplifier is used for amplifying the analog signal;
the data transmission chip is a network chip and is used for transmitting data and receiving an upper computer instruction;
the external instruction memory, the external data memory, the operational amplifier and the data transmission chip are respectively connected with the main processor;
the main processor is provided with two paths of SPI interfaces, and the two paths of SPI interfaces are respectively connected with the waveform generating chip and the high-frequency receiving and transmitting chip of the radio frequency front end to control the radio frequency front end to emit sawtooth wave linear frequency modulation signals;
the radio frequency front end receives a return wave signal, namely an analog IQ signal, the radio frequency front end sends the received analog IQ signal to the operational amplifier, the operational amplifier amplifies zero intermediate frequency signals in the analog IQ signal, the operational amplifier filters high frequency signals in the analog IQ signal, and the operational amplifier sends the processed analog IQ signal to the main processor;
the AD module in the main processor samples the processed analog IQ signal to obtain a sampling result, namely a digital IQ signal, the sampling result is stored in an external data memory, and the main processor also carries out operation processing on the sampling result; the arithmetic processing includes: obtaining distance, speed and intensity information through two-dimensional FFT processing, and obtaining azimuth information through two-channel comparison and phase angle measurement; wherein the first dimension FFT processing is distance dimension processing, and the second dimension FFT processing is speed dimension processing;
and the main processor sends the operation result to an upper computer or other equipment through a data transmission chip.
The main processor is a dual-core DSP signal processor, and the dual cores are core1 and core2 respectively; the external instruction memory comprises n external memory spaces for first dimension FFT processing, namely n one-dimensional external memory spaces, and n external memory spaces for second dimension FFT processing, namely n two-dimensional external memory spaces;
the main processor completes the operation processing of the sampling result through the mutual cooperation of the core1 and the core2, and specifically comprises the following steps:
s1, an AD module in a main processor samples an analog IQ signal under the 1 st period, and core2 stores a sampling result of the 1 st period into a 1 st one-dimensional external memory space of an external data memory;
the AD module in the main processor samples the analog IQ signal under the 2 nd period, and the core2 stores the sampling result of the 2 nd period into the 2 nd one-dimensional external memory space of the external data memory; at the same time, core1 reads the sampling result of the 1 st period from the 1 st one-dimensional memory space, performs a first-dimensional FFT processing on the read sampling result of the 1 st period, and stores the data after the first-dimensional FFT processing into the 1 st two-dimensional memory space;
the AD module in the main processor samples the analog IQ signal of the 3 rd period, and the core2 stores the sampling result of the 3 rd period into the 3 rd one-dimensional external memory space of the external data memory; at the same time, core1 reads the sampling result of the 2 nd period from the 2 nd one-dimensional memory space, performs a first-dimension FFT processing on the read sampling result of the 2 nd period, and stores the data after the first-dimension FFT processing into the 2 nd two-dimensional memory space;
repeating the steps until core1 completes the first dimension FFT processing of the sampling result stored in the nth dimension external memory space, and stores the data after the first dimension FFT processing into the nth dimension external memory space;
s2, the core1 reads data on the same distance library from each two-dimensional memory space to perform second-dimensional FFT processing and target detection, and simultaneously, the core2 reads data on different same distance libraries from each two-dimensional memory space to perform second-dimensional FFT processing and target detection.
In step S2, core1 reads the data in the first half of the distance library to perform the second-dimension FFT processing and target detection, and core2 reads the data in the second half of the distance library to perform the second-dimension FFT processing and target detection.
In step S1, after the core2 puts the sampling result into the external memory space of the external data memory, the core2 will send a stored signal to the core1; after the core1 receives the stored signal, the core1 reads the sampling result from the external memory space of the external data memory to perform first dimension FFT processing, and after the first dimension FFT processing is completed, the core1 sends a processed signal to the core2; after the core2 receives the processed signal, the core2 puts the sampling result into the external memory space of the external data memory, and circulates in this way, so as to achieve synchronous work between the core2 and the core1;
if the core2 and the core1 cannot synchronously work, the main processor automatically restarts, and the main processor also reports faults to the upper computer through the data transmission chip.
After the radio frequency front end transmits a sawtooth wave frequency modulation signal, a high-level pulse is generated, and the radio frequency front end feeds back the high-level pulse to the main processor;
the radar signal processor takes the high-level pulse sent by the radio frequency front end as a reference of the time sequence of the whole machine; if the main processor can not receive the high-level pulse or the number of the received high-level pulse is less than the total number of the emission of the sawtooth wave frequency modulation signals, the main processor is automatically restarted, the radio frequency front end is reconfigured, and the main processor also reports faults to the upper computer through the data transmission chip.
The model of the dual-core DSP signal processor adopted by the main processor is TMS320F28377D, and the manufacturer is Texas Instruments company.
The invention has the advantages that:
(1) The signal processor is used for processing echo signals of sawtooth wave linear frequency modulation signals, the echo signals are two-dimensional matrixes, and have a speed dimension and a distance dimension, and the two-dimensional resolution greatly improves target resolution and target capacity, wherein the first dimension is the distance dimension, after the first dimension is subjected to FFT processing, the amplitude of a main lobe and a side lobe of a zero channel is very high, the amplitude on a distance base behind the side lobe is very low, the second dimension is the speed dimension, after the second dimension is subjected to FFT processing, if no stationary target echo signals exist, the amplitude of the zero channel of the speed dimension is lower, if the stationary target echo signals exist, the amplitude of the zero channel of the speed dimension is higher, and subsequently, whether the stationary target exists can be detected by detecting whether the amplitude is higher.
(2) In the one-dimensional FFT processing process, the dual-core DSP chip achieves synchronous work through interaction signals, and when two cores cannot interact, namely cannot synchronously work, the dual-core DSP chip can report faults to an upper computer, reset and restart the dual-core DSP chip and eliminate the faults. If the fault is repeatedly reported in a short time, the signal processing hardware is indicated to have a problem, and the hardware needs to be maintained.
(3) The main processor of the invention adopts a dual-core DSP chip, and has high running speed. Two cores of the dual-core DSP chip are core1 and core2 respectively, the core2 is sampled and stored in an external memory, the core1 takes a first-dimension FFT from the external memory, and the result is stored in the external memory, and when the core2 finishes sampling, the core1 delays for one period, namely hundreds of microseconds, to finish the first-dimension FFT; core1 and core2 do the second dimension FFT at the same time, finally send out the result through W5300 network interface, the whole process flow is completed in one frame, there is no delay taking frame as unit, send out the processing result in real time.
(4) After the radio frequency front end transmits a sawtooth wave frequency modulation signal, a high level pulse is generated, 128 sawtooth wave frequency modulation signals are completed, 128 high level pulses are generated, the high level pulse sent by each front end can be used as a reference of the time sequence of the whole machine, if the high level pulse is not detected or the number of the high level pulses is less than 128, the signal processor can report the radio frequency front end fault to the upper computer, and the signal processor reconfigures the radio frequency front end by restarting the radar so as to recover normal operation.
(5) The clock of the signal processor is provided by the radio frequency front end, so that the radar system can be ensured to keep synchronous consistency, the noise of the front end is reduced, the IQ signal of the front end is ensured not to submerge weak small signals in the detection range, the small signals have enough signal-to-noise ratio, and convenience is brought to finding and distinguishing targets.
Drawings
Fig. 1 is a schematic diagram of a radar signal processor for perimeter defense according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, a radar signal processor for perimeter defense according to the present invention includes:
the main processor 1 is a DSP signal processor, namely a DSP chip, wherein an AD module is arranged in the DSP signal processor, the model is TMS320F28377D, and the manufacturer is Texas Instruments company.
The external instruction memory 2 is a FLASH memory chip, which is used for storing radar configuration parameters, and can be powered down to reserve the radar configuration parameters, and the model is 39VF800A, and the manufacturer is Silicon Storage Technology company.
And the external data memory 3 IS an SRAM memory chip and IS used for storing radar echo data, the model IS61WV102416BLL and the manufacturer IS Integrated Silicon Solution company.
The operational amplifier 4 is used for amplifying analog signals, and has a model number of MAX4478 and a manufacturer of Maxim Integrated company.
And the data transmission chip 5 is a network chip and is used for transmitting data and receiving an upper computer instruction, the model is W5300, and the manufacturer is WIZnet company.
The external instruction memory 2, the external data memory 3, the operational amplifier 4 and the data transmission chip 5 are respectively connected with the main processor 1.
The main processor 1 is provided with a plurality of SPI, SCI, HPWM, AD and other external interfaces, so that the data transmission between the radar signal processor and the front end and the rear end of the radio frequency is met.
The main processor 1 is provided with two SPI interfaces, the two SPI interfaces are connected with the radio frequency front end, and the two SPI interfaces are respectively connected with the waveform generation chip and the 24G high-frequency receiving and transmitting chip of the radio frequency front end to control the radio frequency front end to emit a sawtooth wave linear frequency modulation signal of a 24G wave band.
After the front end of the radio frequency transmits a sawtooth wave frequency modulation signal, a high-level pulse is generated, and the front end of the radio frequency feeds back the high-level pulse to the main processor 1; the radar signal processor takes the high-level pulse sent by the radio frequency front end as a reference of the time sequence of the whole machine, namely, the radar signal processor takes the high-level pulse as a clock, if the main processor 1 cannot receive the high-level pulse or the number of the received high-level pulses is less than the total number of the emission of the sawtooth wave frequency modulation signals, the main processor 1 automatically restarts to reconfigure the radio frequency front end, the main processor 1 also reports faults to an upper computer through the data transmission chip 5, and the signal processor reconfigures the radio frequency front end in a mode of restarting the radar so as to restore normal work. The clock of the signal processor is provided by the radio frequency front end, so that the radar system can be ensured to keep synchronous consistency, the noise of the front end is reduced, the IQ signal of the front end is ensured not to submerge weak small signals in the detection range, the small signals have enough signal-to-noise ratio, and convenience is brought to finding and distinguishing targets.
The radio frequency front end receives a return wave signal, namely an analog IQ signal, the radio frequency front end returns the received analog IQ signal to the operational amplifier 4, the operational amplifier 4 amplifies zero intermediate frequency signals in the analog IQ signal, the high frequency signals in the analog IQ signal are filtered, interference caused by secondary echo is prevented, and the operational amplifier 4 sends the processed analog IQ signal to the main processor 1.
The AD module in the main processor 1 samples the processed analog IQ signal to obtain a sampling result, namely a digital IQ signal, the sampling result is stored in the external data memory 3, the main processor 1 carries out operation processing on the sampling result, the operation processing is that distance, speed and intensity information is obtained through two-dimensional FFT processing, and azimuth information is obtained through two-channel comparison and phase angle measurement; the first dimension FFT processing is distance dimension processing, and the second dimension FFT processing is speed dimension processing.
The main processor 1 reads data from the external data memory 3 to perform operation processing, wherein the operation processing is that distance, speed and intensity information is obtained through two-dimensional FFT processing, and azimuth information is obtained through two-channel comparison and phase angle measurement; the first dimension FFT processing is distance dimension processing, and the second dimension FFT processing is speed dimension processing.
The main processor 1 sends the operation result to an upper computer or other devices, in this embodiment, cameras, through the data transmission chip 5.
Processor 1 is a dual-core DSP signal processor, with core1 and core2, respectively; the external instruction memory 2 includes 128 memory spaces for the first-dimensional FFT processing, i.e., 128 one-dimensional memory spaces, and 128 memory spaces for the second-dimensional FFT processing, i.e., 128 two-dimensional memory spaces;
the main processor 1 completes the operation processing of the sampling result through the mutual cooperation of the core1 and the core2, and specifically comprises the following steps:
s1, an AD module in a main processor 1 samples an analog IQ signal under the 1 st period, and core2 stores a sampling result of the 1 st period into a 1 st one-dimensional memory space of an external data memory 3;
the AD module in the main processor 1 samples the analog IQ signal under the 2 nd period, and the core2 stores the sampling result of the 2 nd period into the 2 nd one-dimensional external memory space of the external data memory 3; at the same time, core1 reads the sampling result of the 1 st period from the 1 st one-dimensional memory space, performs a first-dimensional FFT processing on the read sampling result of the 1 st period, and stores the data after the first-dimensional FFT processing into the 1 st two-dimensional memory space;
the AD module in the main processor 1 samples the analog IQ signal of the 3 rd period, and the core2 stores the sampling result of the 3 rd period into the 3 rd one-dimensional external memory space of the external data memory 3; at the same time, core1 reads the sampling result of the 2 nd period from the 2 nd one-dimensional memory space, performs a first-dimension FFT processing on the read sampling result of the 2 nd period, and stores the data after the first-dimension FFT processing into the 2 nd two-dimensional memory space;
repeating the steps until core1 completes the first dimension FFT processing of the sampling result stored in the 128 th dimension external memory space, and stores the data after the first dimension FFT processing into the 128 th dimension external memory space;
s2, the core1 respectively reads data on the same distance library from each two-dimensional memory space to perform second-dimensional FFT processing and target detection, and simultaneously, the core2 also respectively reads data on different same distance libraries from each two-dimensional memory space to perform second-dimensional FFT processing and target detection; and core1 reads the data on the first half distance library to perform second-dimension FFT processing and target detection, and core2 reads the data on the second half distance library to perform second-dimension FFT processing and target detection.
In step S1, after the core2 puts the sampling result into the external memory space of the external data memory 3, the core2 will send a stored signal to the core1; after the core1 receives the stored signal, the core1 reads the sampling result from the external memory space of the external data memory 3 to perform a first dimension FFT processing, and after the first dimension FFT processing is completed, the core1 sends a processed signal to the core2; after the core2 receives the processed signal, the core2 puts the sampling result into the external memory space of the external data memory 3 again, and circulates in this way, so as to achieve synchronous work between the core2 and the core1;
if the core2 and the core1 cannot synchronously work, the main processor 1 automatically restarts, and the main processor 1 reports a fault to the upper computer through the data transmission chip 5 and resets and restarts the main processor to eliminate the fault. If the fault is repeatedly reported in a short time, the signal processing hardware is indicated to have a problem, and the hardware needs to be maintained.
The main processor of the invention adopts a dual-core DSP chip, and has high running speed. Two cores of the dual-core DSP chip are core1 and core2 respectively, the core2 is sampled and stored in an external memory, the core1 takes a first-dimension FFT from the external memory, and the result is stored in the external memory, and when the core2 finishes sampling, the core1 delays for one period, namely hundreds of microseconds, to finish the first-dimension FFT; core1 and core2 do the second dimension FFT at the same time, finally send out the result through W5300 network interface, the whole process flow is completed in one frame, there is no delay taking frame as unit, send out the processing result in real time.
The signal processor is used for processing echo signals of sawtooth wave linear frequency modulation signals, the echo signals are two-dimensional matrixes, and have a speed dimension and a distance dimension, and the two-dimensional resolution greatly improves target resolution and target capacity, wherein the first dimension is the distance dimension, after the first dimension is subjected to FFT processing, the amplitude of a main lobe and a side lobe of a zero channel is very high, the amplitude on a distance base behind the side lobe is very low, the second dimension is the speed dimension, after the second dimension is subjected to FFT processing, if no stationary target echo signals exist, the amplitude of the zero channel of the speed dimension is lower, if the stationary target echo signals exist, the amplitude of the zero channel of the speed dimension is higher, and subsequently, whether the stationary target exists can be detected by detecting whether the amplitude is higher.
The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (5)
1. A radar signal processor for perimeter defense, comprising: the device comprises a main processor (1), an external instruction memory (2), an external data memory (3), an operational amplifier (4) and a data transmission chip (5);
the main processor (1) is a dual-core DSP signal processor, and an AD module, namely an analog-to-digital conversion module, is arranged in the dual-core DSP signal processor;
the external instruction memory (2) is a FLASH memory chip which is used for storing radar configuration parameters and can save the radar configuration parameters when power is lost;
the external data memory (3) is an SRAM memory chip and is used for storing echo data;
an operational amplifier (4) for amplifying the analog signal;
the data transmission chip (5) is a network chip and is used for transmitting data and receiving an upper computer instruction;
the external instruction memory (2), the external data memory (3), the operational amplifier (4) and the data transmission chip (5) are respectively connected with the main processor (1);
the main processor (1) is provided with two paths of SPI interfaces, and the two paths of SPI interfaces are respectively connected with a waveform generating chip and a high-frequency receiving and transmitting chip of the radio frequency front end to control the radio frequency front end to emit sawtooth wave linear frequency modulation signals;
the radio frequency front end receives a return wave signal, namely an analog IQ signal, the radio frequency front end sends the received analog IQ signal to the operational amplifier (4), the operational amplifier (4) amplifies zero intermediate frequency signals in the analog IQ signal, high frequency signals in the analog IQ signal are filtered, and the operational amplifier (4) sends the processed analog IQ signal to the main processor (1);
the AD module in the main processor (1) samples the processed analog IQ signal to obtain a sampling result, namely a digital IQ signal, the sampling result is stored in an external data memory (3), and the main processor (1) also carries out operation processing on the sampling result; the arithmetic processing includes: obtaining distance, speed and intensity information through two-dimensional FFT processing, and obtaining azimuth information through two-channel comparison and phase angle measurement; wherein the first dimension FFT processing is distance dimension processing, and the second dimension FFT processing is speed dimension processing;
the main processor (1) sends the operation result to an upper computer or other equipment through the data transmission chip (5);
the main processor (1) is a dual-core DSP signal processor, and the dual cores are core1 and core2 respectively; the external instruction memory (2) comprises n external memory spaces for the first dimension FFT processing, namely n one-dimensional external memory spaces, and n external memory spaces for the second dimension FFT processing, namely n two-dimensional external memory spaces;
the main processor (1) completes the operation processing of the sampling result through the mutual cooperation of the core1 and the core2, and specifically comprises the following steps:
s1, an AD module in a main processor (1) samples an analog IQ signal under a 1 st period, and core2 stores a sampling result of the 1 st period into a 1 st one-dimensional memory space of an external data memory (3);
an AD module in the main processor (1) samples an analog IQ signal under the 2 nd period, and the core2 stores the sampling result of the 2 nd period into a 2 nd one-dimensional external memory space of the external data memory (3); at the same time, core1 reads the sampling result of the 1 st period from the 1 st one-dimensional memory space, performs a first-dimensional FFT processing on the read sampling result of the 1 st period, and stores the data after the first-dimensional FFT processing into the 1 st two-dimensional memory space;
the AD module in the main processor (1) samples the analog IQ signal of the 3 rd period, and the core2 stores the sampling result of the 3 rd period into the 3 rd one-dimensional external memory space of the external data memory (3); at the same time, core1 reads the sampling result of the 2 nd period from the 2 nd one-dimensional memory space, performs a first-dimension FFT processing on the read sampling result of the 2 nd period, and stores the data after the first-dimension FFT processing into the 2 nd two-dimensional memory space;
repeating the steps until core1 completes the first dimension FFT processing of the sampling result stored in the nth dimension external memory space, and stores the data after the first dimension FFT processing into the nth dimension external memory space;
s2, the core1 reads data on the same distance library from each two-dimensional memory space to perform second-dimensional FFT processing and target detection, and simultaneously, the core2 reads data on different same distance libraries from each two-dimensional memory space to perform second-dimensional FFT processing and target detection.
2. A radar signal processor according to claim 1, wherein in step S2, core1 reads data from the first half of the range bin for second-dimensional FFT processing and target detection, and core2 reads data from the second half of the range bin for second-dimensional FFT processing and target detection.
3. A radar signal processor for perimeter defense according to claim 1, wherein in step S1, after the core2 puts the sampling result into the external memory space of the external data memory (3), the core2 sends a stored signal to the core1; after the core1 receives the stored signal, the core1 reads the sampling result from the external memory space of the external data memory (3) to perform first dimension FFT processing, and after the first dimension FFT processing is completed, the core1 sends a processed signal to the core2; after the core2 receives the processed signal, the core2 puts the sampling result into the external memory space of the external data memory (3) again, and circulates in this way, so as to achieve synchronous work between the core2 and the core1;
if the core2 and the core1 cannot work synchronously, the main processor (1) is restarted automatically, and the main processor (1) also reports faults to the upper computer through the data transmission chip (5).
4. A radar signal processor for perimeter defense according to claim 1, wherein the rf front-end generates a high level pulse after transmitting a saw-tooth frequency modulated signal, the rf front-end feeding back the high level pulse to the main processor (1);
the radar signal processor takes the high-level pulse sent by the radio frequency front end as a reference of the time sequence of the whole machine; if the main processor (1) cannot receive the high-level pulse or the number of the received high-level pulse is less than the total number of the transmission of the sawtooth wave frequency modulation signals, the main processor (1) automatically restarts to reconfigure the radio frequency front end, and the main processor (1) also reports faults to an upper computer through the data transmission chip (5).
5. A radar signal processor for perimeter protection according to claim 1, characterized in that the model of the dual-core DSP signal processor used by the main processor (1) is TMS320F28377D, manufacturer Texas Instruments.
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