CN111679278B - W-waveband unmanned aerial vehicle synthetic aperture radar real-time imaging system based on FPGA - Google Patents
W-waveband unmanned aerial vehicle synthetic aperture radar real-time imaging system based on FPGA Download PDFInfo
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Abstract
A W-band unmanned aerial vehicle synthetic aperture radar real-time imaging system based on FPGA comprises a digital intermediate frequency receiver, a secondary power module, an unmanned aerial vehicle, a stable platform, a wireless communication module, an upper computer, a W-band FMCW receiving and transmitting front end, an X-band FMCW frequency synthesizer and an airborne SAR antenna subsystem; the digital intermediate frequency receiver is used for forwarding an operation instruction of the upper computer, receiving a digital intermediate frequency echo signal and carrying out real-time imaging processing; the secondary power supply module is used for supplying power to all modules of the system; the unmanned aerial vehicle is responsible for carrying the whole radar system; the stable platform ensures that the antenna pointing direction is stable and unchanged in the flight process; the wireless communication module is used for communication between the upper computer and the radar system; the X-band FMCW frequency synthesis provides a linear frequency modulation signal; and the W-band FMCW transceiving front end receives a target echo signal, and the target echo signal is provided to an intermediate frequency receiver after down-conversion. The system adopts a novel real-time imaging algorithm, improves the image quality, has flexible algorithm and high operation speed, and can meet the real-time requirement of a radar system.
Description
Technical Field
The invention relates to a W-band unmanned aerial vehicle synthetic aperture radar real-time imaging system based on an FPGA (field programmable gate array), and belongs to the technical field of radars.
Background
The synthetic aperture radar technology has matured over the years. Because of its all-weather, all-time, long-distance characteristics, it has extensive application in the fields of aviation, spaceflight, national defense, etc. The synthetic aperture radar signal processing algorithm is complex and intensive in operation, and a radar signal processing system is required to have strong processing capacity and high-speed data transmission performance. With the development of the SAR system to multi-polarization, high resolution and real-time imaging, the echo data volume received by the radar is larger and larger, the imaging time is shorter and shorter, and the traditional real-time imaging system solution cannot meet the real-time requirement of the radar system.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the defects of the prior art are overcome, and the W-band unmanned aerial vehicle synthetic aperture radar real-time imaging system based on the FPGA is provided.
The technical solution of the invention is as follows:
the utility model provides a real-time imaging system of W wave band unmanned aerial vehicle synthetic aperture radar based on FPGA, includes: digital intermediate frequency receiver, secondary power module, unmanned aerial vehicle, stable platform, wireless communication module, host computer, W wave band FMCW receive and dispatch front end, X wave band FMCW and frequently combine and airborne SAR antenna subsystem, wherein:
an upper computer: sending an operation instruction to the wireless communication module, and receiving a return state of the radar real-time imaging system forwarded by the wireless communication module;
a wireless communication module: the operation instruction from the upper computer is forwarded to the digital intermediate frequency receiver, and the current working state of the radar real-time imaging system is forwarded to the upper computer;
digital intermediate frequency receiver: analyzing an operating instruction of the upper computer to obtain an antenna pointing angle control instruction, a pulse repetition period, an artificial gain control parameter, a read/write instruction and a USB control instruction; sending an antenna pointing angle control instruction to a stable platform, and sending a pulse repetition period and an artificial gain control parameter to an X-band FMCW frequency synthesizer; receiving a digital intermediate frequency echo signal, and performing real-time imaging processing and storage on the digital intermediate frequency echo signal;
a secondary power supply module: receiving power supply of an unmanned aerial vehicle battery, and performing voltage transformation processing on the power supply to supply power to a digital intermediate frequency receiver, a wireless communication module, a W-band FMCW transceiving front end and an X-band FMCW frequency synthesis;
unmanned aerial vehicle: an unmanned aerial vehicle battery carried by the unmanned aerial vehicle is used for supplying power to the secondary power supply module and the stable platform;
stabilizing the platform: the system is hung on an unmanned aerial vehicle, a digital intermediate frequency receiver, a secondary power supply module, a wireless communication module, a W-band FMCW transceiving front end, an X-band FMCW frequency synthesizer and an airborne SAR antenna subsystem are carried on the system, and the antenna pointing direction and the flying direction included angle are controlled to be stable according to an antenna pointing angle control instruction in the working process of a radar real-time imaging system;
x-band FMCW frequency synthesis: setting related parameters according to the pulse repetition period and the artificial gain control parameters, and generating a linear frequency modulation signal after starting;
w-band FMCW transmit-receive front end: the system is responsible for transmitting linear frequency modulation signals generated by the X-waveband FMCW frequency synthesis through an airborne SAR antenna subsystem, receiving target echo signals through the airborne SAR antenna subsystem, and providing the target echo signals to a digital intermediate frequency receiver after down-conversion;
airborne SAR antenna subsystem: the high-power high-directivity pulse beam is used for transmitting a high-power high-directivity pulse beam to a free space and receiving a target echo signal.
The digital intermediate frequency receiver comprises a processing and control unit, a storage unit, a collection unit, a clock unit, an interface unit and a power supply unit;
the processing and control unit: the system is responsible for realizing the time sequence of the system and various control functions and finishing the processing task of the imaging algorithm;
a storage unit: the storage array is composed of a plurality of NandFlash storage particles and provides a storage space for the original collected data and the image data after imaging processing;
a collecting unit: the single-chip ADC comprises two analog input channels for collecting two digital intermediate frequency echo signals and outputting the signals to the processing and control unit;
a clock unit: the synchronous clock signal is responsible for providing synchronous clock signals required by work for the processing and control unit, the storage unit and the acquisition unit;
an interface unit: the system is responsible for communication and control with other external single machines;
a power supply unit: and the power supply of the secondary power supply module is received, and the power supply is processed through voltage stabilization and transformation and then supplied to the processing and control unit, the storage unit, the acquisition unit, the clock unit and the interface unit.
The processing and control unit comprises two FPGAs (field programmable gate arrays) recorded as FPGA1 and FPGA 2;
wherein the FPGA 1: the receiving, the analysis and the forwarding of the operation instruction are realized, and the management of the storage file and the read-write operation of the NandFlash are realized; the system is in charge of receiving sampling data of the single-chip ADC, realizing the configuration and read-write control functions of the single-chip ADC according to the time sequence requirement of the single-chip ADC, framing and storing the sampling data and auxiliary data, and sending the sampling data to the FPGA2 through the GTX high-speed transceiver; the system is responsible for communication processing tasks with other peripheral single machines, and is used for completing remote measurement data, auxiliary data, configuration communication data packaging and unpacking tasks; generating a timing signal of periodic work, coordinating and controlling the working time sequence of other single machines; completing the calculation tasks of the inertial navigation compensation function and other related parameters;
FPGA 2: and carrying out real-time imaging processing on the sampled data, wherein the sampled data is a digital intermediate frequency echo signal.
The FPGA1 comprises an ADC control module, a Nandflash control module, a USB control module, a communication control module and a clock reset module;
an ADC control module: the system is responsible for configuring a single-chip ADC (analog to digital converter), generating a PRF (pulse repetition frequency) pulse signal by monitoring timing according to an input pulse repetition period, receiving sampling data of the single-chip ADC, framing the sampling data of the ADC and inertial navigation data by using the PRF pulse signal, and transmitting the processed sampling data to a Nandflash control module;
the Nandflash control module: completing the read/write operation of the Nandflash memory matrix according to the read/write instruction of the upper computer;
the USB control module: the data read from the Nandflash storage matrix by the Nandflash control module is exported according to the USB control instruction and is forwarded to the upper computer through the wireless communication module;
a communication control module: the digital intermediate frequency receiver is responsible for communication between the digital intermediate frequency receiver and each single machine, is responsible for forwarding an operation instruction of the upper computer to each single machine, returns a remote measurement signal of each single machine to the upper computer and generates a monitoring timing signal according to a sampling clock;
a clock reset module: managing the board card clock reset signal, and synchronously processing the reset signal.
The FPGA2 performs real-time imaging processing on the processed digital intermediate-frequency echo signal, and the steps are as follows:
RVP item correction is carried out on the processed digital intermediate frequency echo signal;
performing inertial navigation compensation on the digital intermediate-frequency echo signal corrected by the RVP term, and eliminating the modulation of the change of the direction of the antenna echo on the amplitude and the phase of the echo;
performing motion error estimation on the digital intermediate frequency echo signal subjected to inertial navigation compensation to obtain an estimated phase error, fitting the estimated phase error along the distance direction to obtain azimuth data, and then performing azimuth fitting on the azimuth data to obtain sub-aperture data;
when the sub-aperture data are accumulated to two full aperture lengths, motion error compensation is carried out on the data, and imaging is realized through azimuth matching filtering.
The FPGA2 carries out motion error estimation on the digital intermediate frequency echo signal subjected to inertial navigation compensation, and the steps of obtaining the estimated phase error are as follows:
1) sequencing all distance units of an image data sequence of the digital intermediate frequency echo signals subjected to inertial navigation compensation from large to small according to intensity, and selecting the first 6 distance units after sequencing;
2) performing Fourier transform on the selected data sequence of each distance unit to obtain a complex image of the azimuth dimension of each distance unit, and selecting 1 strong feature display point from the complex image;
3) setting the window width of the window function as eighty azimuth resolution units;
4) intercepting a section of complex image for each strong special display point image by using a window function;
5) and circularly shifting the image segments intercepted by the window functions, and shifting the peak value of the strong feature point to the center of the image.
6) Each section of complex image sequence is subjected to inverse Fourier transform to obtain respective data sequence and relevant vector sequence;
7) adding the related vector sequences of 6 strong feature points of 6 distance units to obtain a synthesized vector sequence, wherein the phase of the synthesized vector sequence is an estimated phase error, and performing phase correction on each data sequence which is not windowed by using the estimated phase error;
8) judging whether the current window width is 3-5 azimuth resolution units, if so, finishing motion error estimation, and ending; otherwise, narrowing the window width to 20% -50% of the original window width, and entering step 9);
9) repeating the steps 4) -8).
In the step 2), the amplitudes of two hundred resolution units around the selected highlight point are all less than 5% of the amplitude of the selected highlight point.
The clock unit comprises two paths of local working clocks, an external input system clock and a sampling clock so as to meet different requirements of different units on the clocks.
(1) Two-way local work clock
The two local working clocks are respectively 100Mhz and 125Mhz, the 100Mhz clock is divided into a plurality of paths of homologous clocks through a Buffer chip, and the plurality of paths of working clocks required by the working of the internal logic circuit are respectively provided for the FPGA1 and the FPGA 2; the 125Mhz clock provides a reference working clock for high-speed communication between the FPGA1 and the FPGA2, and the reference working clock respectively enters the FPGA1 and the FPGA2 after passing through a clock Buffer;
(2) external input system clock
The external input system clock is used for generating a reference timing signal and other control signals, and is a unified reference signal for coordinating other external single machines; the FPGA1 and the FPGA2 use the internal related logic processing circuits as reference clock sources for generating timing frequency sweep pulses and working timing signals; in the design, a single-end-to-differential circuit is adopted to input a reference clock generated by an X-band FMCW frequency synthesis into the FPGA1, so that the signal source quality is improved;
(3) sampling clock
The sampling clock is a reference clock for the working of the sampling circuit of the single-chip ADC converter, and the sampling circuit finishes the output of the AD sampling data according to the sampling configuration requirement.
Compared with the prior art, the invention has the following technical effects:
(1) the invention designs a W-band unmanned aerial vehicle synthetic aperture radar real-time imaging system based on FPGA, the system realizes the acquisition of radar echo signals, simultaneously designs the specific form of a digital intermediate frequency receiver, particularly designs a new algorithm to carry out real-time imaging processing on the digital intermediate frequency echo signals, and simultaneously carries out inertial navigation compensation and migration correction in the processing process, thereby improving the image quality, having flexible algorithm and high operation speed, and being capable of meeting the real-time requirement of a radar system.
(2) The clock unit comprises two paths of local working clocks, an external input system clock and a sampling clock, and different requirements of different units on the clocks can be met.
Drawings
FIG. 1 is a schematic diagram of the composition of a real-time imaging system of the present invention;
fig. 2 is a schematic diagram of the digital if receiver architecture of the present invention;
FIG. 3 is a block diagram of the hardware components of the digital receiver of the present invention;
FIG. 4 is a schematic diagram of the FPGA1 of the present invention;
FIG. 5 is a schematic flow chart of the real-time imaging algorithm of the present invention
Detailed Description
The invention is described in further detail below with reference to the following figures and specific examples:
fig. 1 is a schematic diagram of the real-time imaging system of the invention, fig. 2 is a schematic diagram of the digital intermediate frequency receiver of the invention, and the real-time imaging system shown in fig. 1 is composed of a digital intermediate frequency receiver, a secondary power module, an unmanned aerial vehicle, a stable platform, a wireless communication module, an upper computer, a W-band FMCW transceiving front end, an X-band FMCW frequency synthesizer and an airborne SAR antenna subsystem.
In the working process, firstly, the system is installed in place schematically according to the figure 1, after a flight route of the unmanned aerial vehicle is set, a radar pointing angle is set through an upper computer before the unmanned aerial vehicle enters the set route, an X-waveband FMCW frequency synthesis and a digital intermediate frequency receiver working mode are configured, after the flight speed of the unmanned aerial vehicle tends to be uniform, a frequency sweeping starting command is issued through the upper computer, after the digital intermediate frequency receiver receives the frequency sweeping starting command from the upper computer, a periodic pulse signal is generated according to a preset frequency sweeping period and serves as a frequency sweeping start of the X-waveband FMCW frequency synthesis, the X-waveband FMCW frequency synthesis starts to produce an X-waveband broadband frequency sweeping signal after receiving the frequency sweeping start, the X-waveband broadband frequency sweeping signal is transmitted out through a transmitting antenna after octave frequency of a W-waveband FMCW transceiving front end to a W waveband, a reflected echo signal is received by a receiving antenna, the echo signal is input to the digital intermediate frequency receiver after down-conversion, meanwhile, the unmanned aerial vehicle transmits auxiliary data such as inertial navigation and the like in the flight process to the digital intermediate frequency receiver, the digital intermediate frequency receiver packs and stores echo data and inertial navigation data to the storage unit, imaging processing is carried out on real-time data, and the processed data are also stored to the storage unit.
Specifically, the modules in fig. 1 are described as follows:
an upper computer: sending an operation instruction to the wireless communication module, and receiving a radar real-time imaging system return state forwarded by the wireless communication module;
a wireless communication module: the operation instruction from the upper computer is forwarded to the digital intermediate frequency receiver, and the current working state of the radar real-time imaging system is forwarded to the upper computer;
digital intermediate frequency receiver: analyzing an operating instruction of the upper computer to obtain an antenna pointing angle control instruction, a pulse repetition period, an artificial gain control parameter, a read/write instruction and a USB control instruction; sending an antenna pointing angle control instruction to a stable platform, and sending a pulse repetition period and an artificial gain control parameter to an X-band FMCW frequency synthesizer; receiving a digital intermediate frequency echo signal, and performing real-time imaging processing and storage on the digital intermediate frequency echo signal;
a secondary power supply module: receiving power supply of an unmanned aerial vehicle battery, and performing voltage transformation processing on the power supply to supply power to a digital intermediate frequency receiver, a wireless communication module, a W-band FMCW transceiving front end and an X-band FMCW frequency synthesis;
unmanned aerial vehicle: an unmanned aerial vehicle battery carried by the unmanned aerial vehicle is used for supplying power to the secondary power supply module and the stable platform;
stabilizing the platform: the system is hung on an unmanned aerial vehicle, a digital intermediate frequency receiver, a secondary power supply module, a wireless communication module, a W-band FMCW transceiving front end, an X-band FMCW frequency synthesizer and an airborne SAR antenna subsystem are carried on the system, and the antenna pointing direction and the flying direction included angle are controlled to be stable according to an antenna pointing angle control instruction in the working process of a radar real-time imaging system;
x-band FMCW frequency synthesis: setting related parameters according to the pulse repetition period and the artificial gain control parameters, and generating a linear frequency modulation signal after starting;
w-band FMCW transmit-receive front end: and the system is responsible for transmitting out a linear frequency modulation signal generated by the X-waveband FMCW frequency synthesis through the airborne SAR antenna subsystem, receiving a target echo signal through the airborne SAR antenna subsystem, and providing the target echo signal to the digital intermediate frequency receiver after down-conversion.
And the airborne SAR antenna subsystem is used for transmitting a high-power high-directivity pulse beam to a free space and receiving a target echo signal.
As shown in fig. 2, the digital intermediate frequency receiver includes a processing and control unit, a storage unit, an acquisition unit, a clock unit, an interface unit, and a power supply unit;
the processing and control unit: the system is responsible for realizing system time sequence and various control functions and completing the processing task of the imaging algorithm;
a storage unit: the storage array composed of a plurality of NandFlash storage particles provides a storage space for the original acquired data and the image data after imaging processing;
a collecting unit: the single-chip ADC comprises two analog input channels for collecting two digital intermediate frequency echo signals and outputting the signals to the processing and control unit;
a clock unit: the synchronous clock signal is responsible for providing synchronous clock signals required by work for the processing and control unit, the storage unit and the acquisition unit;
an interface unit: the system is responsible for communication and control with other external single machines;
a power supply unit: and the power supply of the secondary power supply module is received, and the power supply is processed through voltage stabilization and transformation and then supplied to the processing and control unit, the storage unit, the acquisition unit, the clock unit and the interface unit.
Fig. 3 is a schematic diagram of the hardware connection of the digital if receiver according to the present invention.
The processing and control unit comprises two V7 FPGAs which are marked as FPGA1 and FPGA 2;
wherein the FPGA 1: the receiving, the analysis and the forwarding of the operation instruction are realized, and the management of the storage file and the read-write operation of the NandFlash are realized; the system is in charge of receiving sampling data of the single-chip ADC, realizing the configuration and read-write control functions of the single-chip ADC according to the time sequence requirement of the single-chip ADC, framing and storing the sampling data and auxiliary data, and sending the sampling data to the FPGA2 through the GTX high-speed transceiver; the system is responsible for communication processing tasks with other peripheral single machines, and is used for completing remote measurement data, auxiliary data, configuration communication data packaging and unpacking tasks; generating a timing signal of periodic work, coordinating and controlling the working time sequence of other single machines; completing the calculation tasks of the inertial navigation compensation function and other related parameters;
FPGA 2: carrying out real-time imaging processing on the sampling data; wherein the sampling data is a digital intermediate frequency echo signal.
As shown in fig. 4, the FPGA1 includes an ADC control module, a Nandflash control module, a USB control module, a communication control module, and a clock reset module;
an ADC control module: the system is responsible for configuring a single-chip ADC (analog to digital converter), generating a PRF (pulse repetition frequency) pulse signal by monitoring timing according to an input pulse repetition period, receiving sampling data of the single-chip ADC, framing the sampling data of the ADC and inertial navigation data by using the PRF pulse signal, and transmitting the processed sampling data to a Nandflash control module;
the Nandflash control module: completing the read/write operation of the Nandflash memory matrix according to the read/write instruction of the upper computer;
the USB control module: the data read from the Nandflash storage matrix by the Nandflash control module is exported according to the USB control instruction and is forwarded to the upper computer through the wireless communication module;
a communication control module: the digital intermediate frequency receiver is responsible for communication between the digital intermediate frequency receiver and each single machine, is responsible for forwarding an operation instruction of the upper computer to each single machine, returns a remote measurement signal of each single machine to the upper computer and generates a monitoring timing signal according to a sampling clock;
a clock reset module: managing the board card clock reset signal, and synchronously processing the reset signal.
In a storage unit of the digital intermediate frequency receiver, a NandFlash storage chip adopts a high-speed Flash chip MT29F256G08AUCAB of Micron company, the storage capacity of a single Flash is 256Gbits, the data width is 8bits, a DDR interface is supported, and the IO data throughput can reach 200 MT/s. The single chip has 8 LUNs inside, and the capacity of each LUN is 32 Gbit.
For 20 NandFlash chips of the storage sub-module, two NandFlash chips are combined into one group, and 10 groups are provided, and except CE and RB pins, IO pins of each group of two NandFlash chips are connected in parallel to be connected to the FPGA 1. The NandFlash stored in the image is controlled by the FPGA1, and the chip works in an asynchronous interface mode, wherein each IO rate is 50 MT/s.
The interface unit includes:
(1) RS422 interface of asynchronous communication, RS422 according to EIA-RS-422 standard.
(2) USB protocol interface realizing circuit
The interface unit is used for realizing the export function of the stored data, the circuit of the part is realized by preselecting an application specific integrated circuit CY7C68013 of Cypress company, the chip supports USB2.0, supports 8bit or 16bit external data bus, is internally integrated with an enhanced 8051 core and supports clocks of 48MHz, 24MHz or 12 MHz.
The power supply required by the digital intermediate frequency receiver mainly comprises +3.3V, +1.8V, +1.35V, +1.2V, +1.0V and + 0.625V. The power supply unit is realized by PTH08T210W, PTH08T240W, TPS54620 and TPS51200 of TI company.
TABLE 1 digital IF receiver power distribution table
Real-time imaging is limited by resources such as time and memory, and the computational complexity is required to be reduced as much as possible while the imaging accuracy is satisfied, so that unnecessary computation steps should be eliminated as much as possible when real-time imaging is realized. Meanwhile, the real-time imaging needs to adopt a flow design, namely, part of data is processed firstly, and the azimuth pulse pressure mapping is carried out until the data volume reaches the full aperture. For a longer imaging process, images are respectively generated according to imaging processing of every two full-aperture data, in order to ensure that all points are fully resolved, the size of one full-aperture image in each image is only reserved, and two adjacent images are spliced by overlapping one half. At this time, the data processing of the overlapped portion can be retained in the imaging process of the next image. The method of sub-aperture error phase extraction and full-aperture phase splicing is adopted, the two-dimensional space-variant error estimation and compensation are combined to realize the SAR imaging with ultrahigh resolution, the error estimation and the two-dimensional accurate compensation are carried out based on the echo data, and the adaptability of the processing algorithm to different environmental conditions and application scenes can be improved.
Due to the limitation of the beam width, the W-UAV-SAR system can meet the imaging width requirement only by 4096 points at most in the distance direction, and can meet the requirement of azimuth full-resolution imaging by 2048 points in the azimuth direction. And the range migration amount is smaller than one range cell, so that the influence of the range migration can be ignored, and the step of range migration correction is cancelled. The real-time imaging algorithm flow chart is designed as shown in fig. 5.
The procedure of processing every 256 recorded echoes, firstly correcting by RVP term to remove the azimuth phase modulation caused by Dechirp reception, can process every recorded echo, and does not need to accumulate 256 echo data. And then, the motion error is estimated by partitioning the distance direction, because the distance space variation of the motion error is not negligible due to the closer observation distance, and the distance space variation estimation of the motion error needs to be realized through the fitting of multiple distance blocks. When the data amount is accumulated to 2048 points, the azimuth data reaches two full aperture lengths, a full-resolution image with the full aperture size can be obtained through matched filtering, motion error compensation is carried out on the data, and imaging is achieved through the azimuth matched filtering.
Specifically, the steps of the FPGA2 performing real-time imaging processing on the processed digital intermediate-frequency echo signal are as follows:
RVP term correction is carried out on the processed digital intermediate frequency echo signal, and phase modulation caused by Dechirp receiving is removed;
performing inertial navigation compensation on the digital intermediate-frequency echo signal corrected by the RVP term, and eliminating the modulation of the change of the direction of the antenna echo on the amplitude and the phase of the echo;
performing motion error estimation on the digital intermediate frequency echo signal subjected to inertial navigation compensation to obtain an estimated phase error, fitting the estimated phase error along the distance direction to obtain azimuth data, and then performing azimuth fitting on the azimuth data to obtain sub-aperture data;
when the sub-aperture data are accumulated to two full aperture lengths, motion error compensation is carried out on the data, and imaging is realized through azimuth matching filtering.
The FPGA2 carries out motion error estimation on the digital intermediate frequency echo signal subjected to inertial navigation compensation, and the steps of obtaining the estimated phase error are as follows:
1) sequencing all distance units of an image data sequence of the digital intermediate frequency echo signals subjected to inertial navigation compensation from large to small according to intensity, and selecting the first 6 distance units after sequencing;
2) performing Fourier transform on the data sequence of each selected distance unit to obtain a complex image of the azimuth dimension of each distance unit, and selecting 1 strong special display point from the complex image, wherein two hundred resolution units around the strong special display point are very weak (the amplitudes of the two hundred resolution units around the selected strong special display point are less than 5% of the amplitude of the selected strong special display point); 6 strong feature display points can be selected by 6 distance units;
3) setting the window width of the window function as eighty azimuth resolution units;
4) intercepting a section of complex image for each strong special display point image by using a window function;
5) and circularly shifting the image segments intercepted by each window function, and shifting the peak value of the strong feature point to the center of the image (namely, the position of zero Doppler).
6) Each section of complex image sequence is subjected to inverse Fourier transform to obtain respective data sequence and relevant vector sequence;
7) adding the correlation vector sequences of 6 strong feature points of 6 distance units to obtain a synthetic vector sequence, wherein the phase of the synthetic vector sequence is an estimated phase error, and performing phase correction on each data sequence which is not windowed by using the estimated phase error;
8) judging whether the current window width is 3-5 azimuth distinguishing units, if so, finishing motion error estimation, otherwise, narrowing the window width to 20% -50% of the original window width, and entering step 9);
9) performing steps 4) -8).
In the above step, after the window function is applied for the first time, the situation of each orientation dimensional image obtained by the compensated data sequence through fourier transform is certainly improved obviously, and mainly the point spread function of strong feature points is sharpened. On the basis of the window width, the window width is continuously narrowed, so that the signal-to-noise (noise) ratio is continuously improved. Since the point spread function is sharp, the peak position is continuously adjusted to be more aligned with zero doppler when performing the phase error estimation. Then the data sequence is continuously corrected with the new phase error estimate values, via steps 6) and 7).
In the invention, the clock unit comprises two paths of local working clocks, an external input system clock and a sampling clock so as to meet different requirements of different units on the clock.
(1) Two-way local work clock
The two local working clocks are respectively 100Mhz and 125Mhz, the 100Mhz clock is divided into multiple paths of homologous clocks by a Buffer chip, and the multiple paths of working clocks required by the working of the internal logic circuit are respectively provided for the FPGA1 and the FPGA 2; the 125Mhz clock provides a reference working clock for high-speed communication between the FPGA1 and the FPGA2, and the reference working clock respectively enters the FPGA1 and the FPGA2 after passing through a clock Buffer;
(2) external input system clock
The external input system clock is used for generating a reference timing signal and other control signals, and is a unified reference signal for coordinating other external single machines; the FPGA1 and the FPGA2 use the internal related logic processing circuits as reference clock sources for generating timing frequency sweep pulses and working timing signals; in the design, a single-end-to-differential circuit is adopted to input a reference clock generated by an X-band FMCW frequency synthesis into the FPGA1, so that the signal source quality is improved;
(3) sampling clock
The sampling clock is a reference clock for the working of the sampling circuit of the single-chip ADC converter, and the sampling circuit finishes the output of the AD sampling data according to the sampling configuration requirement.
The invention designs a new algorithm to carry out real-time imaging processing on the digital intermediate-frequency echo signal, and inertial navigation compensation and migration correction are carried out in the processing process, thereby improving the image quality, having flexible algorithm and high operation speed, and being capable of meeting the real-time requirement of a radar system.
Those skilled in the art will appreciate that the invention is not described in detail in this specification.
Claims (6)
1. The utility model provides a real-time imaging system of W wave band unmanned aerial vehicle synthetic aperture radar based on FPGA which characterized in that includes: digital intermediate frequency receiver, secondary power module, unmanned aerial vehicle, stable platform, wireless communication module, host computer, W wave band FMCW receive and dispatch front end, X wave band FMCW are frequently combined and are carried SAR antenna subsystem on the machine, wherein:
an upper computer: sending an operation instruction to the wireless communication module, and receiving a radar real-time imaging system return state forwarded by the wireless communication module;
a wireless communication module: the operation instruction from the upper computer is forwarded to the digital intermediate frequency receiver, and the current working state of the radar real-time imaging system is forwarded to the upper computer;
digital intermediate frequency receiver: analyzing an operating instruction of the upper computer to obtain an antenna pointing angle control instruction, a pulse repetition period, an artificial gain control parameter, a read/write instruction and a USB control instruction; sending an antenna pointing angle control instruction to a stable platform, and sending a pulse repetition period and an artificial gain control parameter to an X-band FMCW frequency synthesizer; receiving a digital intermediate frequency echo signal, and performing real-time imaging processing and storage on the digital intermediate frequency echo signal;
a secondary power supply module: receiving power supply of an unmanned aerial vehicle battery, and performing voltage transformation processing on the power supply to supply power to a digital intermediate frequency receiver, a wireless communication module, a W-band FMCW transceiving front end and an X-band FMCW frequency synthesis;
unmanned aerial vehicle: an unmanned aerial vehicle battery carried by the unmanned aerial vehicle is used for supplying power to the secondary power supply module and the stable platform;
stabilizing the platform: the system is hung on an unmanned aerial vehicle, a digital intermediate frequency receiver, a secondary power supply module, a wireless communication module, a W-band FMCW transceiving front end, an X-band FMCW frequency synthesizer and an airborne SAR antenna subsystem are carried on the system, and the antenna pointing direction and the flying direction included angle are controlled to be stable according to an antenna pointing angle control instruction in the working process of a radar real-time imaging system;
x-band FMCW frequency synthesis: setting related parameters according to the pulse repetition period and the artificial gain control parameters, and generating a linear frequency modulation signal after starting;
w-band FMCW transmit-receive front end: the system is responsible for transmitting linear frequency modulation signals generated by the X-waveband FMCW frequency synthesis through an airborne SAR antenna subsystem, receiving target echo signals through the airborne SAR antenna subsystem, and providing the target echo signals to a digital intermediate frequency receiver after down-conversion;
airborne SAR antenna subsystem: the device is used for transmitting a high-power high-directivity pulse beam to a free space and receiving a target echo signal;
the digital intermediate frequency receiver comprises a processing and control unit, a storage unit, a collection unit, a clock unit, an interface unit and a power supply unit;
the processing and control unit: the system is responsible for realizing the time sequence of the system and various control functions and finishing the processing task of the imaging algorithm;
a storage unit: the storage array is composed of a plurality of NandFlash storage particles and provides a storage space for the original collected data and the image data after imaging processing;
a collecting unit: the single-chip ADC comprises two analog input channels for collecting two digital intermediate frequency echo signals and outputting the signals to the processing and control unit;
a clock unit: the synchronous clock signal is responsible for providing synchronous clock signals required by work for the processing and control unit, the storage unit and the acquisition unit;
an interface unit: the system is responsible for communication and control with other external single machines;
a power supply unit: the power supply of the secondary power supply module is received, and the power supply is processed through voltage stabilization and transformation and then supplied to the processing and control unit, the storage unit, the acquisition unit, the clock unit and the interface unit;
the processing and control unit comprises two FPGAs (field programmable gate arrays) recorded as FPGA1 and FPGA 2;
wherein the FPGA 1: the receiving, the analysis and the forwarding of the operation instruction are realized, and the management of the storage file and the read-write operation of the NandFlash are realized; the system is in charge of receiving sampling data of the single-chip ADC, realizing the configuration and read-write control functions of the single-chip ADC according to the time sequence requirement of the single-chip ADC, framing and storing the sampling data and auxiliary data, and sending the sampling data to the FPGA2 through the GTX high-speed transceiver; the remote data processing system is responsible for communication processing tasks with other peripheral single machines, and completes remote measurement data, auxiliary data and configuration communication data packaging and unpacking tasks; generating a timing signal of periodic work, coordinating and controlling the working time sequence of other single machines; completing calculation tasks of an inertial navigation compensation function and other related parameters;
FPGA 2: carrying out real-time imaging processing on sampling data, wherein the sampling data are digital intermediate frequency echo signals;
the FPGA1 comprises an ADC control module, a Nandflash control module, a USB control module, a communication control module and a clock reset module;
an ADC control module: the system is responsible for configuring a single-chip ADC (analog to digital converter), generating a PRF (pulse repetition frequency) pulse signal by monitoring timing according to an input pulse repetition period, receiving sampling data of the single-chip ADC, framing the sampling data of the ADC and inertial navigation data by using the PRF pulse signal, and transmitting the processed sampling data to a Nandflash control module;
the Nandflash control module: completing the read/write operation of the Nandflash memory matrix according to the read/write instruction of the upper computer;
the USB control module: the data read from the Nandflash storage matrix by the Nandflash control module is exported according to the USB control instruction and is forwarded to the upper computer through the wireless communication module;
a communication control module: the digital intermediate frequency receiver is responsible for communication between the digital intermediate frequency receiver and each single machine, forwarding an operation instruction of the upper computer to each single machine, returning a telemetering signal of each single machine to the upper computer and generating a monitoring timing signal according to a sampling clock;
a clock reset module: managing the board card clock reset signal, and synchronously processing the reset signal.
2. The FPGA-based real-time imaging system for the synthetic aperture radar of the W-band unmanned aerial vehicle of claim 1, wherein: the steps of the FPGA2 for real-time imaging processing of the processed digital intermediate frequency echo signal are as follows:
RVP item correction is carried out on the processed digital intermediate frequency echo signals;
performing inertial navigation compensation on the digital intermediate-frequency echo signal corrected by the RVP term, and eliminating the modulation of the change of the direction of the antenna echo on the amplitude and the phase of the echo;
performing motion error estimation on the digital intermediate frequency echo signal subjected to inertial navigation compensation to obtain an estimated phase error, fitting the estimated phase error along the distance direction to obtain azimuth data, and then performing azimuth fitting on the azimuth data to obtain sub-aperture data;
when the sub-aperture data are accumulated to two full aperture lengths, motion error compensation is carried out on the data, and imaging is achieved through azimuth matching filtering.
3. The FPGA-based real-time imaging system for the synthetic aperture radar of the W-band unmanned aerial vehicle of claim 2, wherein: the FPGA2 carries out motion error estimation on the digital intermediate frequency echo signal subjected to inertial navigation compensation, and the steps of obtaining the estimated phase error are as follows:
1) sequencing all distance units of an image data sequence of the digital intermediate frequency echo signals subjected to inertial navigation compensation from large to small according to intensity, and selecting the first 6 distance units after sequencing;
2) performing Fourier transform on the selected data sequence of each distance unit to obtain a complex image of the azimuth dimension of each distance unit, and selecting 1 strong feature display point from the complex image;
3) setting the window width of the window function as eighty azimuth resolution units;
4) intercepting a section of complex image for each strong special display point image by using a window function;
5) performing circular displacement on the image segments intercepted by each window function, and moving the peak value of the strong feature display point to the center of the image;
6) each section of complex image sequence is subjected to inverse Fourier transform to obtain respective data sequence and relevant vector sequence;
7) adding the correlation vector sequences of 6 strong feature points of 6 distance units to obtain a synthetic vector sequence, wherein the phase of the synthetic vector sequence is an estimated phase error, and performing phase correction on each data sequence which is not windowed by using the estimated phase error;
8) judging whether the current window width is 3-5 azimuth resolution units, if so, finishing motion error estimation, and ending; otherwise, narrowing the window width to 20% -50% of the original window width, and entering step 9);
9) repeating the steps 4) -8).
4. The FPGA-based real-time imaging system for the synthetic aperture radar of the W-band unmanned aerial vehicle of claim 3, wherein: in the step 2), the amplitudes of two hundred resolution units around the selected highlight point are all less than 5% of the amplitude of the selected highlight point.
5. The FPGA-based real-time imaging system for the synthetic aperture radar of the W-band unmanned aerial vehicle of claim 1, wherein: the clock unit comprises two local working clocks, an external input system clock and a sampling clock so as to meet different requirements of different units on the clock.
6. The FPGA-based real-time imaging system for the synthetic aperture radar of the W-band unmanned aerial vehicle of claim 5, wherein:
(1) two-way local work clock
The two local working clocks are respectively 100Mhz and 125Mhz, the 100Mhz clock is divided into a plurality of paths of homologous clocks through a Buffer chip, and the plurality of paths of working clocks required by the working of the internal logic circuit are respectively provided for the FPGA1 and the FPGA 2; the 125Mhz clock provides a reference working clock for high-speed communication between the FPGA1 and the FPGA2, and the reference working clock respectively enters the FPGA1 and the FPGA2 after passing through a clock Buffer;
(2) external input system clock
The external input system clock is used for generating a reference timing signal and other control signals, and is a unified reference signal for coordinating other external single machines; the FPGA1 and the FPGA2 use the internal related logic processing circuits as reference clock sources for generating timing frequency sweep pulses and working timing signals; in the design, a single-end-to-differential circuit is adopted to input a reference clock generated by an X-band FMCW frequency synthesis into the FPGA1, so that the signal source quality is improved;
(3) sampling clock
The sampling clock is a reference clock for the working of the sampling circuit of the single-chip ADC converter, and the sampling circuit finishes the output of AD sampling data according to the sampling configuration requirement.
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