CN110850372A - Radar signal processor for perimeter defense - Google Patents
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- CN110850372A CN110850372A CN201911058847.4A CN201911058847A CN110850372A CN 110850372 A CN110850372 A CN 110850372A CN 201911058847 A CN201911058847 A CN 201911058847A CN 110850372 A CN110850372 A CN 110850372A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
Abstract
The invention discloses a radar signal processor for perimeter defense, which comprises a main processor, an external instruction memory, an external data memory, an operational amplifier and a data transmission chip, wherein the main processor is connected with the external instruction memory; the external instruction memory, the external data memory, the operational amplifier and the data transmission chip are respectively connected with the main processor. The radar signal processor adopts two-dimensional FFT processing, the main processor has double cores and high operation efficiency, the fault detection function of the radio frequency front end is added, and the clock of the signal processor is provided by the radio frequency front end.
Description
Technical Field
The invention relates to the technical field of radar signal processing, in particular to a radar signal processor for perimeter defense.
Background
The radar signal processing is the core part of the radar system, and the main functions of the radar system are as follows: providing a time sequence for the whole machine and controlling the waveform required by the transmission of the radio frequency front end; and sampling the radar echo signals, and outputting a processing result to an upper computer. The existing low-cost miniaturized radar signal processor mainly has the following defects:
1. radio frequency front end failure is difficult to detect
The existing low-cost miniaturized signal processor transmits an instruction to the radio frequency front end through the SPI interface, controls the radio frequency front end to transmit a required high-frequency signal, and if the radio frequency front end fails to work, the signal processor can not judge, so that the fault of the radio frequency front end can not be known, and a frequency spectrograph is required to be used for testing whether the radio frequency front end has 24G high-frequency signal output, so that the testing process is relatively troublesome.
2. Failure to detect stationary targets
The existing low-cost miniaturized signal processor only has one-dimensional speed resolution, the distance is calculated by depending on the frequency difference and the phase difference of signals with different frequencies, all static targets are mixed with ground clutter at zero frequency, a proper clutter removing method is not available, static target information cannot be effectively extracted from the ground clutter, and the static targets can be filtered if the ground clutter is filtered, so that the static targets are difficult to detect.
3. The noise caused by the crystal oscillator chip is large
Because the synchronous reason of radar complete machine, the clock of radio frequency front end is introduced through the internal bus by the crystal oscillator chip among the signal processor, can guarantee entire system's synchronization, but the radio frequency front end all is high frequency signal, and the clock comes through the wiring and has inevitable the interference, and the radar starting point receives the interference, and when the signal passed to signal processor, noise can grow, all is difficult to detect to the target or the long-distance weak signal that intensity is little.
4. Long running time
The existing low-cost miniaturized signal processor only has one core, and the existing TMS320F28377D has two cores, so that the original speed is doubled. The original main frequency of the signal processor is 150M, the current main frequency of the signal processor is 200M, and the running speed is 30% slower than the current main frequency.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a radar signal processor with perimeter defense, which adopts two-dimensional FFT processing, and a main processor has double cores and high operation efficiency.
In order to achieve the purpose, the invention adopts the following technical scheme that:
a perimeter defence radar signal processor comprising: the device comprises a main processor, an external instruction memory, an external data memory, an operational amplifier and a data transmission chip;
the main processor is a dual-core DSP signal processor, and an AD module, namely an analog-to-digital conversion module, is arranged in the dual-core DSP signal processor;
the external instruction memory is a FLASH memory chip used for storing the radar configuration parameters, and the FLASH memory chip can be powered down to reserve the radar configuration parameters;
the external data memory is an SRAM memory chip and is used for storing echo data;
the operational amplifier is used for amplifying the analog signal;
the data transmission chip is a network chip and is used for transmitting data and receiving instructions of an upper computer;
the external instruction memory, the external data memory, the operational amplifier and the data transmission chip are respectively connected with the main processor;
the main processor is provided with two SPI interfaces which are respectively connected with a waveform generating chip and a high-frequency transceiving chip at the radio frequency front end to control the radio frequency front end to transmit sawtooth wave linear frequency modulation signals;
the radio frequency front end is connected with a received back wave signal, namely an analog IQ signal, the radio frequency front end sends the received analog IQ signal to an operational amplifier, the operational amplifier amplifies a zero intermediate frequency signal in the analog IQ signal and filters a high frequency signal in the analog IQ signal, and the operational amplifier sends the processed analog IQ signal to a main processor;
an AD module in the main processor samples the processed analog IQ signal to obtain a sampling result, namely a digital IQ signal, the sampling result is stored in an external data memory, and the main processor also performs operation processing on the sampling result; the arithmetic processing includes: obtaining distance, speed and intensity information through two-dimensional FFT processing, and obtaining azimuth information through a two-channel phase comparison angle measurement; the first dimension FFT processing is distance dimension processing, and the second dimension FFT processing is speed dimension processing;
and the main processor sends the operation result to an upper computer or other equipment through a data transmission chip.
The main processor is a dual-core DSP signal processor, and the dual cores are respectively core1 and core 2; the external instruction memory comprises n external memory spaces for first-dimension FFT processing, namely n one-dimension external memory spaces, and n external memory spaces for second-dimension FFT processing, namely n two-dimension external memory spaces;
the main processor completes the operation processing of the sampling result through the mutual matching of the core1 and the core2, and the method specifically comprises the following steps:
s1, the AD module in the main processor samples the analog IQ signal in the 1 st period, and the core2 stores the sampling result in the 1 st period into the 1 st one-dimensional external memory space of the external data memory;
an AD module in the main processor samples the analog IQ signal in the 2 nd period, and the core2 stores the sampling result in the 2 nd period into the 2 nd one-dimensional external memory space of the external data memory; meanwhile, the core1 reads the sampling result of the 1 st cycle from the 1 st one-dimensional external memory space, performs the first-dimensional FFT processing on the read sampling result of the 1 st cycle, and stores the data after the first-dimensional FFT processing into the 1 st two-dimensional external memory space;
an AD module in the main processor samples the analog IQ signal of the 3 rd period, and the core2 stores the sampling result of the 3 rd period into the 3 rd one-dimensional external memory space of the external data memory; meanwhile, the core1 reads the sampling result of the 2 nd period from the 2 nd one-dimensional external memory space, and performs the first-dimensional FFT processing on the read sampling result of the 2 nd period, and stores the data after the first-dimensional FFT processing into the 2 nd two-dimensional external memory space;
repeating the steps until the core1 finishes the first-dimension FFT processing of the sampling result stored in the nth one-dimension external memory space, and storing the data after the first-dimension FFT processing into the nth two-dimension external memory space;
s2, the core1 reads the data in the same distance bin from each two-dimensional external memory space for the second-dimensional FFT processing and the target detection, and the core2 also reads the data in the different same distance bin from each two-dimensional external memory space for the second-dimensional FFT processing and the target detection.
In step S2, the core1 reads the data in the first half of the distance library for the second-dimension FFT processing and the target detection, and the core2 reads the data in the second half of the distance library for the second-dimension FFT processing and the target detection.
In step S1, after the core2 puts the sampling result into the external memory space of the external data storage, the core2 sends a stored signal to the core 1; after the core1 receives the stored signal, the core1 reads the sampling result from the external memory space of the external data memory to perform the first dimension FFT processing, and after the first dimension FFT processing is completed, the core1 sends a processed signal to the core 2; after the core2 receives the processed signal, the core2 puts the sampling result into the external memory space of the external data memory, and the cycle is carried out in such a way, so that the synchronous work between the core2 and the core1 is achieved;
if the core2 and the core1 cannot work synchronously, the main processor automatically restarts and reports the fault to the upper computer through the data transmission chip.
The radio frequency front end generates a high level pulse after transmitting a sawtooth wave frequency modulation signal, and feeds the high level pulse back to the main processor;
the radar signal processor takes a high-level pulse sent by the radio frequency front end as the reference of the complete machine time sequence; if the main processor can not receive the high level pulse or the number of the received high level pulses is less than the total number of the transmitted sawtooth wave frequency modulation signals, the main processor automatically restarts to reconfigure the radio frequency front end, and reports the fault to the upper computer through the data transmission chip.
The model of the dual-core DSP signal processor used by the main processor is TMS320F28377D, and the manufacturer is Texas instruments.
The invention has the advantages that:
(1) the signal processor is used for processing an echo signal of a sawtooth wave linear frequency modulation signal, the echo signal is a two-dimensional matrix and has a speed dimension and a distance dimension, and the two-dimensional resolution greatly improves the target resolution and the target capacity, wherein the first dimension is the distance dimension, after the first dimension FFT processing, the amplitude of a main lobe and a side lobe of a zero channel is very high, the amplitude on a distance library behind the side lobe is very low, the second dimension is the speed dimension FFT processing, if no static target echo signal exists, the amplitude of the zero channel of the speed dimension is low, if the static target echo signal exists, the amplitude of the zero channel of the speed dimension is high, and subsequently, whether the static target exists or not can be detected by detecting whether the amplitude is high or not.
(2) In the one-dimensional FFT processing process, the dual-core DSP chip achieves synchronous work through interaction signals, when two cores cannot interact with each other, namely cannot synchronously work, faults can be reported to an upper computer, the dual-core DSP chip resets and restarts the dual-core DSP chip, and the faults are eliminated. If the fault is reported repeatedly in a short time, the signal processing hardware is indicated to have a problem, and the hardware needs to be maintained.
(3) The main processor of the invention adopts a dual-core DSP chip, and the operation speed is high. Two cores of the dual-core DSP chip are respectively core1 and core2, the core2 is used for sampling and storing in an external memory, the core1 fetches data from the external memory to perform first-dimension FFT, the result is stored in the external memory, and when the core2 finishes sampling, the core1 delays for one period, namely hundreds of microseconds to finish the first-dimension FFT; and performing second-dimensional FFT on the core1 and the core2 at the same time, and finally sending out the result through the W5300 network interface, wherein the whole processing flow is completed in one frame, no delay in frame unit exists, and the processing result is sent out in real time.
(4) The radio frequency front end can generate a high level pulse after transmitting a sawtooth wave frequency modulation signal, a frame of 128 sawtooth wave frequency modulation signals can be completed, 128 high level pulses can be generated, the high level pulse sent by each front end can be used as the reference of the whole machine time sequence, if the high level pulse cannot be detected or the number of the high level pulses is less than 128, the signal processor can report the radio frequency front end fault to an upper computer, and the signal processor reconfigures the radio frequency front end in a mode of restarting a radar so as to recover normal work.
(5) The clock of the signal processor is provided by the radio frequency front end, so that the radar system can be ensured to keep synchronous consistency, the noise of the front end is reduced, the IQ signal of the front end cannot submerge weak small signals in a detection range, the small signals have enough signal-to-noise ratio, and convenience is brought to finding and distinguishing targets.
Drawings
Fig. 1 is an architecture diagram of a radar signal processor for perimeter defense according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, a radar signal processor for perimeter defense of the present invention includes:
the main processor 1 is a DSP signal processor, that is, a DSP chip, and the DSP signal processor is provided with an AD module in a built-in model of TMS320F28377D, manufactured by Texas Instruments.
The external instruction memory 2 is a FLASH memory chip used for storing radar configuration parameters, the FLASH memory chip can be powered down to reserve the radar configuration parameters, the model is 39VF800A, and the manufacturer is SiliconStorage Technology company.
The external data storage 3 IS an SRAM memory chip for storing radar echo data, and the model IS IS61WV102416BLL, and the manufacturer IS Integrated Silicon Solution company.
An operational amplifier 4 for amplifying analog signals, of type MAX4478, manufactured by Maxim Integrated.
And the data transmission chip 5 is a network chip, is used for transmitting data and receiving upper computer instructions, and has the model of W5300 and the manufacturer of WIZnet company.
The external instruction memory 2, the external data memory 3, the operational amplifier 4 and the data transmission chip 5 are respectively connected with the main processor 1.
The main processor 1 is provided with a plurality of SPI, SCI, HPWM, AD and other external interfaces, and data transmission between the radar signal processor and the radio frequency front end and the radio frequency rear end is met.
The main processor 1 is provided with two SPI interfaces, the two SPI interfaces are connected with a radio frequency front end and respectively connected with a waveform generation chip and a 24G high-frequency transceiving chip of the radio frequency front end, and the radio frequency front end is controlled to transmit sawtooth wave linear frequency modulation signals of a 24G wave band.
The front end of the radio frequency can generate a high level pulse after transmitting a sawtooth wave frequency modulation signal, and the front end of the radio frequency feeds back the high level pulse to the main processor 1; the radar signal processor takes high level pulses sent by the radio frequency front end as the reference of the whole machine time sequence, namely, the high level pulses are taken as a clock, if the main processor 1 cannot receive the high level pulses or the number of the received high level pulses is less than the total number of the transmission of the sawtooth wave frequency modulation signals, the main processor 1 automatically restarts to reconfigure the radio frequency front end, and the main processor 1 reports faults to an upper computer through a data transmission chip 5, and the signal processor reconfigures the radio frequency front end in a radar restarting mode so as to restore normal work. The clock of the signal processor is provided by the radio frequency front end, so that the radar system can be ensured to keep synchronous consistency, the noise of the front end is reduced, the IQ signal of the front end cannot submerge weak small signals in a detection range, the small signals have enough signal-to-noise ratio, and convenience is brought to finding and distinguishing targets.
The radio frequency front end receives a received signal, namely an analog IQ signal, the radio frequency front end returns the received analog IQ signal to the operational amplifier 4, the operational amplifier 4 amplifies a zero intermediate frequency signal in the analog IQ signal, and filters a high frequency signal in the analog IQ signal to prevent interference caused by mixing of a secondary echo, and the operational amplifier 4 sends the processed analog IQ signal to the main processor 1.
An AD module in the main processor 1 samples the processed analog IQ signal to obtain a sampling result, namely a digital IQ signal, the sampling result is stored in an external data memory 3, the main processor 1 performs operation processing on the sampling result, the operation processing is to obtain distance, speed and intensity information through two-dimensional FFT processing, and orientation information is obtained through a two-channel phase comparison angle measurement; the first dimension FFT processing is distance dimension processing, and the second dimension FFT processing is velocity dimension processing.
The main processor 1 reads data from the external data memory 3 for operation processing, wherein the operation processing is to obtain distance, speed and intensity information through two-dimensional FFT processing and obtain azimuth information through a two-channel phase comparison angle measurement; the first dimension FFT processing is distance dimension processing, and the second dimension FFT processing is velocity dimension processing.
The main processor 1 sends the operation result to an upper computer or other equipment, which is a camera in this embodiment, through the data transmission chip 5.
The processor 1 is a dual-core DSP signal processor, and the dual cores are core1 and core2 respectively; the external instruction memory 2 includes 128 external memory spaces for the first-dimensional FFT processing, that is, 128 one-dimensional external memory spaces, and 128 external memory spaces for the second-dimensional FFT processing, that is, 128 two-dimensional external memory spaces;
the main processor 1 completes the operation processing of the sampling result by the mutual cooperation of the core1 and the core2, and specifically comprises the following steps:
s1, the AD module in the main processor 1 samples the analog IQ signal in the 1 st cycle, and the core2 stores the sampling result in the 1 st cycle into the 1 st one-dimensional external memory space of the external data memory 3;
the AD module in the main processor 1 samples the analog IQ signal in the 2 nd period, and the core2 stores the sampling result in the 2 nd period into the 2 nd one-dimensional external memory space of the external data memory 3; meanwhile, the core1 reads the sampling result of the 1 st cycle from the 1 st one-dimensional external memory space, performs the first-dimensional FFT processing on the read sampling result of the 1 st cycle, and stores the data after the first-dimensional FFT processing into the 1 st two-dimensional external memory space;
the AD module in the main processor 1 samples the 3 rd cycle of the analog IQ signal, and the core2 stores the 3 rd cycle of the sampling result into the 3 rd one-dimensional external memory space of the external data memory 3; meanwhile, the core1 reads the sampling result of the 2 nd period from the 2 nd one-dimensional external memory space, and performs the first-dimensional FFT processing on the read sampling result of the 2 nd period, and stores the data after the first-dimensional FFT processing into the 2 nd two-dimensional external memory space;
repeating the steps until the core1 finishes the first-dimension FFT processing of the sampling result stored in the 128 th one-dimension external memory space, and storing the data after the first-dimension FFT processing into the 128 th two-dimension external memory space;
s2, respectively reading data in the same distance library from each two-dimensional external memory space by the core1 to perform second-dimensional FFT processing and target detection, and simultaneously reading different data in the same distance library from each two-dimensional external memory space by the core2 to perform second-dimensional FFT processing and target detection; and the core1 reads the data in the first half of the distance library for second-dimension FFT processing and target detection, and the core2 reads the data in the second half of the distance library for second-dimension FFT processing and target detection.
In step S1, after the core2 puts the sampling result into the external memory space of the external data memory 3, the core2 sends a stored signal to the core 1; after the core1 receives the stored signal, the core1 reads the sampling result from the external memory space of the external data memory 3 to perform the first dimension FFT processing, and after the first dimension FFT processing is completed, the core1 sends a processed signal to the core 2; after the core2 receives the processed signal, the core2 puts the sampling result into the external memory space of the external data memory 3, and the cycle is performed in such a way, so that the synchronous operation between the core2 and the core1 is achieved;
if the core2 and the core1 cannot work synchronously, the main processor 1 automatically restarts, and the main processor 1 reports a fault to the upper computer through the data transmission chip 5, resets and restarts itself, and eliminates the fault. If the fault is reported repeatedly in a short time, the signal processing hardware is indicated to have a problem, and the hardware needs to be maintained.
The main processor of the invention adopts a dual-core DSP chip, and the operation speed is high. Two cores of the dual-core DSP chip are respectively core1 and core2, the core2 is used for sampling and storing in an external memory, the core1 fetches data from the external memory to perform first-dimension FFT, the result is stored in the external memory, and when the core2 finishes sampling, the core1 delays for one period, namely hundreds of microseconds to finish the first-dimension FFT; and performing second-dimensional FFT on the core1 and the core2 at the same time, and finally sending out the result through the W5300 network interface, wherein the whole processing flow is completed in one frame, so that the delay taking the frame as a unit does not exist, and the processing result is sent out in real time.
The signal processor is used for processing an echo signal of a sawtooth wave linear frequency modulation signal, the echo signal is a two-dimensional matrix and has a speed dimension and a distance dimension, and the two-dimensional resolution greatly improves the target resolution and the target capacity, wherein the first dimension is the distance dimension, after the first dimension FFT processing, the amplitude of a main lobe and a side lobe of a zero channel is very high, the amplitude on a distance library behind the side lobe is very low, the second dimension is the speed dimension FFT processing, if no static target echo signal exists, the amplitude of the zero channel of the speed dimension is low, if the static target echo signal exists, the amplitude of the zero channel of the speed dimension is high, and subsequently, whether the static target exists or not can be detected by detecting whether the amplitude is high or not.
The invention is not to be considered as limited to the specific embodiments shown and described, but is to be understood to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. A perimeter defence radar signal processor, comprising: the device comprises a main processor (1), an external instruction memory (2), an external data memory (3), an operational amplifier (4) and a data transmission chip (5);
the main processor (1) is a dual-core DSP signal processor, and an AD module, namely an analog-to-digital conversion module, is arranged in the dual-core DSP signal processor;
the external instruction memory (2) is a FLASH memory chip for storing radar configuration parameters, and the FLASH memory chip can be powered down to reserve the radar configuration parameters;
the external data memory (3) is an SRAM memory chip and is used for storing echo data;
the operational amplifier (4) is used for amplifying the analog signal;
the data transmission chip (5) is a network chip and is used for transmitting data and receiving instructions of an upper computer;
the external instruction memory (2), the external data memory (3), the operational amplifier (4) and the data transmission chip (5) are respectively connected with the main processor (1);
the main processor (1) is provided with two SPI interfaces which are respectively connected with a waveform generating chip and a high-frequency transceiving chip at the radio frequency front end to control the radio frequency front end to transmit sawtooth wave linear frequency modulation signals;
the radio frequency front end is connected with a received back wave signal, namely an analog IQ signal, the radio frequency front end sends the received analog IQ signal to an operational amplifier (4), the operational amplifier (4) amplifies a zero intermediate frequency signal in the analog IQ signal and filters a high frequency signal in the analog IQ signal, and the operational amplifier (4) sends the processed analog IQ signal to a main processor (1);
an AD module in the main processor (1) samples the processed analog IQ signal to obtain a sampling result, namely a digital IQ signal, the sampling result is stored in an external data memory (3), and the main processor (1) also performs operation processing on the sampling result; the arithmetic processing includes: obtaining distance, speed and intensity information through two-dimensional FFT processing, and obtaining azimuth information through a two-channel phase comparison angle measurement; the first dimension FFT processing is distance dimension processing, and the second dimension FFT processing is speed dimension processing;
the main processor (1) sends the operation result to an upper computer or other equipment through a data transmission chip (5).
2. Radar signal processor for perimeter defense according to claim 1,
the main processor (1) is a dual-core DSP signal processor, and the dual cores are respectively core1 and core 2; the external instruction memory (2) comprises n external memory spaces for the first-dimension FFT processing, namely n one-dimension external memory spaces, and n external memory spaces for the second-dimension FFT processing, namely n two-dimension external memory spaces;
the main processor (1) completes the operation processing of the sampling result through the mutual matching of the core1 and the core2, and specifically comprises the following steps:
s1, the AD module in the main processor (1) samples the analog IQ signal in the 1 st period, and the core2 stores the sampling result in the 1 st period into the 1 st one-dimensional external memory space of the external data memory (3);
an AD module in the main processor (1) samples the analog IQ signal under the 2 nd period, and the core2 stores the sampling result of the 2 nd period into the 2 nd one-dimensional external memory space of the external data memory (3); meanwhile, the core1 reads the sampling result of the 1 st cycle from the 1 st one-dimensional external memory space, performs the first-dimensional FFT processing on the read sampling result of the 1 st cycle, and stores the data after the first-dimensional FFT processing into the 1 st two-dimensional external memory space;
an AD module in the main processor (1) samples the analog IQ signal of the 3 rd period, and the core2 stores the sampling result of the 3 rd period into the 3 rd one-dimensional external memory space of the external data memory (3); meanwhile, the core1 reads the sampling result of the 2 nd period from the 2 nd one-dimensional external memory space, and performs the first-dimensional FFT processing on the read sampling result of the 2 nd period, and stores the data after the first-dimensional FFT processing into the 2 nd two-dimensional external memory space;
repeating the steps until the core1 finishes the first-dimension FFT processing of the sampling result stored in the nth one-dimension external memory space, and storing the data after the first-dimension FFT processing into the nth two-dimension external memory space;
s2, the core1 reads the data in the same distance bin from each two-dimensional external memory space for the second-dimensional FFT processing and the target detection, and the core2 also reads the data in the different same distance bin from each two-dimensional external memory space for the second-dimensional FFT processing and the target detection.
3. The perimeter defense radar signal processor as claimed in claim 2, wherein in step S2, the core1 reads the data in the first half of the distance bins for the second dimension FFT processing and target detection, and the core2 reads the data in the second half of the distance bins for the second dimension FFT processing and target detection.
4. The radar signal processor for perimeter defense according to claim 2, wherein in step S1, after the core2 puts the sampling result into the external memory space of the external data memory (3), the core2 sends a stored signal to the core 1; after the core1 receives the stored signal, the core1 reads the sampling result from the external memory space of the external data memory (3) to perform the first dimension FFT processing, and after the first dimension FFT processing is completed, the core1 sends a processed signal to the core 2; after the core2 receives the processed signal, the core2 puts the sampling result into the external memory space of the external data memory (3) again, and the circulation is carried out in such a way, thereby achieving the synchronous work between the core2 and the core 1;
if the core2 and the core1 cannot work synchronously, the main processor (1) is restarted automatically, and the main processor (1) reports faults to the upper computer through the data transmission chip (5).
5. A radar signal processor for perimeter defense according to claim 1, characterized in that, after the rf front end transmits a sawtooth fm signal, it will generate a high level pulse, and the rf front end feeds back the high level pulse to the main processor (1);
the radar signal processor takes a high-level pulse sent by the radio frequency front end as the reference of the complete machine time sequence; if the main processor (1) cannot receive the high-level pulse or the number of the received high-level pulses is less than the total number of the transmitted sawtooth wave frequency modulation signals, the main processor (1) automatically restarts to reconfigure the radio frequency front end, and the main processor (1) reports the fault to the upper computer through the data transmission chip (5).
6. Perimeter defence radar signal processor according to claim 1, characterised in that the dual core DSP signal processor used by the main processor (1) is of the type TMS320F28377D, manufactured by Texas Instruments.
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