CN110837241A - SIP-based sampling processing system - Google Patents
SIP-based sampling processing system Download PDFInfo
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- CN110837241A CN110837241A CN201911156386.4A CN201911156386A CN110837241A CN 110837241 A CN110837241 A CN 110837241A CN 201911156386 A CN201911156386 A CN 201911156386A CN 110837241 A CN110837241 A CN 110837241A
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G05B19/0425—Safety, monitoring
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
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- G05B2219/26—Pc applications
- G05B2219/2612—Data acquisition interface
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Abstract
The invention discloses a sampling processing system based on SIP (Session initiation protocol), and belongs to the technical field of signal processing. The SIP-based sampling processing system comprises narrowband analog-to-digital conversion dies NB _ ADC1 and NB _ ADC2 for sampling narrowband signals; the wideband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC2 are used for sampling wideband signals; the narrowband analog-to-digital conversion dies NB _ ADC1 and NB _ ADC2 and the wideband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC2 are connected with the signal control processing dies; the signal control processing bare chip is used for real-time control and signal processing and sends out signals through the digital-to-analog conversion bare chips DAC _1 and DAC _ 2. The narrowband analog-to-digital conversion dies NB _ ADC1 and NB _ ADC2, the signal control processing die and the digital-to-analog conversion dies DAC _1 and DAC _2 are packaged into a whole through SIP.
Description
Technical Field
The invention relates to the technical field of signal processing, in particular to a broadband multichannel sampling processing system based on SIP (Session initiation protocol).
Background
The informatization technology is developed at a high speed, the capacity and the speed of data stream are greatly improved, and the multichannel sampling processing system is widely applied to the fields of radar, aerospace, communication and the like. Digital signal processing techniques typically include spectral analysis, digital filtering, and the like. Common software and hardware architectures include architectures based on ADC + FPGA + DSP, architectures based on ADC + CPU + hardware acceleration unit, and the like. The ADC is used for sampling, quantizing, encoding and other operations of analog signals, the FPGA and the CPU are used for completing system control, the DSP and the hardware acceleration unit are used for accelerating signal processing, and the speed and the flexibility of the system are considered.
In order to meet the development requirement of miniaturization of electronic devices, the integration of many dies such as ADCs and CPUs on a multilayer substrate based on a SIP package is being widely studied. Compared with a PCB (printed Circuit Board) design, the SIP packaging has short internal connecting line, small parasitic effect and more compact overall layout. The shortening of the average length of the interconnecting lines between the bare chips can effectively reduce the delay and the capacitive reactance of the interconnecting lines, and the data transmission speed can be improved to some extent. The multichannel sampling processing system based on the SIP is gradually becoming a development trend.
Disclosure of Invention
The invention aims to provide a SIP-based sampling processing system, which meets the requirements of a system with wider frequency band coverage and higher sensitivity and has the advantages of miniaturization and online configuration.
The invention provides a sampling processing system based on SIP, comprising:
narrowband analog-to-digital conversion dies NB _ ADC1, NB _ ADC2 for sampling narrowband signals;
the wideband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC2 are used for sampling wideband signals;
the narrowband analog-to-digital conversion dies NB _ ADC1 and NB _ ADC2 and the wideband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC2 are connected with the signal control processing dies; the signal control processing bare chip is used for real-time control and signal processing and sends out signals through the digital-to-analog conversion bare chips DAC _1 and DAC _ 2.
Optionally, the narrowband analog-to-digital conversion dies NB _ ADC1 and NB _ ADC2, the signal control processing die, and the digital-to-analog conversion dies DAC _1 and DAC _2 are packaged into a whole by SIP.
Optionally, the signal control processing bare chip includes a low-speed serial peripheral interface set, a CPU, a hardware acceleration unit, and a multi-channel ADC receiving end;
the parameters of the narrowband analog-to-digital conversion dies NB _ ADC1, NB _ ADC2 and the wideband analog-to-digital conversion dies WB _ ADC1, WB _ ADC2 and the digital-to-analog conversion dies DAC _1 and DAC _2 are configured through the low-speed serial peripheral interface group;
the multichannel ADC receiving end receives serial data of the narrow-band analog-to-digital conversion bare chips NB _ ADC1 and NB _ ADC2 for synchronization, serial conversion and parallel operation; the multichannel ADC receiving end receives parallel data of the broadband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC2 for synchronization and frequency reduction; the hardware acceleration unit receives and processes the data at the receiving end of the multichannel ADC; and the CPU monitors the state of the sampling processing system and configures the hardware acceleration unit on line.
Optionally, the low-speed serial peripheral interface group includes a low-speed serial peripheral interface x4 and a low-speed serial peripheral interface x 2; the low-speed serial peripheral interface x4 comprises 4 low-speed serial peripheral interfaces, and the low-speed serial peripheral interface x2 comprises 2 low-speed serial peripheral interfaces; the 1-way low-speed serial peripheral interface is connected with the 1 bare chip.
The invention provides a SIP-based sampling processing system, which comprises narrowband analog-to-digital conversion bare chips NB _ ADC1 and NB _ ADC2, wherein the narrowband analog-to-digital conversion bare chips NB _ ADC1 and NB _ ADC2 are used for sampling narrowband signals; the wideband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC2 are used for sampling wideband signals; the narrowband analog-to-digital conversion dies NB _ ADC1 and NB _ ADC2 and the wideband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC2 are connected with the signal control processing dies; the signal control processing bare chip is used for real-time control and signal processing and sends out signals through the digital-to-analog conversion bare chips DAC _1 and DAC _ 2. The narrowband analog-to-digital conversion dies NB _ ADC1 and NB _ ADC2, the signal control processing die and the digital-to-analog conversion dies DAC _1 and DAC _2 are packaged into a whole through SIP.
The invention has the following beneficial effects:
(1) narrowband signals are processed through narrowband analog-to-digital conversion bare chips NB _ ADC1 and NB _ ADC2, broadband signals are processed through broadband analog-to-digital conversion bare chips WB _ ADC1 and WB _ ADC2, a hardware acceleration unit is configured on line through a CPU, signal processing is carried out through the hardware acceleration unit, and a wider frequency band is covered;
(2) the narrow-band analog-to-digital conversion bare chips NB _ ADC1 and NB _ ADC2, the signal control processing bare chip and the digital-to-analog conversion bare chips DAC _1 and DAC _2 are packaged into a whole through SIP packaging, and the system integration level is improved; interconnection delays of the narrowband analog-to-digital conversion dies NB _ ADC1, NB _ ADC2 and signal control processing die connection lines are reduced.
Drawings
FIG. 1 is an overall schematic diagram of a SIP-based sample processing system provided by the present invention;
fig. 2 is a schematic diagram of specific connections of a signal control processing die to other dies.
Detailed Description
The following describes a SIP-based sampling processing system according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a sampling processing system based on SIP, as shown in figure 1, comprising:
narrowband analog-to-digital conversion dies NB _ ADC1, NB _ ADC2 for sampling narrowband signals;
the wideband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC2 are used for sampling wideband signals;
the narrowband analog-to-digital conversion dies NB _ ADC1 and NB _ ADC2 and the wideband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC2 are connected with the signal control processing dies; the signal control processing bare chip is used for real-time control and signal processing and sends out signals through the digital-to-analog conversion bare chips DAC _1 and DAC _ 2. The narrowband analog-to-digital conversion dies NB _ ADC1 and NB _ ADC2, the signal control processing die, and the digital-to-analog conversion dies DAC _1 and DAC _2 are packaged into a whole through SIP, so that the system integration level is improved.
Please refer to fig. 2, which is a schematic diagram illustrating the connection between the signal control processing die and other dies. The signal control processing bare chip comprises a low-speed serial peripheral interface group, a CPU, a hardware acceleration unit and a multi-channel ADC receiving end; the parameters of the narrowband analog-to-digital conversion dies NB _ ADC1, NB _ ADC2 and the wideband analog-to-digital conversion dies WB _ ADC1, WB _ ADC2 and the digital-to-analog conversion dies DAC _1 and DAC _2 are configured through the low-speed serial peripheral interface group; the multichannel ADC receiving end receives serial data of the narrow-band analog-to-digital conversion bare chips NB _ ADC1 and NB _ ADC2 for synchronization, serial conversion and parallel operation; the multichannel ADC receiving end receives parallel data of the broadband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC2 for synchronization and frequency reduction; the hardware acceleration unit receives and processes the data at the receiving end of the multichannel ADC; and the CPU monitors the state of the sampling processing system and configures the hardware acceleration unit on line.
The low-speed serial peripheral interface group comprises a low-speed serial peripheral interface x4 and a low-speed serial peripheral interface x 2. The low-speed serial peripheral interface x4 comprises a 4-way low-speed serial peripheral interface, and the low-speed serial peripheral interface x2 comprises a 2-way low-speed serial peripheral interface. Configuring parameters of the narrowband analog-to-digital conversion dies NB _ ADC1 and NB _ ADC2, the wideband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC2, and the digital-to-analog conversion dies DAC _1 and DAC _2 through the low-speed serial peripheral interface group; wherein, 1 way low speed serial peripheral interface links to each other with 1 bare chip. As shown in fig. 2, 4 low-speed serial peripheral interfaces of the low-speed serial peripheral interface x4 are respectively connected to the narrowband analog-to-digital conversion dies NB _ ADC1 and NB _ ADC2 and the wideband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC 2; and 2 paths of low-speed serial peripheral interfaces of the low-speed serial peripheral interface x2 are respectively connected with the digital-to-analog conversion bare chips DAC _1 and DAC _ 2. Receiving serial data of the narrowband analog-to-digital conversion bare chips NB _ ADC1 and NB _ ADC2 through the multichannel ADC receiving end for synchronization and serial-to-parallel operation; receiving parallel data of the wideband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC2 through the multi-channel ADC receiving end for synchronization and frequency reduction; receiving and processing the data at the receiving end of the multichannel ADC through the hardware acceleration unit; and monitoring the state of the sampling processing system through the CPU, and configuring the hardware acceleration unit on line.
The CPU completes initialization operation after the sampling processing system is powered on and reset; the low-speed serial peripheral interface group configures the narrowband analog-to-digital conversion dies NB _ ADC1, NB _ ADC2 and the wideband analog-to-digital conversion dies WB _ ADC1, WB _ ADC 2; after configuration is successful, the CPU configures a multi-channel ADC receiving end, and the multi-channel ADC receiving end performs synchronization, serial-to-parallel conversion or frequency reduction processing on received multi-channel data; and after the data are stable, the CPU configures the hardware acceleration unit and the digital-to-analog conversion bare chips DAC _1 and DAC _2, the system configuration process is completed, and signal sampling and processing are carried out.
The wide-band multi-channel sampling processing system based on the SIP is applied:
the SIP-based sampling processing system is applied to a whole communication monitoring-oriented system. The signal control processing bare chip in the whole machine system is based on a general CPU framework and a local bus, supports low-speed peripheral interfaces such as SPI (serial peripheral interface), SCI (serial peripheral interface) and the like, and is configured with an analog-to-digital conversion bare chip and a digital-to-analog conversion bare chip through the SPI. The hardware acceleration unit accelerates to realize functions of signal filtering, demodulation, decoding and the like, supports various modes, and can monitor the running state of the hardware acceleration unit through the DEBUG mode to assist system testing. Through practical tests, the whole machine system can monitor target signals in a broadband mode and a narrowband mode and can complete communication with a target, the whole machine system works normally, the signal quality is good, and the use requirement of the whole machine is met.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (4)
1. A SIP-based sampling processing system, comprising:
narrowband analog-to-digital conversion dies NB _ ADC1, NB _ ADC2 for sampling narrowband signals;
the wideband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC2 are used for sampling wideband signals;
the narrowband analog-to-digital conversion dies NB _ ADC1 and NB _ ADC2 and the wideband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC2 are connected with the signal control processing dies; the signal control processing bare chip is used for real-time control and signal processing and sends out signals through the digital-to-analog conversion bare chips DAC _1 and DAC _ 2.
2. The SIP-based sampling processing system of claim 1, wherein the narrowband analog-to-digital conversion die NB _ ADC1, NB _ ADC2, the signal control processing die, and the digital-to-analog conversion die DAC _1, DAC _2 are packaged together by SIP.
3. The SIP-based sampling processing system of claim 1 or 2, wherein the signal control processing die comprises a low speed serial peripheral interface bank, a CPU, a hardware acceleration unit, and a multi-channel ADC receiving terminal;
the parameters of the narrowband analog-to-digital conversion dies NB _ ADC1, NB _ ADC2 and the wideband analog-to-digital conversion dies WB _ ADC1, WB _ ADC2 and the digital-to-analog conversion dies DAC _1 and DAC _2 are configured through the low-speed serial peripheral interface group;
the multichannel ADC receiving end receives serial data of the narrow-band analog-to-digital conversion bare chips NB _ ADC1 and NB _ ADC2 for synchronization, serial conversion and parallel operation; the multichannel ADC receiving end receives parallel data of the broadband analog-to-digital conversion dies WB _ ADC1 and WB _ ADC2 for synchronization and frequency reduction; the hardware acceleration unit receives and processes the data at the receiving end of the multichannel ADC; and the CPU monitors the state of the sampling processing system and configures the hardware acceleration unit on line.
4. The SIP-based sampling processing system of claim 3, wherein the low-speed serial peripheral interface group comprises a low-speed serial peripheral interface x4 and a low-speed serial peripheral interface x 2; the low-speed serial peripheral interface x4 comprises 4 low-speed serial peripheral interfaces, and the low-speed serial peripheral interface x2 comprises 2 low-speed serial peripheral interfaces; the 1-way low-speed serial peripheral interface is connected with the 1 bare chip.
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