CN110828561A - 用于在垂直功率器件中减小接触注入物向外扩散的氧插入的Si层 - Google Patents

用于在垂直功率器件中减小接触注入物向外扩散的氧插入的Si层 Download PDF

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CN110828561A
CN110828561A CN201910728974.4A CN201910728974A CN110828561A CN 110828561 A CN110828561 A CN 110828561A CN 201910728974 A CN201910728974 A CN 201910728974A CN 110828561 A CN110828561 A CN 110828561A
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region
substrate
trench
gate
doped
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CN110828561B (zh
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R.哈瑟
S.里奥曼
A.梅瑟
M.波茨尔
M.罗施
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Infineon Technologies Austria AG
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Abstract

用于在垂直功率器件中减小接触注入物向外扩散的氧插入的Si层。一种半导体器件包括：延伸到Si衬底中的栅沟槽，该栅沟槽包括栅电极和将栅电极与Si衬底分离的栅电介质。该半导体器件进一步包括：在Si衬底中与栅沟槽相邻的本体区，该本体区包括沿栅沟槽的侧壁延伸的沟道区；在本体区上方、在Si衬底中的源区；延伸到Si衬底中并且填充有导电材料的接触沟槽，该导电材料接触源区和在接触沟槽底部处的高掺杂本体接触区；以及扩散阻挡结构，其沿沟道区的至少一部分延伸，并且设置在沟道区与高掺杂本体接触区之间。该扩散阻挡结构包括Si和氧掺杂Si的交替层。

Description

用于在垂直功率器件中减小接触注入物向外扩散的氧插入的 Si层
背景技术
随着基于沟槽的晶体管的尺寸缩小，高度掺杂的源/本体接触对在沟道区附近掺杂的净本体的影响变得更加重要。对于与本体掺杂相比具有高2-3个数量级的掺杂水平的源/本体接触扩散的更宽横向分布，器件的Vth（阈值电压）和RonA（导通状态电阻）增加。增加源/本体接触与沟道区之间的距离引起在高漏极电压下耗尽本体，这可能导致高DIBL（漏极引发的阻挡降低）。此外，沟槽宽度和接触宽度两者的工艺窗口变化以及接触不对准必须变得更小以避免这些不利影响（更高的Vth、更高的RonA和更高的DIBL）。
因此，更好地控制源/本体接触掺杂的横向外扩散是合期望的。
发明内容
根据半导体器件的实施例，该半导体器件包括：延伸到Si衬底中的栅沟槽，该栅沟槽包括栅电极和将栅电极与Si衬底分离的栅电介质；在Si衬底中与栅沟槽相邻的本体区，该本体区包括沿栅沟槽的侧壁延伸的沟道区；在本体区上方、在Si衬底中的源区；延伸到Si衬底中并且填充有导电材料的接触沟槽，该导电材料接触源区和在接触沟槽底部处的高掺杂本体接触区；以及扩散阻挡结构，其沿沟道区的至少一部分延伸，并且设置在沟道区与高掺杂本体接触区之间，该扩散阻挡结构包括Si和氧掺杂Si的交替层。
在实施例中，沟道区、栅电极和栅电介质可以比扩散阻挡结构更深地延伸到Si衬底中。
单独地或以组合的形式，栅沟槽可以进一步包括设置在栅电极下方的场电极和将场电极与栅电极和Si衬底分离的场电介质，并且扩散阻挡结构可以在到达场电介质之前终止，以提供从沟道区到本体区下方的漂移区域的电荷载流子通路而不穿过扩散阻挡结构。
单独地或以组合的形式，扩散阻挡结构可以在本体区的上侧之上延伸，并且可以在本体区的上侧处处于源区与本体区之间。
单独地或以组合的形式，半导体器件可以进一步包括：插入在扩散阻挡结构与栅电介质之间的外延Si覆盖层，其中可以掺杂外延Si覆盖层以形成沟道区。
单独地或以组合的形式，Si衬底可以包括在基底Si衬底上生长的一个或多个Si外延层。
根据制造半导体器件的方法的实施例，该方法包括：形成延伸到Si衬底中的栅沟槽，该栅沟槽包括栅电极和将栅电极与Si衬底分离的栅电介质；形成在Si衬底中与栅沟槽相邻的本体区，该本体区包括沿栅沟槽的侧壁延伸的沟道区；形成在Si衬底中、在本体区上方的源区；形成接触沟槽，其延伸到Si衬底中并且填充有导电材料，该导电材料接触源区和在接触沟槽底部处的高掺杂本体接触区；以及形成扩散阻挡结构，其沿沟道区的至少一部分延伸，并且设置在沟道区与高掺杂本体接触区之间，该扩散阻挡结构包括Si和氧掺杂Si的交替层。
在实施例中，形成扩散阻挡结构可以包括：在将栅沟槽蚀刻到Si衬底中之后并且在栅沟槽中形成栅电极和栅电介质之前，在栅沟槽的侧壁上外延生长Si和氧掺杂Si的交替层。
单独地或以组合的形式，该方法可以进一步包括：在栅沟槽被蚀刻到其中的Si衬底的主表面上外延生长Si和氧掺杂Si的交替层。
单独地或以组合的形式，Si和氧掺杂Si的交替层可以在Si衬底的主表面上与在栅沟槽的侧壁上同时地外延生长。
单独地或以组合的形式，该方法可以进一步包括：在扩散阻挡与栅沟槽的侧壁之间形成外延Si覆盖层。
单独地或以组合的形式，该方法可以进一步包括掺杂覆盖层以形成沟道区。
单独地或以组合的形式，该方法可以进一步包括：在将栅沟槽蚀刻到Si衬底中之后并且在外延生长Si和氧掺杂Si的交替层之前，形成场电极和将场电极与在栅沟槽的下部中的Si衬底分离的场电介质；以及在栅沟槽的侧壁上外延生长Si和氧掺杂Si的交替层之后，使场电介质凹陷以暴露沟槽侧壁的未被扩散阻挡结构覆盖的区段，并且在场电介质与Si和氧掺杂Si的交替层之间形成垂直间隙。
单独地或以组合的形式，该方法可以进一步包括：在Si和氧掺杂Si的交替层上以及在沟槽侧壁的未被扩散阻挡结构覆盖的暴露区段上外延生长外延Si覆盖层，外延Si覆盖层填充场电介质与Si和氧掺杂Si的交替层之间的垂直间隙并且形成沟道区。
单独地或以组合的形式，该方法可以进一步包括：在外延Si覆盖层上形成栅电介质。
单独地或以组合的形式，该方法可以进一步包括：通过栅电介质注入掺杂剂，并且将其注入到外延生长在Si和氧掺杂Si的交替层上的外延Si覆盖层的一部分中，以调整半导体器件的阈值电压。
单独地或以组合的形式，该方法可以进一步包括：在形成栅电介质之后，利用形成栅电极的导电材料填充场电极上方的栅沟槽。
单独地或以组合的形式，形成接触沟槽可以包括：通过在Si衬底的主表面上外延生长的Si和氧掺杂Si的交替层、通过源区来蚀刻接触沟槽，并且将其蚀刻到本体区中；将掺杂剂注入到接触沟槽的底部中，并且使掺杂剂退火以在接触沟槽的底部处形成高掺杂本体接触区；以及利用接触源区和高掺杂本体接触区的导电材料来填充接触沟槽。
单独地或以组合的形式，形成本体区和源区可以包括：在形成扩散阻挡结构之后，将相反导电类型的掺杂剂注入到栅沟槽被蚀刻到其中的Si衬底的主表面中。
单独地或以组合的形式，被用来制造半导体器件的Si衬底可以包括在基底Si衬底上生长的一个或多个Si外延层。
在阅读以下详细描述时并且在查看附图时，本领域技术人员将意识到附加的特征和优点。
附图说明
附图的要素不一定相对于彼此是按比例的。同样的附图标记标明对应的类似部分。可以组合各种图示实施例的特征，除非它们彼此排斥。在附图中描绘实施例，并且在以下描述中详述实施例。
图1图示了具有扩散阻挡结构的基于沟槽的半导体器件的实施例的部分横截面视图。
图2是基于沟槽的半导体器件的区的分解视图，其中从器件的沟道区与漂移区域之间的电荷载流子通路的区中省略扩散阻挡结构。
图3A至图3I图示了在制造工艺的不同阶段期间，图1中所示的基于沟槽的半导体器件的相应横截面视图。
具体实施方式
本文中描述的实施例控制用于基于沟槽的晶体管的源/本体接触掺杂的横向外扩散，从而对于高度掺杂的源/本体接触和栅沟槽的给定几何变化允许更窄的Vth、RonA和DIBL分布，和/或对于给定的Vth、RonA和DIBL窗口允许器件的源/本体接触与沟道区之间的横向间距减小。通过插入沿器件的沟道区的至少一部分延伸的扩散阻挡结构来更好地控制源/本体接触掺杂的横向外扩散。扩散阻挡结构包括：设置在器件的高度掺杂的源/本体接触与沟道区之间的Si和氧掺杂Si的交替层。扩散阻挡结构的氧掺杂Si层限制源/本体接触掺杂的横向外扩散，从而控制源/本体接触掺杂在朝向沟道区的方向上的横向外扩散。扩散阻挡结构使得能够实现例如针对窄沟槽MOSFET的更窄Vth分布，或者对于预定的Vth分布宽度，使得能够实现接触沟槽与栅沟槽之间的更小距离。通过结合扩散阻挡结构，可以使沟道区中的电荷载流子迁移率增加例如高达80％。通过结合扩散阻挡结构，还可以使栅泄漏减小例如高达50％，并且与在常规的硅外延层上生长的栅氧化物相比，栅可靠性得以改善。接下来更详细地描述的是具有这样的扩散阻挡结构的半导体器件的实施例，以及对应的制造方法。
图1图示了基于沟槽的半导体器件100的实施例的部分横截面视图。半导体器件100包括：延伸到Si衬底104中的一个或多个栅沟槽102。图1中示出了单个栅沟槽102，然而，半导体器件100可以包括具有相同或相似构造但是在视图外的多个栅沟槽102。Si衬底104可以包括在基底Si衬底上生长的一个或多个Si外延层。设置在每个栅沟槽102中的栅电极106通过栅电介质108与周围的半导体材料绝缘。场电极110可以设置在对应的栅电极106下方、在每个栅沟槽102中，并且通过场电介质112与周围的半导体材料和栅电极106绝缘。栅电介质108和场电介质112可以包括相同或不同的材料，并且可以具有相同或不同的厚度。代替地，场电极110可以形成在与栅沟槽102分离的不同沟槽中或被完全省略，这取决于半导体器件的类型。基于沟槽的半导体器件100可以是功率半导体器件，诸如功率MOSFET（金属氧化物半导体场效应晶体管）、IGBT（绝缘栅双极晶体管）等。
基于沟槽的半导体器件100进一步包括：形成在Si衬底104中的本体区114。本体区114包括沟道区116，该沟道区116沿对应的栅沟槽102的侧壁118垂直延伸。半导体器件100还包括在本体区114上方、在Si衬底104中形成的源区120。通过向栅电极106施加栅电势来控制流过沟道区116的垂直电流。在器件100的漂移区域122下方形成漏极或集电极区（未示出）。取决于器件的类型，可以在漂移区域122中和/或在漂移区域122与漏极/集电极区之间形成附加结构。例如，在IGBT型器件的情况下，可以在漂移区域122中形成电荷补偿结构和/或可以在漂移区域122与漏极/集电极区之间形成场停止层。再一次，具有沟槽栅的任何类型的半导体器件可以利用本文中描述的扩散阻挡教导。
基于沟槽的半导体器件100进一步包括：延伸到Si衬底104中的接触沟槽124。接触沟槽124通过源区120的一部分和本体区114的一部分而与每个相邻的栅沟槽102分离。接触沟槽124填充有导电材料126（诸如掺杂多晶硅、金属等），该导电材料126接触在接触沟槽124的侧壁处的源区120，和在接触沟槽124的底部处的高掺杂本体接触区128。
在接触沟槽124的底部处的高掺杂本体接触区128具有与本体区114相同的掺杂类型，但是处于更高的浓度，以提供与填充了接触沟槽124的导电材料126的良好欧姆接触。例如，在n沟道器件的情况下，源区120和漂移区域122是n型掺杂的，并且本体区114、沟道区116和高掺杂本体接触区128是p型掺杂的。相反地，在p沟道器件的情况下，源区120和漂移区域122是p型掺杂的，并且本体区114、沟道区116和高掺杂本体接触区128是n型掺杂的。在任一种情况下，栅和接触沟槽102、124从相同的前表面130延伸到Si衬底104中。
扩散阻挡结构132沿沟道区116的至少一部分延伸，并且设置在沟道区116与邻近的高掺杂本体接触区128之间。扩散阻挡结构132包括Si 134和氧掺杂Si 136的交替层。Si134和氧掺杂Si 136的交替层形成了通过外延而生长的氧掺杂硅区。在实施例中，每个氧掺杂Si层136的氧浓度低于5e14cm-3。每个氧掺杂Si层136可以具有在原子范围内的厚度（例如，一个或若干个原子厚度）或在纳米范围内的厚度，以确保用于在氧掺杂Si层136上生长Si的足够晶体信息。Si 134和氧掺杂Si 136的交替层可以通过与分别吸附在Si层表面上的氧层相间地外延生长Si层来实现，例如具有对于氧掺杂Si层136的特定有限的厚度以确保充足的Si生长。
图1提供了扩散阻挡结构132的分解视图，该扩散阻挡结构132还可以包括在Si134和氧掺杂Si 136的交替层下方的Si缓冲层138，和/或在Si 134和氧掺杂Si 136的交替层上外延生长的Si覆盖层140。Si缓冲层138可以相对较薄，例如，在2-5 nm厚的范围内。可以在注入或蚀刻步骤之后生长Si缓冲层138。覆盖层140在器件100的该区中提供高载流子迁移率。可以省略缓冲层138和覆盖层140中的一个或两个。扩散阻挡结构132的氧掺杂Si层136限制源/本体接触掺杂的横向外扩散，从而控制从每个高掺杂本体接触区128在朝向相应沟道区116的方向上的横向外扩散。扩散阻挡结构132的氧掺杂Si层136还可以改进器件100的垂直沟道区116内的载流子迁移率。
可以通过向Si晶格引入氧部分单层来形成扩散阻挡结构132的氧掺杂Si层136。间隙地放置氧原子以最小化对Si晶格的破坏。Si原子层134使相邻的氧部分单层136分离。Si134和氧掺杂Si 136的交替层可以通过在不同步骤处具有氧吸收的Si外延来形成。例如，可以在外延过程期间控制温度和气体条件以形成部分氧单层136。可以例如通过控制氧前体（oxygen precursor）到外延室中的引入而在Si的外延层134之间引入/结合氧。所得到的阻挡结构132包括与没有氧的标准Si外延层134相间的单层136，该单层136主要包括Si但具有一定掺杂水平或浓度水平的氧。扩散阻挡结构132还可以包括在Si 134和氧掺杂Si 136的交替层上外延生长的Si覆盖层140，或者可以省略Si覆盖层140。如果提供外延Si覆盖层140，则可以掺杂覆盖层140以形成沟道区116。此外或替换地，扩散阻挡结构132可以在本体区114的上侧115之上延伸，并且在本体区114的上侧处被设置在源区120与本体区114之间。
沟道区116、栅电极106和栅电介质108可以比扩散阻挡结构132更深地延伸到Si衬底104中，延伸到本体区114下方从沟道区116到漂移区域122的没有扩散阻挡结构132的电荷载流子通路区142。如果场电极110存在于栅沟槽102中，则扩散阻挡结构132可以在到达场电介质112之前终止，以形成没有扩散阻挡结构132的电荷载流子通路区142。
图2是基于沟槽的半导体器件100的区的分解视图，其中从沟道区116与漂移区域122之间的电荷载流子通路区142中省略扩散阻挡结构132。通过将栅电势（图2中由“-ve偏压”表示）施加到栅电极106，电流流过沟道区116。在沟道区116与漂移区域122之间的电流通路区142中省略扩散阻挡结构132允许电流在漂移区域122中散开（如由图2中的虚线指示的），这进而减小了半导体器件100的RonA（导通状态电阻）。
图3A至图3I图示了在制造过程的不同阶段期间图1中所示的基于沟槽的半导体器件100的相应横截面视图。
图3A示出了在形成栅沟槽102之后的半导体器件100。可以使用任何常见的沟槽形成过程（诸如掩模和蚀刻）将栅沟槽102蚀刻到Si衬底104中。场电极110可以形成在每个栅沟槽102的下部中，并且通过场电介质112与周围的半导体材料绝缘。场电介质112凹陷到Si衬底104中的第一深度D_field1。
图3B示出了在栅沟槽侧壁118的未被场电介质112覆盖的部分上外延生长扩散阻挡结构132的Si 134和氧掺杂Si 136的交替层之后的半导体器件100。根据该实施例，在将栅沟槽102蚀刻到Si衬底104中之后，但在栅沟槽102中形成栅电极106和栅电介质108之前，在栅沟槽侧壁118上外延生长Si 134和氧掺杂Si 136的交替层。
可以在Si衬底104的顶部主表面130’的暴露部分上外延生长Si 134和氧掺杂Si136的交替层。即，如果在外延生长Si 134和氧掺杂Si 136的交替层期间，Si衬底104的顶部主表面130’的全部或部分没有被掩模或其他类型的绝缘材料覆盖，则Si 134和氧掺杂Si136的交替层也将在Si衬底104的顶部主表面130’的暴露部分上生长。在一个实施例中，Si134和氧掺杂Si 136的交替层在Si衬底104的主表面130’上与在栅沟槽102的侧壁118上同时地外延生长。代替地，可以通过利用诸如绝缘层之类的硬掩模覆盖顶部主表面130’来防止Si 134和氧掺杂Si 136的交替层在Si衬底104的顶部主表面130’上外延生长。在图3B中使用附图标记130’来指示刚好在外延生长Si 134和氧掺杂Si 136的交替层之前的Si衬底102的顶部主表面。在图1中使用附图标记130来指示在全部器件处理完成之后的Si衬底102的顶部主表面，因为Si衬底可以包括在基底Si衬底上生长的一个或多个Si外延层，例如，诸如被用来形成本体区114、源区120、漂移区域122和扩散阻挡结构132的一个或多个外延层。
图3C示出了在场电介质112凹陷到Si衬底104中的第二深度D_field2之后的半导体器件100，其中D_field2 > D_field1。可以使用任何常见的凹陷工艺（例如，诸如蚀刻）使场电介质112更深地凹陷到栅沟槽102中。以这种方式使场电介质112凹陷暴露了沟槽侧壁118的未被扩散阻挡结构132的Si 134和氧掺杂Si 136的交替层覆盖的区段，并且在场电介质112与Si 134和氧掺杂Si 136的交替层之间形成垂直间隙200。
图3D示出了在Si 134和氧掺杂Si 136的交替层上外延生长Si覆盖层140之后的半导体器件100。外延Si覆盖层140填充了场电介质112与Si 134和氧掺杂Si 136的交替层之间的垂直间隙200，如果存在这样的垂直间隙200的话。在一个实施例中，外延Si覆盖层140具有与Si 134和氧掺杂Si 136的交替层相同的标准原位掺杂浓度，并且可以之后利用不同的掺杂剂物质和浓度进行掺杂，以形成半导体器件100的沟道区116。替换地，覆盖层140可以具有与Si 134和氧掺杂Si 136的交替层相比不同的原位掺杂浓度。在任一种情况下，覆盖层140可以被用来实现半导体器件100的沟道区116。
图3E示出了在沿扩散阻挡结构132形成栅电介质108之后的半导体器件100。可以使用用于形成栅电介质的任何常见的半导体制造工艺，例如，诸如电介质沉积和/或热氧化等。
图3F示出了下述过程期间的半导体器件100：该过程为利用具有与本体区114相同导电类型的掺杂剂202注入扩散阻挡结构132的外延Si覆盖层140以形成沿栅沟槽侧壁118的器件100的沟道区116。例如，如果覆盖层140的下部具有与扩散阻挡结构132的其余部分不同的掺杂浓度，则通过栅电介质108注入掺杂剂202，并且将其注入到外延Si覆盖层140中，例如以调整半导体器件100的阈值电压，这是因为在覆盖层140中没有形成Si 134和氧掺杂Si 136的交替层。掺杂剂202可以例如经由四元注入工艺以一角度注入到覆盖层140中。后续通过退火来激活掺杂剂202以形成沟道区116。
图3G示出了在利用导电材料（诸如掺杂的多晶硅、金属等）填充栅沟槽102以形成栅电极106之后的半导体器件100。例如，掺杂的多晶硅可以沉积在栅沟槽102中，并且然后往回蚀刻以形成栅电极106。
图3H示出了在例如通过掺杂剂注入和通过退火激活而在Si衬底104中形成本体区114和源区120之后的半导体器件。具有相反导电类型的掺杂剂被用来形成本体区114和源区120。可以在Si衬底104的前主表面130处将掺杂剂物质直接注入到Si衬底104中，如果在该表面130上没有形成扩散阻挡结构132的话。可以使用常见的掺杂和激活工艺来形成半导体器件的本体区114和源区120。
图3I示出了在通过Si衬底104的主表面130’上外延生长的Si 134和氧掺杂Si 136的交替层、通过源区120蚀刻接触沟槽并且将其蚀刻到本体区114中之后的半导体器件100。可以使用任何常见的沟槽蚀刻工艺。例如，诸如氧化硅之类的硬掩模/绝缘层204可以形成在Si衬底104的前主表面130之上并且被图案化以形成开口。可以往回蚀刻硬掩模204以加宽掩模204中的开口，使得开口比接触沟槽124更宽。在任一种情况下，然后可以各向同性地蚀刻Si衬底104的暴露部分以形成接触沟槽124。
图3I还示出了下述过程期间的半导体器件100，该过程利用具有与本体区114相同导电类型的掺杂剂206注入接触沟槽124的下部，以在本体区114和后续沉积在接触沟槽124中的导电材料126之间提供良好的欧姆接触。通过退火来激活所注入的掺杂剂206在每个接触沟槽124的底部处形成了高掺杂本体接触区128，该高掺杂本体接触区128具有与本体区114相同的掺杂类型，但是处于更高的浓度以提供与后续沉积在接触沟槽124中的导电材料126的良好欧姆接触。每个接触沟槽124填充有导电材料126，该导电材料126接触在接触沟槽124的侧壁处的源区120和在接触沟槽124的底部处的高掺杂本体接触区128，例如，如图1中所示。
扩散阻挡结构132的氧掺杂Si层136限制源/本体接触掺杂的横向外扩散，从而控制从每个高掺杂本体接触区128在朝向沟道区116的方向上的横向外扩散。如上面结合图2所描述的，在沟道区116与漂移区域122之间的电流通路区142中省略扩散阻挡结构132允许电流在漂移区域122中散开，这进而减小了半导体器件100的RonA。通过在形成扩散阻挡结构132的Si 134和氧掺杂Si 136的交替层之后使场电介质112更深地凹陷在栅沟槽102中，可以在沟道区116与漂移区域122之间的电流通路区142中省略扩散阻挡结构132，例如，如图3C中所示。
为了易于描述，使用诸如“之下”、“下方”、“下”、“之上”、“上”等等的空间相对术语来解释一个元件相对于第二元件的定位。除了与图中描绘的取向不同的取向之外，这些术语意图涵盖器件的不同取向。此外，诸如“第一”、“第二”等等的术语也被用来描述各种元件、区、区段等，并且也不意图是限制性的。同样的术语遍及说明书指代同样的元件。
如本文中使用的，术语“具有”、“含有”、“包括”、“包含”等等是开放式术语，其指示所陈述的元件或特征的存在，但并不排除附加的元件或特征。除非上下文另行明确指示的，冠词“一”、“一个”和“该”意图包括复数以及单数。
考虑到上面的变型和应用的范围，应该理解的是，本发明不受前述描述的限制，也不受附图的限制。代替地，本发明仅受所附权利要求及其合法等同物的限制。

Claims (20)

1.一种半导体器件，其包括：
延伸到Si衬底中的栅沟槽，所述栅沟槽包括栅电极和将所述栅电极与所述Si衬底分离的栅电介质；
在所述Si衬底中与所述栅沟槽相邻的本体区，所述本体区包括沿所述栅沟槽的侧壁延伸的沟道区；
在所述本体区上方、在所述Si衬底中的源区；
延伸到所述Si衬底中并且填充有导电材料的接触沟槽，所述导电材料接触所述源区和在所述接触沟槽底部处的高掺杂本体接触区；以及
扩散阻挡结构，其沿所述沟道区的至少一部分延伸，并且设置在所述沟道区与所述高掺杂本体接触区之间，所述扩散阻挡结构包括Si和氧掺杂Si的交替层。
2.根据权利要求1所述的半导体器件，其中所述沟道区、所述栅电极和所述栅电介质比所述扩散阻挡结构更深地延伸到所述Si衬底中。
3.根据权利要求1所述的半导体器件，其中所述栅沟槽进一步包括设置在所述栅电极下方的场电极和将所述场电极与所述栅电极和所述Si衬底分离的场电介质，并且其中所述扩散阻挡结构在到达所述场电介质之前终止，以提供从所述沟道区到所述本体区下方的漂移区域的电荷载流子通路而不穿过所述扩散阻挡结构。
4.根据权利要求1所述的半导体器件，其中，所述扩散阻挡结构在所述本体区的上侧之上延伸，并且在所述本体区的上侧处处于所述源区与所述本体区之间。
5.根据权利要求1所述的半导体器件，进一步包括：插入在所述扩散阻挡结构与所述栅电介质之间的外延Si覆盖层，其中掺杂所述外延Si覆盖层以形成所述沟道区。
6.根据权利要求1所述的半导体器件，其中所述Si衬底包括在基底Si衬底上生长的一个或多个Si外延层。
7.一种制造半导体器件的方法，所述方法包括：
形成延伸到Si衬底中的栅沟槽，所述栅沟槽包括栅电极和将栅电极与所述Si衬底分离的栅电介质；
形成在所述Si衬底中与所述栅沟槽相邻的本体区，所述本体区包括沿所述栅沟槽的侧壁延伸的沟道区；
形成在所述本体区上方、在所述Si衬底中的源区；
形成接触沟槽，其延伸到所述Si衬底中并且填充有导电材料，所述导电材料接触所述源区和在所述接触沟槽底部处的高掺杂本体接触区；以及
形成扩散阻挡结构，其沿所述沟道区的至少一部分延伸，并且设置在所述沟道区与所述高掺杂本体接触区之间，所述扩散阻挡结构包括Si和氧掺杂Si的交替层。
8.根据权利要求7所述的方法，其中形成所述扩散阻挡结构包括：
在将所述栅沟槽蚀刻到所述Si衬底中之后并且在所述栅沟槽中形成所述栅电极和所述栅电介质之前，在所述栅沟槽的侧壁上外延生长Si和氧掺杂Si的交替层。
9.根据权利要求8所述的方法，进一步包括：
在所述栅沟槽被蚀刻到其中的Si衬底的主表面上外延生长Si和氧掺杂Si的交替层。
10.根据权利要求9所述的方法，其中Si和氧掺杂Si的交替层在所述Si衬底的主表面上与在所述栅沟槽的侧壁上同时地外延生长。
11.根据权利要求8所述的方法，进一步包括：
在所述扩散阻挡与所述栅沟槽的侧壁之间形成外延Si覆盖层。
12.根据权利要求11所述的方法，进一步包括：
掺杂所述覆盖层以形成所述沟道区。
13.根据权利要求8所述的方法，进一步包括：
在将所述栅沟槽蚀刻到所述Si衬底中之后并且在外延生长Si和氧掺杂Si的交替层之前，形成场电极和将所述场电极与在所述栅沟槽的下部中的Si衬底分离的场电介质；以及
在所述栅沟槽的侧壁上外延生长Si和氧掺杂Si的交替层之后，使所述场电介质凹陷以暴露沟槽侧壁的未被扩散阻挡结构覆盖的区段，并且在所述场电介质与Si和氧掺杂Si的交替层之间形成垂直间隙。
14.根据权利要求13所述的方法，进一步包括：
在Si和氧掺杂Si的交替层上以及在所述沟槽侧壁的未被所述扩散阻挡结构覆盖的暴露区段上外延生长外延Si覆盖层，所述外延Si覆盖层填充所述场电介质与所述Si和氧掺杂Si的交替层之间的垂直间隙并且形成所述沟道区。
15.根据权利要求14所述的方法，进一步包括：
在外延Si覆盖层上形成所述栅电介质。
16.根据权利要求15所述的方法，进一步包括：
通过所述栅电介质注入掺杂剂，并且将其注入到外延生长在所述Si和氧掺杂Si的交替层上的外延Si覆盖层的一部分中，以调整所述半导体器件的阈值电压。
17.根据权利要求15所述的方法，进一步包括：
在形成所述栅电介质之后，利用形成所述栅电极的导电材料填充所述场电极上方的栅沟槽。
18.根据权利要求9所述的方法，其中形成所述接触沟槽包括：
通过在所述Si衬底的主表面上外延生长的Si和氧掺杂Si的交替层、通过所述源区来蚀刻所述接触沟槽，并且将其蚀刻到所述本体区中；
将掺杂剂注入到所述接触沟槽的底部中，并且使所述掺杂剂退火以在所述接触沟槽的底部处形成高掺杂本体接触区；以及
利用接触所述源区和所述高掺杂本体接触区的导电材料来填充所述接触沟槽。
19.根据权利要求7所述的方法，其中形成所述本体区和所述源区包括：
在形成所述扩散阻挡结构之后，将相反导电类型的掺杂剂注入到所述栅沟槽被蚀刻到其中的Si衬底的主表面中。
20.根据权利要求7所述的方法，其中所述Si衬底包括在基底Si衬底上生长的一个或多个Si外延层。
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