CN110827777A - Display panel driving device and configuration method thereof - Google Patents
Display panel driving device and configuration method thereof Download PDFInfo
- Publication number
- CN110827777A CN110827777A CN201910995518.6A CN201910995518A CN110827777A CN 110827777 A CN110827777 A CN 110827777A CN 201910995518 A CN201910995518 A CN 201910995518A CN 110827777 A CN110827777 A CN 110827777A
- Authority
- CN
- China
- Prior art keywords
- pin
- time
- flash memory
- memory chip
- driving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Abstract
The invention provides a display panel driving device and a configuration method thereof. The display panel driving apparatus includes: the flash memory comprises a first time sequence controller, a second time sequence controller connected with the first time sequence controller and a first flash memory chip connected with the first time sequence controller; the first flash memory chip is used for storing a first drive code and a second drive code; the first time schedule controller is used for loading a first driving code from the first flash memory chip at a first time, establishing driving configuration according to the first driving code, loading a second driving code from the first flash memory chip at a second time and transmitting the second driving code to the second time schedule controller; the second time schedule controller is used for receiving the second driving codes and establishing driving configuration according to the second driving codes, so that the configuration of two time schedule controllers can be completed through one flash memory chip, the number of the flash memory chips can be reduced, the circuit wiring difficulty is simplified, the product cost is reduced, and the utilization rate of storage resources is improved.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel driving apparatus and a configuration method thereof.
Background
With the development of Display technology, flat panel Display devices such as Liquid Crystal Displays (LCDs) have advantages of high image quality, power saving, thin body, and wide application range, and thus are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers, and become the mainstream of Display devices.
Generally, a Liquid Crystal display panel is composed of a Color Filter substrate (CF), a thin film Transistor substrate (TFT), a Liquid Crystal (LC) sandwiched between the Color Filter substrate and the thin film Transistor substrate, and a Sealant frame (Sealant).
When the liquid crystal display panel works, the liquid crystal display panel needs to be driven by an external driving circuit, and the external driving circuit generally comprises: the LCD panel driving Circuit comprises a time sequence control chip (TCON), a Power management chip (Power management IC), a programmable gamma correction chip (P-gamma IC) and the like which are arranged on a Printed Circuit Board (PCB), wherein the time sequence control chip is mainly used for converting Low-Voltage Differential Signaling (LVDS) signals into Mini-LVDS signals with high Low amplitude transmission frequency and generating time sequence signals for driving the LCD panel, the Power management chip is mainly used for generating various voltages for driving the LCD panel, and the programmable gamma correction chip is mainly used for generating gamma voltages.
With the increase of the size and resolution of the liquid crystal display device, the requirements for the time sequence controller of the liquid crystal display device are higher and higher, and for the liquid crystal display device with ultra high definition 120Hz or 8K 120Hz, a single time sequence controller is difficult to meet the production requirements, for this reason, a technical scheme including a plurality of chip drives is proposed, namely, a plurality of time sequence controllers are arranged in the liquid crystal display device to work simultaneously, each time sequence controller correspondingly controls a corresponding sub-area, namely, each time sequence controller can only obtain and process data (such as video data) in the sub-area corresponding to the time sequence controller, each time sequence controller is provided with a Flash memory chip (Flash), namely, each time sequence controller is connected with one Flash memory chip (for example, two Flash memory chips are needed by the two time sequence controllers), each time sequence controller respectively obtains the corresponding drive Code (Code) from the corresponding Flash memory chip, however, each timing controller corresponds to one flash memory chip, which results in excessive flash memory chips, occupying a large amount of wiring space, and each flash memory chip needs one set of connecting wires, for example, each flash memory chip needs five connecting wires of Chip Select (CS), Write Protect (WP), input (DI), output (Do) and Clock (CLK) to connect the timing controller, and meanwhile, a grounding wire is needed to be grounded, a power wire is connected to a power supply, and excessive connecting wires can increase the cost and wiring complexity of a Control Circuit Board (CB); the actual effect of the flash memory chip is only to store the driving code, when the plurality of chips are driven, the actual use of the plurality of flash memory chips is redundant, and the storage resource is not fully utilized, so that the scheme that each existing time schedule controller corresponds to one flash memory chip not only occupies a large wiring space, but also increases the wiring cost and the wiring complexity, and simultaneously, the resource is effectively utilized, and the principle that the design of a circuit board is simple and clear is not met completely.
Disclosure of Invention
The invention aims to provide a display panel driving device which can reduce the number of flash memory chips, simplify the circuit wiring difficulty, reduce the product cost and improve the utilization rate of storage resources.
The present invention also provides a configuration method of a display panel driving apparatus, which can reduce the number of flash memory chips, simplify the circuit wiring difficulty, reduce the product cost, and improve the utilization rate of storage resources.
To achieve the above object, the present invention provides a display panel driving apparatus including: the flash memory comprises a first time sequence controller, a second time sequence controller connected with the first time sequence controller and a first flash memory chip connected with the first time sequence controller;
the first flash memory chip is used for storing a first drive code and a second drive code;
the first time schedule controller is used for loading a first driving code from the first flash memory chip at a first time, establishing driving configuration according to the first driving code, loading a second driving code from the first flash memory chip at a second time and transmitting the second driving code to the second time schedule controller;
the second time schedule controller is used for receiving a second driving code and establishing driving configuration according to the second driving code.
The first time schedule controller comprises a first pin, a second pin and a pin direct-connection module, and the pin direct-connection module is respectively connected with the first pin and the second pin;
the first flash memory chip is connected with the first pin, and the second time schedule controller is connected with the second pin;
the pin direct connection module is used for controlling the first pin to be connected with the second pin at the second time and controlling the first pin to be disconnected with the second pin at the time except the second time.
The display panel driving device also comprises a second flash memory chip, a chip selection module and a debugging and burning module;
the first time schedule controller comprises a first pin, a second pin, a third pin and a pin direct connection module, and the pin direct connection module is respectively connected with the first pin, the second pin and the third pin;
the first flash memory chip is connected with the first pin, the second flash memory chips of the second time schedule controller are connected with the chip selection module, the chip selection module is connected with the second pin, and the debugging and burning module is connected with the third pin;
the first time schedule controller is also used for receiving Mura repair data from the debugging and burning module at a third time and transmitting the Mura repair data to the second flash memory chip;
the pin direct connection module is used for controlling the first pin to be connected with the second pin at the second time, controlling the second pin to be connected with the third pin at the third time, and controlling the second pin to be disconnected with the first pin and the second pin to be disconnected with the third pin at the time except the second time and the third time;
the chip selection module is used for controlling the second pin to be connected with the second time schedule controller at the second time and controlling the second pin to be connected with the second flash memory chip at the time except the second time.
The first flash memory chip comprises a first storage address and a second storage address, and the first driving code and the second driving code are respectively stored in the first storage address and the second storage address.
The display panel driving device also comprises a first circuit board and a second circuit board connected with the first circuit board; the first time schedule controller, the second time schedule controller and the first flash memory chip are all arranged on the first circuit board, and the second flash memory chip is arranged on the second circuit board.
The invention also provides a configuration method of the display panel driving device, which comprises the following steps:
providing a display panel driving device, wherein the display panel driving device comprises a first time sequence controller, a second time sequence controller connected with the first time sequence controller and a first flash memory chip connected with the first time sequence controller;
storing a first driving code and a second driving code in the first flash memory chip;
at a first time, the first time schedule controller loads a first driving code from a first flash memory chip and establishes driving configuration of the first time schedule controller according to the first driving code;
and at a second time, the first time sequence controller loads a second driving code from the first flash memory chip and transmits the second driving code to the second time sequence controller, and the second time sequence controller receives the second driving code and establishes driving configuration according to the second driving code.
The first time schedule controller comprises a first pin, a second pin and a pin direct-connection module, and the pin direct-connection module is respectively connected with the first pin and the second pin; the first flash memory chip is connected with the first pin, and the second time schedule controller is connected with the second pin;
and at the second time, the pin direct connection module controls the first pin to be connected with the second pin, and controls the first pin to be disconnected with the second pin at the time except the second time.
The display panel driving device also comprises a second flash memory chip, a chip selection module and a debugging and burning module;
the first time schedule controller comprises a first pin, a second pin, a third pin and a pin direct connection module, and the pin direct connection module is respectively connected with the first pin, the second pin and the third pin;
the first flash memory chip is connected with the first pin, the second time schedule controller and the second flash memory chip are both connected with the chip selection module, the chip selection module is connected with the second pin, and the debugging and burning module is connected with the third pin;
at a third time, the first time sequence controller receives the Mura repair data from the debugging and burning module and transmits the Mura repair data to the second flash memory chip;
at a second time, the pin direct connection module controls the first pin to be connected with the second pin, and the chip selection module controls the second pin to be connected with the second time schedule controller;
at a third time, the pin direct connection module controls the second pin and the third pin to be connected;
the chip selection module controls the second pin to be connected with the second flash memory chip at the time except the second time;
and at the time except the second time and the third time, the pin direct connection module controls the second pin to be disconnected with the first pin and the second pin to be disconnected with the third pin.
The first flash memory chip comprises a first storage address and a second storage address; and respectively storing the first driving code and the second driving code in the first storage address and the second storage address.
The display panel driving device also comprises a first circuit board and a second circuit board connected with the first circuit board; the first time schedule controller, the second time schedule controller and the first flash memory chip are all arranged on the first circuit board, and the second flash memory chip is arranged on the second circuit board.
The invention has the beneficial effects that: the present invention provides a display panel driving device, including: the flash memory comprises a first time sequence controller, a second time sequence controller connected with the first time sequence controller and a first flash memory chip connected with the first time sequence controller; the first flash memory chip is used for storing a first drive code and a second drive code; the first time schedule controller is used for loading a first driving code from the first flash memory chip at a first time, establishing driving configuration according to the first driving code, loading a second driving code from the first flash memory chip at a second time and transmitting the second driving code to the second time schedule controller; the second time schedule controller is used for receiving the second driving codes and establishing driving configuration according to the second driving codes, so that the configuration of two time schedule controllers can be completed through one flash memory chip, the number of the flash memory chips can be reduced, the circuit wiring difficulty is simplified, the product cost is reduced, and the utilization rate of storage resources is improved. The invention also provides a configuration method of the display panel driving device, which can reduce the number of flash memory chips, simplify the circuit wiring difficulty, reduce the product cost and improve the utilization rate of storage resources.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
FIG. 1 is a diagram of a display panel driving apparatus according to a first embodiment of the present invention;
FIG. 2 is a diagram of a display panel driving apparatus according to a second embodiment of the present invention;
FIG. 3 is a flowchart illustrating a configuration method of a display panel driving apparatus according to the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 1, the present invention provides a display panel driving apparatus, including: the flash memory comprises a first time sequence controller 10, a second time sequence controller 20 connected with the first time sequence controller 10 and a first flash memory chip 30 connected with the first time sequence controller 10;
the first flash memory chip 30 is used for storing a first driver code and a second driver code;
the first timing controller 10 is configured to load a first driving code from the first flash memory chip 30 at a first time, establish a driving configuration according to the first driving code, and load a second driving code from the first flash memory chip 30 at a second time, and transmit the second driving code to the second timing controller 20;
the second timing controller 20 is configured to receive a second driving code and establish a driving configuration according to the second driving code.
Specifically, as shown in fig. 1, in the first embodiment of the present invention, the first timing controller 10 includes a first pin 11, a second pin 12, and a pin direct connection module 13, where the pin direct connection module 13 is connected to the first pin 11 and the second pin 12, respectively;
the first flash memory chip 30 is connected to the first pin 11, and the second timing controller 20 is connected to the second pin 12;
the pin direct connection module 13 is configured to control the first pin 11 to be connected to the second pin 12 at a second time, and control the first pin 11 to be disconnected from the second pin 12 at a time other than the second time.
Preferably, the first pin 11 and the second pin 12 are both Serial Peripheral Interface (SPI) pins.
Specifically, the first timing controller 10 and the second timing controller 20 respectively drive two different regions of the display panel, for example, respectively distinguish a left half region and a right half region of the display panel, and the display panel is preferably an 8K 120Hz liquid crystal display panel.
Specifically, the storage capacity of the first flash chip 30 needs to be larger than the sum of the first driver code, the second driver code, the header file (header file), and other data amount that must be configured.
Further, the display panel driving apparatus further includes a first circuit Board 100, the first timing controller 10, the second timing controller 20, and the first flash memory chip 30 are all disposed on the first circuit Board 100, and the first circuit Board 100 is a Control Board (Control Board) of the display apparatus.
Specifically, the first flash memory chip 30 includes a first storage address and a second storage address, the first driving code and the second driving code are respectively stored in the first storage address and the second storage address, and the first timing controller 10 distinguishes the first driving code and the second driving code according to a difference in addresses.
In the first embodiment of the present invention, during configuration, after the first circuit board 100 is powered on, the first timing controller 10 loads a first driving code from a first storage address to configure the first timing controller 10, then the pin direct-connection module 13 controls the first pin 11 and the second pin 12 to be connected together, the first timing controller 10 loads a second driving code from a second storage address, and transmits the second driving code to the second timing controller 20 through the directly connected first pin 11 and second pin 12 to configure the second timing controller 20.
It should be noted that the time taken for the first timing controller 10 to load the first driving code is less than 200ms, the time taken for the second driving code to be loaded and transmitted to the second timing controller 20 is less than 200ms, and the total time for the first timing controller 10 and the second timing controller 20 to complete configuration is less than 500 ms.
Referring to fig. 2, in a second embodiment of the present invention, compared to the first embodiment, the display panel driving apparatus further includes a second flash memory chip 40, a chip selection module 50 and a debug burning module 60;
the first timing controller 10 comprises a first pin 11 ', a second pin 12', a third pin 14 'and a pin direct connection module 13', wherein the pin direct connection module 13 'is respectively connected with the first pin 11', the second pin 12 'and the third pin 14';
the first flash memory chip 30 is connected with the first pin 11 ', the second timing controller 20 and the second flash memory chip 40 are both connected with the chip selection module 50, the chip selection module 50 is connected with the second pin 12 ', and the debugging and burning module is connected with the third pin 14 ';
the first timing controller 10 is further configured to receive Mura repair data from the debug burning module 60 at a third time, and transmit display-bad (Mura) repair data (i.e., Demura data) to the second flash memory chip 40;
the pin direct connection module 13 ' is used for controlling the first pin 11 ' to be connected with the second pin 12 ' at a second time, controlling the second pin 12 ' to be connected with the third pin 14 ' at a third time, and controlling the second pin 12 ' to be disconnected with the first pin 11 ' and the second pin 12 ' to be disconnected with the third pin 14 ' at times except the second time and the third time;
the chip selecting module 50 is used for controlling the second pin 12 'to be connected to the second timing controller 20 at the second time, and controlling the second pin 12' to be connected to the second flash memory chip 40 at the time other than the second time.
Specifically, the display driving apparatus further includes a first circuit board 100 and a second circuit board 200 connected to the first circuit board 100; the first timing controller 10, the second timing controller 20, and the first flash memory chip 30 are all disposed on the first circuit Board 100, the second flash memory chip is disposed on the second circuit Board 200, the first circuit Board 100 is a Control Board (Control Board) of the display device, and the second circuit Board 200 is an X-Board (X-Board) of the display device.
Preferably, the first pin 11 ', the second pin 12 ' and the third pin 13 ' are Serial Peripheral Interface (SPI) pins.
Specifically, the first timing controller 10 and the second timing controller 20 respectively drive two different regions of the display panel, for example, respectively distinguish a left half region and a right half region of the display panel, and the display panel is preferably an 8K 120Hz liquid crystal display panel.
Specifically, the storage capacity of the first flash chip 30 needs to be larger than the sum of the first driver code, the second driver code, the header file (header file), and other data amount that must be configured.
Specifically, the first flash memory chip 30 includes a first storage address and a second storage address, the first driving code and the second driving code are respectively stored in the first storage address and the second storage address, and the first timing controller 10 distinguishes the first driving code and the second driving code according to a difference in addresses.
In the second embodiment of the present invention, during configuration (including a first time and a second time), after the first circuit board 100 is powered on, the first timing controller 10 loads a first driving code from a first storage address to configure the first timing controller 10, then the pin direct-connection module 13 ' controls the first pin 11 ' and the second pin 12 ' to be connected together, the first timing controller 10 loads a second driving code from a second storage address, and transmits the second driving code to the second timing controller 20 through the directly-connected first pin 11 ' and the second pin 12 ' to configure the second timing controller 20; when the Mura repair data is burned and debugged (i.e. at the third time), the pin directly connecting module 13 'controls the third pin 14' and the second pin 12 'to be connected together, the chip selecting module 50 receives the second control signal and selects the second flash memory chip 40, the burning and debugging module 60 stores the Mura repair data into the second flash memory chip 40 through the second pin 12' and the third pin 14 ', and when the Mura repair data is not configured or burned and debugged, the pin directly connecting module 13' controls the third pin 14 'to be disconnected from the second pin 12' and the first pin 11 'to be disconnected from the second pin 12', and the first timing controller 10 reads the Mura repair data from the second flash memory chip 40.
It should be noted that, in the display panel driving apparatus of the present invention, only one flash memory chip is required for the two timing controllers, and compared with the technical scheme in the prior art in which each timing controller requires one flash memory chip, the display panel driving apparatus of the present invention can effectively reduce the number of flash memory chips, and with the reduction in the number of flash memory chips, the number of connecting wires for connecting the flash memory chips in the printed circuit board is also reduced, so that the wiring complexity is effectively simplified, and at the same time, the area utilization rate of the printed circuit board is improved, the size of the printed circuit board is promoted to be developed toward miniaturization, the product cost is reduced, and the product competitiveness is enhanced.
Referring to fig. 3, the present invention further provides a configuration method of a display panel driving apparatus, including the following steps:
providing a display panel driving device, wherein the display panel driving device comprises a first time schedule controller 10, a second time schedule controller 20 connected with the first time schedule controller 10 and a first flash memory chip 30 connected with the first time schedule controller 10;
storing a first driver code and a second driver code in the first flash memory chip 30;
at a first time, the first timing controller 10 loads a first driving code from the first flash memory chip 30, and establishes a driving configuration of the first timing controller 10 according to the first driving code;
at the second time, the first timing controller 10 loads the second driving code from the first flash memory chip 30 and transmits the second driving code to the second timing controller 20, and the second timing controller 20 receives the second driving code and establishes the driving configuration according to the second driving code.
Specifically, as shown in fig. 2, in the first embodiment of the present invention, the first timing controller 10 includes a first pin 11, a second pin 12, and a pin direct connection module 13, where the pin direct connection module 13 is connected to the first pin 11 and the second pin 12, respectively; the first flash memory chip 30 is connected to the first pin 11, and the second timing controller 20 is connected to the second pin 12;
and at a second time, the pin direct connection module 13 controls the first pin 11 to be connected with the second pin 12, and controls the first pin 11 to be disconnected with the second pin 12 at a time except the second time.
Preferably, the first pin 11 and the second pin 12 are both Serial Peripheral Interface (SPI) pins.
Specifically, the first timing controller 10 and the second timing controller 20 respectively drive two different regions of the display panel, for example, respectively distinguish a left half region and a right half region of the display panel, and the display panel is preferably an 8K 120Hz liquid crystal display panel.
Specifically, the storage capacity of the first flash chip 30 needs to be larger than the sum of the first driver code, the second driver code, the header file (header file), and other data amount that must be configured.
Further, the display panel driving apparatus further includes a first circuit Board 100, the first timing controller 10, the second timing controller 20, and the first flash memory chip 30 are all disposed on the first circuit Board 100, and the first circuit Board 100 is a Control Board (Control Board) of the display apparatus.
Specifically, the first flash memory chip 30 includes a first storage address and a second storage address, the first driving code and the second driving code are respectively stored in the first storage address and the second storage address, and the first timing controller 10 distinguishes the first driving code and the second driving code according to a difference in addresses.
In the second embodiment of the present invention, the display panel driving apparatus further includes a second flash memory chip 40, a chip selecting module 50, and a debugging and burning module 60;
the first timing controller 10 comprises a first pin 11 ', a second pin 12', a third pin 14 'and a pin direct connection module 13', wherein the pin direct connection module 13 'is respectively connected with the first pin 11', the second pin 12 'and the third pin 14';
the first flash memory chip 30 is connected with the first pin 11 ', the second timing controller 20 and the second flash memory chip 40 are both connected with the chip selection module 50, the chip selection module 50 is connected with the second pin 12 ', and the debugging and burning module is connected with the third pin 14 ';
at the third time, the first timing controller 10 receives the Mura repair data from the debug burning module 60 and transmits the Mura repair data to the second flash memory chip 40;
at a second time, the pin direct connection module 13 'controls the first pin 11' to be connected with the second pin 12 ', and the chip selection module 50 controls the second pin 12' to be connected with the second timing controller 20;
at a third time, the pin-direct connection module 13 ' controls the second pin 12 ' and the third pin 14 ' to be connected;
at times other than the second time, the chip selecting module 50 controls the second pin 12' to connect to the second flash memory chip 40;
at times other than the second time and the third time, the pin-direct connection module 13 ' controls the second pin 12 ' to be disconnected from the first pin 11 ' and the second pin 12 ' to be disconnected from the third pin 14 '.
Specifically, the display driving apparatus further includes a first circuit board 100 and a second circuit board 200 connected to the first circuit board 100; the first timing controller 10, the second timing controller 20, and the first flash memory chip 30 are all disposed on the first circuit Board 100, the second flash memory chip is disposed on the second circuit Board 200, the first circuit Board 100 is a Control Board (Control Board) of the display device, and the second circuit Board 200 is an X-Board (X-Board) of the display device.
Preferably, the first pin 11 ', the second pin 12 ' and the third pin 13 ' are Serial Peripheral Interface (SPI) pins.
Specifically, the first timing controller 10 and the second timing controller 20 respectively drive two different regions of the display panel, for example, respectively distinguish a left half region and a right half region of the display panel, and the display panel is preferably an 8K 120Hz liquid crystal display panel.
Specifically, the storage capacity of the first flash chip 30 needs to be larger than the sum of the first driver code, the second driver code, the header file (header file), and other data amount that must be configured.
Specifically, the first flash memory chip 30 includes a first storage address and a second storage address, the first driving code and the second driving code are respectively stored in the first storage address and the second storage address, and the first timing controller 10 distinguishes the first driving code and the second driving code according to a difference in addresses.
It should be noted that, in the display panel driving method of the present invention, only one flash memory chip is needed for two timing controllers, and compared with the technical scheme in the prior art in which each timing controller needs one flash memory chip, the display panel driving method of the present invention can effectively reduce the number of flash memory chips, and with the reduction in the number of flash memory chips, the number of connecting wires for connecting the flash memory chips in the printed circuit board is also reduced, so that the wiring complexity is effectively simplified, and at the same time, the area utilization rate of the printed circuit board is improved, the size of the printed circuit board is promoted to be developed towards miniaturization, the product cost is reduced, and the product competitiveness is enhanced.
In summary, the present invention provides a display panel driving apparatus, including: the flash memory comprises a first time sequence controller, a second time sequence controller connected with the first time sequence controller and a first flash memory chip connected with the first time sequence controller; the first flash memory chip is used for storing a first drive code and a second drive code; the first time schedule controller is used for loading a first driving code from the first flash memory chip at a first time, establishing driving configuration according to the first driving code, loading a second driving code from the first flash memory chip at a second time and transmitting the second driving code to the second time schedule controller; the second time schedule controller is used for receiving the second driving codes and establishing driving configuration according to the second driving codes, so that the configuration of two time schedule controllers can be completed through one flash memory chip, the number of the flash memory chips can be reduced, the circuit wiring difficulty is simplified, the product cost is reduced, and the utilization rate of storage resources is improved. The invention also provides a configuration method of the display panel driving device, which can reduce the number of flash memory chips, simplify the circuit wiring difficulty, reduce the product cost and improve the utilization rate of storage resources.
As described above, it will be apparent to those skilled in the art that other various changes and modifications may be made based on the technical solution and concept of the present invention, and all such changes and modifications are intended to fall within the scope of the appended claims.
Claims (10)
1. A display panel driving apparatus, comprising: the flash memory comprises a first time sequence controller (10), a second time sequence controller (20) connected with the first time sequence controller (10) and a first flash memory chip (30) connected with the first time sequence controller (10);
the first flash memory chip (30) is used for storing a first drive code and a second drive code;
the first time schedule controller (10) is used for loading a first driving code from the first flash memory chip (30) at a first time, establishing driving configuration according to the first driving code, loading a second driving code from the first flash memory chip (30) at a second time, and transmitting the second driving code to the second time schedule controller (20);
the second time schedule controller (20) is used for receiving a second driving code and establishing a driving configuration according to the second driving code.
2. The display panel driving apparatus according to claim 1, wherein the first timing controller (10) comprises a first pin (11), a second pin (12), and a pin-through module (13), the pin-through module (13) being connected to the first pin (11) and the second pin (12), respectively;
the first flash memory chip (30) is connected with the first pin (11), and the second timing controller (20) is connected with the second pin (12);
the pin direct connection module (13) is used for controlling the first pin (11) to be connected with the second pin (12) at the second time and controlling the first pin (11) to be disconnected with the second pin (12) at the time except the second time.
3. The display panel driving apparatus according to claim 1, further comprising a second flash memory chip (40), a chip selection module (50), and a debug burning module (60);
the first time schedule controller (10) comprises a first pin (11 '), a second pin (12'), a third pin (14 ') and a pin direct connection module (13'), wherein the pin direct connection module (13 ') is respectively connected with the first pin (11'), the second pin (12 ') and the third pin (14');
the first flash memory chip (30) is connected with the first pin (11 '), the second timing controller (20) and the second flash memory chip (40) are both connected with the chip selection module (50), the chip selection module (50) is connected with the second pin (12 '), and the debugging and burning module is connected with the third pin (14 ');
the first time schedule controller (10) is further used for receiving Mura repair data from the debugging and burning module (60) at a third time and transmitting the Mura repair data to the second flash memory chip (40);
the pin direct connection module (13 ') is used for controlling the first pin (11 ') to be connected with the second pin (12 ') at a second time, controlling the second pin (12 ') to be connected with the third pin (14 ') at a third time, and controlling the second pin (12 ') to be disconnected with the first pin (11 ') and the second pin (12 ') to be disconnected with the third pin (14 ') at times except the second time and the third time;
the chip selection module (50) is used for controlling the second pin (12 ') to be connected with the second timing controller (20) at a second time and controlling the second pin (12') to be connected with the second flash memory chip (40) at a time except the second time.
4. The display panel driving apparatus according to claim 1, wherein the first flash memory chip (30) includes a first memory address and a second memory address, and the first driving code and the second driving code are stored in the first memory address and the second memory address, respectively.
5. The display panel driving apparatus according to claim 3, further comprising a first circuit board (100) and a second circuit board (200) connected to the first circuit board (100); the first time sequence controller (10), the second time sequence controller (20) and the first flash memory chip (30) are arranged on the first circuit board (100), and the second flash memory chip (40) is arranged on the second circuit board (200).
6. A method for configuring a display panel driving apparatus, comprising:
providing a display panel driving device, wherein the display panel driving device comprises a first time sequence controller (10), a second time sequence controller (20) connected with the first time sequence controller (10) and a first flash memory chip (30) connected with the first time sequence controller (10);
storing a first driver code and a second driver code in the first flash memory chip (30);
at a first time, the first time schedule controller (10) loads a first driving code from a first flash memory chip (30), and establishes a driving configuration of the first time schedule controller (10) according to the first driving code;
and at a second time, the first time schedule controller (10) loads a second driving code from the first flash memory chip (30) and transmits the second driving code to the second time schedule controller (20), and the second time schedule controller (20) receives the second driving code and establishes driving configuration according to the second driving code.
7. The method according to claim 6, wherein the first timing controller (10) comprises a first pin (11), a second pin (12), and a pin-through module (13), and the pin-through module (13) is connected to the first pin (11) and the second pin (12), respectively; the first flash memory chip (30) is connected with the first pin (11), and the second timing controller (20) is connected with the second pin (12);
and at a second time, the pin direct connection module (13) controls the first pin (11) to be connected with the second pin (12), and controls the first pin (11) to be disconnected with the second pin (12) at a time except the second time.
8. The method of claim 6, wherein the display panel driving apparatus further comprises a second flash memory chip (40), a chip selection module (50), and a debug burning module (60);
the first time schedule controller (10) comprises a first pin (11 '), a second pin (12'), a third pin (14 ') and a pin direct connection module (13'), wherein the pin direct connection module (13 ') is respectively connected with the first pin (11'), the second pin (12 ') and the third pin (14'); the first flash memory chip (30) is connected with the first pin (11 '), the second timing controller (20) and the second flash memory chip (40) are both connected with the chip selection module (50), the chip selection module (50) is connected with the second pin (12 '), and the debugging and burning module is connected with the third pin (14 ');
at a third time, the first time sequence controller (10) receives the Mura repair data from the debugging and burning module (60) and transmits the Mura repair data to the second flash memory chip (40);
at a second time, the pin direct connection module (13 ') controls the first pin (11') to be connected with the second pin (12 '), and the chip selection module (50) controls the second pin (12') to be connected with the second timing controller (20);
at a third time, the pin-direct module (13 ') controls the second pin (12 ') and the third pin (14 ') to be connected;
at times other than the second time, the chip selection module (50) controls the second pin (12') to connect to the second flash memory chip (40);
at times other than the second time and the third time, the pin-direct module (13 ') controls the second pin (12 ') to be disconnected from the first pin (11 ') and the second pin (12 ') to be disconnected from the third pin (14 ').
9. The method of claim 6, wherein the first flash memory chip (30) comprises a first memory address and a second memory address; and respectively storing the first driving code and the second driving code in the first storage address and the second storage address.
10. The method of configuring a display panel driving apparatus according to claim 8, wherein the display panel driving apparatus further comprises a first circuit board (100) and a second circuit board (200) connected to the first circuit board (100); the first time sequence controller (10), the second time sequence controller (20) and the first flash memory chip (30) are arranged on the first circuit board (100), and the second flash memory chip (40) is arranged on the second circuit board (200).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910995518.6A CN110827777B (en) | 2019-10-18 | 2019-10-18 | Display panel driving device and configuration method thereof |
| PCT/CN2019/114196 WO2021072806A1 (en) | 2019-10-18 | 2019-10-30 | Display panel driving device and configuration method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910995518.6A CN110827777B (en) | 2019-10-18 | 2019-10-18 | Display panel driving device and configuration method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110827777A true CN110827777A (en) | 2020-02-21 |
| CN110827777B CN110827777B (en) | 2020-11-24 |
Family
ID=69549734
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910995518.6A Active CN110827777B (en) | 2019-10-18 | 2019-10-18 | Display panel driving device and configuration method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110827777B (en) |
| WO (1) | WO2021072806A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111326125A (en) * | 2020-04-07 | 2020-06-23 | Tcl华星光电技术有限公司 | TCON time sequence control signal control method and driving circuit |
| CN111554225A (en) * | 2020-05-20 | 2020-08-18 | Tcl华星光电技术有限公司 | Display device, and speckle eliminating system and speckle eliminating method thereof |
| CN113763884A (en) * | 2021-09-18 | 2021-12-07 | 京东方科技集团股份有限公司 | Data connector, data providing module, method and display device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114063924A (en) * | 2021-11-18 | 2022-02-18 | 惠州华星光电显示有限公司 | Power management chip data configuration method, configuration framework and display panel |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0954564A (en) * | 1995-08-10 | 1997-02-25 | Iida Denshi Sekkei Kk | Display information supplying system to dot matrix electric display machine as well as display information adapter device used for this system |
| US20050047671A1 (en) * | 2003-09-02 | 2005-03-03 | Ho-Hsing Yang | [circuit and method for enhancing motion picture quality ] |
| KR100611501B1 (en) * | 2003-08-13 | 2006-08-11 | (주)씨앤에스 테크놀로지 | Method for interfacing efficacious of display data intersystem |
| KR100749785B1 (en) * | 2006-08-31 | 2007-08-17 | 삼성전자주식회사 | shift-resister and drive circuit of an LCD using the same |
| JP2011150306A (en) * | 2009-12-21 | 2011-08-04 | Renesas Electronics Corp | Semiconductor processing device |
| CN105244004A (en) * | 2015-11-23 | 2016-01-13 | 深圳市华星光电技术有限公司 | Control board and liquid crystal display with control board |
| CN106057165A (en) * | 2016-08-12 | 2016-10-26 | 昆山龙腾光电有限公司 | Control device used for liquid crystal display apparatus and control method thereof |
| CN107680554A (en) * | 2017-11-22 | 2018-02-09 | 深圳市华星光电技术有限公司 | Display device drive system and method |
| CN109358458A (en) * | 2018-10-22 | 2019-02-19 | 深圳市华星光电半导体显示技术有限公司 | Display device |
| CN109389959A (en) * | 2018-12-12 | 2019-02-26 | 惠科股份有限公司 | The driving framework and method of display panel |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104064141B (en) * | 2014-06-12 | 2016-12-14 | 京东方科技集团股份有限公司 | Display floater optical compensating member, display floater and optical compensation method |
| KR102257202B1 (en) * | 2014-12-26 | 2021-05-28 | 엘지디스플레이 주식회사 | Multi timming controlls and display device using the same |
| CN107705769B (en) * | 2017-11-21 | 2021-03-02 | Tcl华星光电技术有限公司 | Display device driving system and method and display device |
| CN108109573A (en) * | 2017-12-06 | 2018-06-01 | 深圳市华星光电半导体显示技术有限公司 | The update method of the Mura offset datas of display panel |
-
2019
- 2019-10-18 CN CN201910995518.6A patent/CN110827777B/en active Active
- 2019-10-30 WO PCT/CN2019/114196 patent/WO2021072806A1/en active Application Filing
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0954564A (en) * | 1995-08-10 | 1997-02-25 | Iida Denshi Sekkei Kk | Display information supplying system to dot matrix electric display machine as well as display information adapter device used for this system |
| KR100611501B1 (en) * | 2003-08-13 | 2006-08-11 | (주)씨앤에스 테크놀로지 | Method for interfacing efficacious of display data intersystem |
| US20050047671A1 (en) * | 2003-09-02 | 2005-03-03 | Ho-Hsing Yang | [circuit and method for enhancing motion picture quality ] |
| KR100749785B1 (en) * | 2006-08-31 | 2007-08-17 | 삼성전자주식회사 | shift-resister and drive circuit of an LCD using the same |
| JP2011150306A (en) * | 2009-12-21 | 2011-08-04 | Renesas Electronics Corp | Semiconductor processing device |
| CN105244004A (en) * | 2015-11-23 | 2016-01-13 | 深圳市华星光电技术有限公司 | Control board and liquid crystal display with control board |
| CN106057165A (en) * | 2016-08-12 | 2016-10-26 | 昆山龙腾光电有限公司 | Control device used for liquid crystal display apparatus and control method thereof |
| CN107680554A (en) * | 2017-11-22 | 2018-02-09 | 深圳市华星光电技术有限公司 | Display device drive system and method |
| CN109358458A (en) * | 2018-10-22 | 2019-02-19 | 深圳市华星光电半导体显示技术有限公司 | Display device |
| CN109389959A (en) * | 2018-12-12 | 2019-02-26 | 惠科股份有限公司 | The driving framework and method of display panel |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111326125A (en) * | 2020-04-07 | 2020-06-23 | Tcl华星光电技术有限公司 | TCON time sequence control signal control method and driving circuit |
| CN111326125B (en) * | 2020-04-07 | 2021-06-01 | Tcl华星光电技术有限公司 | TCON time sequence control signal control method and driving circuit |
| US11410623B2 (en) | 2020-04-07 | 2022-08-09 | Tcl China Star Optoelectronics Technology Co., Ltd. | Control method of time sequential control signal and driving circuit |
| CN111554225A (en) * | 2020-05-20 | 2020-08-18 | Tcl华星光电技术有限公司 | Display device, and speckle eliminating system and speckle eliminating method thereof |
| CN111554225B (en) * | 2020-05-20 | 2023-02-28 | Tcl华星光电技术有限公司 | Display device, and speckle eliminating system and speckle eliminating method thereof |
| CN113763884A (en) * | 2021-09-18 | 2021-12-07 | 京东方科技集团股份有限公司 | Data connector, data providing module, method and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021072806A1 (en) | 2021-04-22 |
| CN110827777B (en) | 2020-11-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110827777B (en) | Display panel driving device and configuration method thereof | |
| CN108597470B (en) | Display device driving system and method and display device | |
| CN107680554B (en) | Display device driving system and method | |
| CN107705769B (en) | Display device driving system and method and display device | |
| KR100423693B1 (en) | Liquid crystal display device | |
| EP1414013A2 (en) | Liquid crystal display and driving method thereof | |
| US8860711B2 (en) | Timing controller and liquid crystal display using the same | |
| JP2006251772A (en) | Driving circuit of liquid crystal display | |
| KR100380258B1 (en) | Display unit, electronic instrument using the same, and method of inspecting the display unit | |
| US7973785B2 (en) | Control board and display apparatus having the same | |
| US11934068B2 (en) | Display module and manufacturing method thereof, and mobile terminal | |
| CN103971647A (en) | Display driver device | |
| CN111199716A (en) | Display device and method of driving the same | |
| CN106228939A (en) | LCD TV driving method, device and LCD TV drive circuit board | |
| CN107300794B (en) | Liquid crystal display panel driving circuit and liquid crystal display panel | |
| CN111292698A (en) | Drive circuit and display device | |
| US9257079B2 (en) | Data driving system and chip for liquid crystal panel as well as liquid crystal display device | |
| CN107342060B (en) | Drive chip and display device | |
| US8957884B2 (en) | Integrated circuit device and electronic apparatus | |
| KR20150073642A (en) | Timing controller and display apparatus having the same | |
| CN105679268A (en) | Display assembly | |
| CN113539137A (en) | Novel display device and display system | |
| CN107300795B (en) | LCD control circuit board | |
| CN110767182B (en) | Screen display control system and screen display control method | |
| CN111063314A (en) | Display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |