CN111554225B - Display device, and speckle eliminating system and speckle eliminating method thereof - Google Patents
Display device, and speckle eliminating system and speckle eliminating method thereof Download PDFInfo
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- CN111554225B CN111554225B CN202010429458.4A CN202010429458A CN111554225B CN 111554225 B CN111554225 B CN 111554225B CN 202010429458 A CN202010429458 A CN 202010429458A CN 111554225 B CN111554225 B CN 111554225B
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
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- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
The invention provides a display device and a speckle removing system and a speckle removing method thereof, wherein the speckle removing system comprises: n time schedule controllers which are mutually cascaded, wherein N is an integer which is more than or equal to 2; the flash memory chip is used for storing the speckle eliminating data of the display device; the flash memory chip and the time sequence controller are connected sequentially through N buses, and the flash memory chip is connected with the first time sequence controller through a first bus; and in the L stage, the L-th time sequence controller is connected with the flash memory chip through the front (L-1) time sequence controllers and the front L buses, and reads the L-th speckle eliminating data in the flash memory chip, wherein L is an integer which is more than or equal to 1 and less than or equal to N. The sequential controller at the rear position in the spot-eliminating system realizes sequential connection with the flash memory chip through the sequential controller at the front position and the bus in respective stages, reduces wiring between the sequential controller and the flash memory chip, simplifies a circuit, reduces manufacturing cost, releases the area of a control panel, and is favorable for layout and wiring of the control panel.
Description
Technical Field
The present disclosure relates to display technologies, and in particular, to a display device, and a speckle removing system and a speckle removing method thereof.
Background
Due to defects in the display panel manufacturing process, the display panel often has various mura (non-uniform brightness of the display panel, causing various speckles), so a timing controller is required to perform a speckle reduction (Demura) process on the display panel.
In the prior art, as shown in fig. 1, the display device includes at least two timing controllers 102 respectively corresponding to different regions of the display panel 101, the timing controllers 102 are cascaded with each other, and the timing controllers 102 are respectively connected to the gating module 104, and are connected to the flash memory chip 103 by selective conduction of the gating module 104, so as to read the speckle reduction data in the flash memory chip 103.
Therefore, the conventional display device has problems of high cost and complicated wiring.
Disclosure of Invention
The invention provides a display device, a spot eliminating system and a spot eliminating method thereof, aiming at solving the problems of high cost and complicated wiring of the existing display device.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the present invention provides a speckle removing system for a display device, comprising:
n time schedule controllers which are mutually cascaded, wherein N is an integer which is more than or equal to 2;
the flash memory chip is used for storing the speckle eliminating data of the display device;
the flash memory chip and the time sequence controller are sequentially connected through N buses, and the flash memory chip is connected with the first time sequence controller through a first bus;
in the L stage, the L time sequence controller is connected with the flash memory chip through the front (L-1) time sequence controllers and the front L buses to read the L speckle eliminating data in the flash memory chip, wherein L is an integer which is more than or equal to 1 and less than or equal to N
In the speckle removing system provided by the invention, the Mth time sequence controller comprises an Mth switching module, an Mth reading module, an Mth detecting module and an Mth switching control module, wherein the Mth switching module, the Mth reading module and the Mth detecting module are positioned in the Mth time sequence controller, and M is an integer which is more than or equal to 1 and less than N.
In the speckle removing system provided by the invention, the Mth switching control module is positioned in the Mth time schedule controller; the Mth reading module is connected with the flash memory chip through the front (M-1) time sequence controllers and the front M buses and is used for reading Mth speckle removing data in the flash memory chip, the Mth detection module is connected with the Mth reading module and is used for detecting the Mth speckle removing data, and the Mth switching control module is connected with the Mth detection module and the Mth switching module and is used for controlling the Mth switching module to carry out switching connection according to the detection result of the Mth detection module.
In the speckle removing system provided by the invention, the Mth switching control module is positioned in the Mth +1 time schedule controller; the Mth reading module is connected with the flash memory chip through the front (M-1) time sequence controllers and the front M buses and is used for reading Mth speckle removing data in the flash memory chip, the Mth detection module is connected with the Mth reading module and is used for detecting the Mth speckle removing data, and the Mth switching control module is connected with the Mth switching module and is used for controlling the Mth switching module to carry out switching connection according to a level transmission signal of the Mth time sequence controller.
The present invention also provides a display device, comprising:
the display panel comprises at least two sub-display areas;
the control panel comprises N time sequence controllers which are mutually cascaded, wherein N is an integer which is more than or equal to 2; the time sequence controllers correspond to the sub display areas one by one and are used for respectively carrying out speckle removing treatment on the corresponding sub display areas;
the printed circuit board comprises a flash memory chip, and the flash memory chip is used for storing the speckle eliminating data of the display device;
the flash memory chip and the time sequence controller are sequentially connected through N buses, and the flash memory chip is connected with the first time sequence controller through a first bus;
and in the L stage, the L-th time sequence controller is connected with the flash memory chip through the front (L-1) time sequence controllers and the front L buses to read the L-th speckle eliminating data in the flash memory chip, wherein L is an integer which is more than or equal to 1 and less than or equal to N.
The display device provided by the invention is subjected to speckle elimination by adopting the speckle elimination system provided by the invention, the speckle elimination system comprises a flash memory chip and N time sequence controllers which are mutually cascaded, wherein N is an integer greater than or equal to 2, the flash memory chip stores speckle elimination data of the display device, the flash memory chip and the time sequence controllers are sequentially connected through N buses, and the flash memory chip is connected with a first time sequence controller through a first bus; the speckle removing method comprises the following steps:
in the Mth stage, the Mth time sequence controller is connected with the flash memory chip through the front (M-1) time sequence controllers and the front M buses, and Mth speckle eliminating data in the flash memory chip are read, wherein M is an integer which is more than or equal to 1 and less than N;
and in the Nth stage, the Nth time sequence controller is connected with the flash memory chip through the front (N-1) time sequence controllers and the front N buses, and reads the Nth speckle eliminating data in the flash memory chip.
In the method for removing the speckle, in the mth stage, the mth timing controller is connected to the flash memory chip through the first (M-1) timing controllers and the first M buses, and the step of reading the mth speckle removing data in the flash memory chip includes:
the Mth reading module reads Mth speckle removing data in the flash memory chip;
the Mth detection module detects the Mth speckle removing data to obtain a detection result;
and the Mth switching control module controls the Mth switching module to carry out switching connection according to the detection result.
In the speckle removing method provided by the invention, the step of detecting the Mth speckle removing data by the Mth detection module to obtain a detection result comprises the following steps:
the Mth detection module detects a storage address of the Mth speckle reduction data and judges whether the storage address is the last address of the Mth speckle reduction data.
In the speckle removing method provided by the invention, the step of controlling the Mth switching module to switch connection by the Mth switching control module according to the detection result comprises the following steps:
if the detection result is that the storage address is the last bit address of the Mth speckle removing data, the Mth switching control module controls the Mth switching module to conduct an (M + 1) th bus and an Mth bus, so that the (M + 1) th reading module is connected with the flash memory chip through the first M time schedule controllers and the first (M + 1) buses, and the speckle removing method enters an (M + 1) th stage;
and if the detection result is that the storage address is not the last address of the Mth speckle reduction data, repeating the steps in the Mth stage.
In the speckle removing method provided by the present invention, in the nth stage, the nth timing controller is connected to the flash memory chip through the first (N-1) timing controllers and the first N buses, and the step of reading nth speckle removing data in the flash memory chip includes:
the Nth reading module reads the Nth speckle eliminating data in the flash memory chip;
the Nth detection module detects the storage address of the Nth speckle removing data and judges whether the storage address is the last address of the Nth speckle removing data;
if the detection result is that the storage address is the last address of the Nth speckle reduction data, ending; if the detection result is that the storage address is not the last address of the Nth speckle reduction data, repeating the steps in the Nth stage. .
The invention provides a display device and a spot eliminating system and a spot eliminating method thereof, wherein the spot eliminating system comprises: n time schedule controllers which are mutually cascaded, wherein N is an integer which is more than or equal to 2; the flash memory chip is used for storing the speckle eliminating data of the display device; the flash memory chip and the time sequence controller are connected sequentially through N buses, and the flash memory chip is connected with the first time sequence controller through a first bus; and in the L stage, the L-th time sequence controller is connected with the flash memory chip through the front (L-1) time sequence controllers and the front L buses, and reads the L-th speckle eliminating data in the flash memory chip, wherein L is an integer which is more than or equal to 1 and less than or equal to N. The speckle eliminating system provided by the embodiment of the invention directly connects the time schedule controller at the first position in the cascaded time schedule controllers with the flash memory chip, and the time schedule controller at the rear position realizes the connection with the flash memory chip through the time schedule controller at the front position in each stage, thereby realizing the sequential connection of the time schedule controller and the flash memory chip and acquiring the corresponding speckle eliminating data; compared with the prior art, the method avoids the independent connection of each time sequence controller and the flash memory chip, reduces the wiring between the time sequence controller and the flash memory chip, simplifies the circuit, reduces the manufacturing cost, releases the area of the control panel and is beneficial to the layout and wiring of the control panel.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a display device in the prior art.
Fig. 2 is a first structural block diagram of a speckle reduction system according to an embodiment of the present invention.
Fig. 3 is a second structural block diagram of a speckle reduction system according to an embodiment of the present invention.
Fig. 4 is a block diagram of a third structure of a speckle reduction system according to an embodiment of the present invention.
Fig. 5 is a fourth structural block diagram of the speckle reduction system according to the embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Fig. 7 is a first flowchart illustrating a speckle reduction method for a display device according to an embodiment of the present invention.
Fig. 8 is a schematic flowchart of a second method for removing speckle in a display device according to an embodiment of the present invention.
Detailed Description
While the embodiments and/or examples of the present invention will be described in detail below in conjunction with the specific embodiments of the present invention, it is to be understood that the embodiments and/or examples described below are only a part of the embodiments and/or examples of the present invention, and not all of the embodiments and/or examples. All other embodiments and/or examples, which can be obtained by a person skilled in the art without inventive step, are within the scope of protection of the present invention.
Directional terms used in the present invention, such as [ upper ], [ lower ], [ left ], [ right ], [ front ], [ rear ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terminology is used for the purpose of describing and understanding the invention and is in no way limiting. The terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature.
The invention provides a display device, a speckle removing system and a speckle removing method thereof, which are used for solving the problems of high cost and complex wiring of the conventional display device.
In an embodiment, referring to fig. 2, fig. 2 is a block diagram illustrating a first structure of a speckle reduction system of a display device according to an embodiment of the present invention. The plaque removal system comprises:
n time schedule controllers Tcon which are mutually cascaded, wherein N is an integer which is more than or equal to 2;
the flash memory chip flash is used for storing the speckle eliminating data of the display device;
the flash memory chip flash and the time schedule controller Tcon are sequentially connected through N buses, and the flash memory chip is connected with the first time schedule controller Tcon1 through a first bus SPI 1;
and in the L stage, the L-th time sequence controller is connected with the flash memory chip flash through the front (L-1) time sequence controllers and the front L buses, and reads the L-th speckle eliminating data in the flash memory chip flash, wherein L is an integer which is more than or equal to 1 and less than or equal to N.
The present embodiment provides a speckle reduction system for a display device, in which a first-order timing controller in a cascaded timing controller is directly connected to a flash memory chip, and a later-order timing controller realizes connection to the flash memory chip through a former-order timing controller in each stage, so as to realize sequential connection between the timing controller and the flash memory chip and obtain corresponding speckle reduction data; compared with the prior art, the method avoids the independent connection of each time sequence controller and the flash memory chip, reduces the wiring between the time sequence controller and the flash memory chip, simplifies the circuit and reduces the manufacturing cost.
In an embodiment, referring to fig. 3 and 4, fig. 3 and 4 respectively show a second and a third block diagrams of a speckle reduction system of a display device according to an embodiment of the present invention. As shown in the drawing, the mth timing controller TconM includes an mth switching module SwitchM, an mth reading module ReadM, an mth detecting module TestM, and an mth switching control module CtlM, and the mth switching module SwitchM, the mth reading module ReadM, the mth detecting module TestM, and the mth switching control module CtlM are all located within the mth timing controller TconM. Meanwhile, the mth timing controller TconM further includes an mth bus interface SPIM1 and an M +1 th bus interface SPIM2. Where M is an integer of 1 or more and N or less, that is, the mth timing controller TconM represents any one of the first to second last timing controllers, for example, the first timing controller Tcon1 shown in the figure.
In one embodiment, referring to fig. 3, the mth bus interface SPIM1 is connected to the mth bus SPIM, and is also directly connected to the mth reading module ReadM, that is, the mth reading module ReadM is directly connected to the mth bus SPIM1 through the mth bus interface SPIM1, and is configured to read the mth speckle reduction data in the flash memory chip flash, and the reading operation of the mth reading module ReadM is not limited by the mth switching module SwitchM.
The Mth detection module TestM is connected with the Mth reading module ReadM and is used for detecting the Mth speckle elimination data read by the Mth reading module ReadM and obtaining a detection result. Specifically, the detection is to detect the storage address of the mth speckle reduction data and judge whether the storage address is the last address of the mth speckle reduction data.
The mth switching control module CtlM is connected to the mth detection module TestM, and is configured to output a control signal to the mth switching module SwitchM according to a detection result of the mth detection module TestM, so as to control the mth switching module SwitchM to perform switching connection.
The mth switching module SwitchM is connected to the mth switching control module CtlM, the mth bus interface SPIM1, and the M +1 th bus interface SPIM2, and is configured to perform switching connection according to a control signal of the mth switching control module CtlM, where the switching connection mainly refers to connection between the mth switching module SwitchM and the mth bus interface SPIM1, and connection between the mth bus and the M +1 th bus interface SPIM2, so as to implement conduction between the mth bus and the M +1 th bus.
For example, when the detection result of the mth detection module TestM indicates that the storage address of the mth speckle removing data is the last bit address of the mth speckle removing data, the mth switching control module CtlM outputs a control signal for turning on the mth bus and the M +1 th bus to the mth switching module SwitchM, where the control signal is specifically a control signal for turning on the mth bus interface SPIM1 and the M +1 th bus interface SPIM 2; the mth switching module SwitchM realizes the connection between the mth bus interface SPIM1 and the M +1 th bus interface SPIM2 according to the received control signal, thereby realizing the conduction between the mth bus and the M +1 th bus. At this time, the mth read module ReadM completes the read operation.
When the detection result of the mth detection module TestM is that the storage address of the mth speckle removing data is not the last bit address of the mth speckle removing data, the mth switching control module CtlM does not output a control signal to the mth switching module SwitchM. At this time, the Mth reading module ReadM continues to read the Mth speckle reduction data in the flash memory chip flash until the storage address of the Mth speckle reduction data is the last bit address of the Mth speckle reduction data.
The nth timing controller TconN which resides in the last order includes an nth read module ReadN, an nth detection module TestN, and an nth bus interface SPIN1, and the nth read module ReadN and the nth detection module TestN are located in the nth timing controller TconN. The Nth bus interface SPIN1 is connected with the Nth bus, the Nth reading module ReadN is connected with the Nth bus interface SPIN1 and used for reading Nth speckle eliminating data in the flash memory chip flash through the Nth bus, and the Nth detection module TestN is connected with the Nth reading module ReadN and used for detecting the Nth speckle eliminating data read by the Nth reading module ReadN and obtaining a detection result. Specifically, the detection is to detect the storage address of the nth speckle reduction data and judge whether the storage address is the last address of the nth speckle reduction data.
And when the detection result of the Nth detection module TestN is that the storage address of the Nth speckle reduction data is the last bit address of the Nth speckle reduction data, the Nth reading module ReadN finishes the reading operation. When the detection result of the nth detection module TestN is that the storage address of the nth speckle reduction data is not the last address of the nth speckle reduction data, the nth reading module ReadN continues to read the nth speckle reduction data in the flash memory chip flash until the storage address of the nth speckle reduction data is the last address of the nth speckle reduction data.
In another embodiment, referring to fig. 4, the mth bus interface SPIM1 is connected to the mth bus SPIM and the mth switching module SwitchM, and the mth reading module ReadM is connected to the mth switching module SwitchM, that is, the mth reading module ReadM realizes indirect connection with the mth bus SPIM through the switching control of the mth switching module SwitchM, so as to read the mth speckle eliminating data in the flash memory chip flash. The read operation of the mth read module ReadM is subject to the mth switching module SwitchM.
The Mth detection module TestM is connected with the Mth reading module ReadM and used for detecting the Mth speckle eliminating data read by the Mth reading module ReadM and obtaining a detection result. Specifically, the detection is to detect the storage address of the mth speckle reduction data and judge whether the storage address is the last address of the mth speckle reduction data.
The mth switching control module CtlM is connected to the mth detection module TestM, and is configured to output a control signal to the mth switching module SwitchM according to a detection result of the mth detection module TestM, so as to control the mth switching module SwitchM to perform switching connection.
The mth switching module SwitchM is connected to the mth switching control module CtlM, the mth bus interface SPIM1, the M +1 th bus interface SPIM2, and the mth reading module ReadM, and is configured to perform switching connection according to a control signal of the mth switching control module CtlM, where the switching connection mainly refers to connection between the mth switching module SwitchM and the mth reading module ReadM and between the mth switching module SwitchM and the mth +1 bus interface SPIM2, so as to respectively implement conduction between the mth bus and the mth reading module ReadM, and conduction between the mth bus and the mth +1 bus.
For example, when the detection result of the mth detection module TestM indicates that the storage address of the mth speckle elimination data is the last bit address of the mth speckle elimination data, the mth switching control module CtlM outputs a control signal for turning on the mth bus and the M +1 th bus to the mth switching module SwitchM, where the control signal is specifically a control signal for turning on the mth bus interface SPIM1 and the M +1 th bus interface SPIM 2; the mth switching module SwitchM realizes the connection between the mth bus interface SPIM1 and the M +1 th bus interface SPIM2 according to the received control signal, thereby realizing the conduction between the mth bus and the M +1 th bus. At this time, the mth reading module ReadM completes the reading operation, and the mth switching control module CtlM simultaneously outputs a control signal for disconnecting the mth bus and the mth reading module ReadM to the mth switching module SwitchM, where the control signal is specifically a control signal for disconnecting the mth bus interface SPIM1 and the mth switching module SwitchM; the mth switching module SwitchM disconnects the mth bus interface SPIM1 and the mth switching module SwitchM according to the received control signal, thereby realizing disconnection of the mth bus and the mth switching module SwitchM.
When the detection result of the mth detection module TestM is that the storage address of the mth speckle removing data is not the last bit address of the mth speckle removing data, the mth switching control module CtlM does not output a control signal to the mth switching module SwitchM. At this time, the Mth reading module ReadM continues to read the Mth speckle reduction data in the flash memory chip flash until the storage address of the Mth speckle reduction data is the last bit address of the Mth speckle reduction data.
The nth timing controller TconN which resides in the last position includes an nth reading module ReadN, an nth detecting module TestN, an nth switching module SwitchN, and an nth bus interface SPIN1, and the nth reading module ReadN, the nth detecting module TestN, and the nth switching module SwitchN are located in the nth timing controller TconN. The Nth bus interface SPIN1 is connected with an Nth bus, the Nth switching module SwitchN is connected with the Nth bus interface SPIN1, the Nth reading module ReadN is connected with the Nth switching module SwitchN, the Nth reading module ReadN realizes indirect connection with the Nth bus SPIN through switching control of the Nth switching module SwitchN, and therefore Nth despeckle data in the flash memory chip flash are read.
The Nth detection module TestN is connected with the Nth reading module ReadN and used for detecting the Nth speckle eliminating data read by the Nth reading module ReadN and obtaining a detection result. Specifically, the detection is to detect the storage address of the nth speckle reduction data and judge whether the storage address is the last address of the nth speckle reduction data.
The nth switching control module CtlN is connected with the nth detection module TestN and used for outputting a control signal to the nth switching module SwitchN according to a detection result of the nth detection module TestN so as to control the nth switching module SwitchN to perform switching connection.
The nth switching module SwitchN is connected to the nth switching control module CtlN, the nth bus interface SPIM1, and the mth reading module ReadM, and is configured to perform switching connection according to a control signal of the nth switching control module CtlN, where the switching connection mainly refers to connection between the nth switching module SwitchN and the nth reading module ReadM, so as to implement conduction between the nth bus and the nth reading module ReadN.
When the detection result of the nth detection module TestN indicates that the storage address of the nth speckle eliminating data is the last address of the nth speckle eliminating data, the nth reading module ReadN completes the reading operation, the nth switching control module CtlN outputs a control signal for disconnecting the nth bus and the nth reading module ReadN to the nth switching module SwitchN, and the nth switching module SwitchN disconnects the nth bus interface SPIN1 and the nth switching module SwitchN according to the received control signal, so that disconnection of the nth bus and the nth switching module SwitchN is realized.
And when the detection result of the Nth detection module TestN is that the storage address of the Nth speckle reduction data is not the last address of the Nth speckle reduction data, the Nth reading module ReadN continues to read the Nth speckle reduction data in the flash memory chip flash until the storage address of the Nth speckle reduction data is the last address of the Nth speckle reduction data.
In another embodiment, referring to fig. 5, fig. 5 is a block diagram illustrating a fourth structure of a speckle reduction system of a display device according to an embodiment of the present invention. As shown, the mth timing controller TconM includes an mth switching module SwitchM, an mth reading module ReadM, an mth detecting module TestM, and an mth switching control module CtlM, the mth switching module SwitchM, the mth reading module ReadM, and the mth detecting module TestM are located in the mth timing controller TconM, and the mth switching control module CtlM is located in the M +1 th timing controller TconM. Meanwhile, the mth timing controller TconM further includes an mth bus interface SPIM1 and an M +1 th bus interface SPIM2. Where M is an integer of 1 or more and N or less, that is, the mth timing controller TconM represents any one of the first to second last timing controllers, for example, the first timing controller Tcon1 shown in the figure.
In one embodiment, referring to fig. 5, the mth bus interface SPIM1 is connected to the mth bus SPIM and is also directly connected to the mth reading module ReadM, and the mth reading module ReadM is connected to the mth bus SPIM through the mth bus interface SPIM1 and is configured to read the mth speckle reduction data in the flash memory chip flash.
The Mth detection module TestM is connected with the Mth reading module ReadM and used for detecting the Mth speckle eliminating data read by the Mth reading module ReadM and obtaining a detection result. Specifically, the detection is to detect the storage address of the mth speckle reduction data and judge whether the storage address is the last address of the mth speckle reduction data.
The M +1 bus interface SPIM2 and the M +1 bus interface SPI (M + 1) 1 are connected through an M +1 bus, the M switching control module CtlM is connected with the M +1 bus interface SPI (M + 1) 1, the M switching module SwitchM is connected with the M +1 bus interface SPIM2, and the M switching control module CtlM is used for receiving a level transmission signal of the M timing controller TconM, outputting a control signal to the M switching module SwitchM according to the level transmission signal, and further controlling the M switching module SwitchM to carry out switching connection.
The mth switching module SwitchM is connected to the mth bus interface SPIM1 and the M +1 th bus interface SPIM2, and is configured to perform switching connection according to a control signal of the mth switching control module CtlM, where the switching connection mainly refers to connection between the mth switching module SwitchM and the mth bus interface SPIM1 and the M +1 th bus interface SPIM2, so as to implement conduction between the mth bus and the M +1 th bus.
For example, when the detection result of the mth detection module TestM is that the storage address of the mth speckle reduction data is the last bit address of the mth speckle reduction data, the mth timing controller TconM outputs a stage transfer signal to the mth switching control module CtlM; after receiving the level transmission signal, the Mth switching control module CtlM outputs a control signal for conducting the Mth bus and the M +1 th bus to the Mth switching module SwitchM; the mth switching module SwitchM realizes the connection between the mth bus interface SPIM1 and the M +1 th bus interface SPIM2 according to the received control signal, thereby realizing the conduction between the mth bus and the M +1 th bus. At this time, the mth read module ReadM completes the read operation.
When the detection result of the mth detection module TestM is that the storage address of the mth speckle eliminating data is not the last bit address of the mth speckle eliminating data, the mth timing controller TconM continuously transmits a signal to the mth switching control module CtlM, and the mth switching control module CtlM does not output a control signal to the mth switching module SwitchM. At this time, the Mth reading module ReadM continues to read the Mth speckle reduction data in the flash memory chip flash until the storage address of the Mth speckle reduction data is the last bit address of the Mth speckle reduction data.
The nth timing controller TconN located at the last position is similar to the nth timing controller TconN in the foregoing embodiments, and specific reference may be made to the foregoing embodiments, which are not described herein again.
The speckle eliminating data in the flash memory chip read by the reading module is compressed speckle eliminating data in a compressed state, and the compressed speckle eliminating data can be used for eliminating the speckles of the display device after being processed by some series of processes such as decompression and the like. Therefore, the timing controller provided in the embodiment of the present invention further includes a decoding module and an algorithm module (not shown). The compressed speckle reduction data includes speckle reduction data for performing speckle reduction processing on the display device, and an identifier for identifying a position of the speckle reduction data, that is, address information of the speckle reduction data according to the embodiment of the present invention. After the reading module acquires the compressed speckle eliminating data in the flash memory chip, the decoding module decodes the compressed speckle eliminating data based on the identifier to obtain decompressed actual speckle eliminating data; the algorithm module obtains a target driving voltage value of the display device based on the brightness data of the display device and the decompressed actual speckle reduction data, and the target driving voltage is adopted to drive the display device, so that speckle reduction processing of the display device can be realized, and the mura phenomenon of the display device is eliminated.
In one embodiment, the invention also provides a display device. Referring to fig. 6, fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in the drawing, the display device includes:
a display panel 610 including at least two sub-display regions (611, 612);
the control board 630 comprises N time schedule controllers (631 and 632) which are mutually cascaded, wherein N is an integer which is more than or equal to 2; the time sequence controllers (631 and 632) correspond to the sub display areas (611 and 612) one by one and are used for respectively carrying out speckle removing processing on the corresponding sub display areas (611 and 612);
the printed circuit board 620 comprises a flash memory chip 621, wherein the flash memory chip 621 is used for storing speckle eliminating data of the display device;
the flash memory chip 621 and the timing controller (631 and 632) are connected through N buses in sequence, and the flash memory chip 621 is connected with the first timing controller 631 through a first bus;
and in the L stage, the L-th time sequence controller is connected with the flash memory chip through the front (L-1) time sequence controllers and the front L buses, and reads the L-th speckle eliminating data in the flash memory chip, wherein L is an integer which is more than or equal to 1 and less than or equal to N.
The present embodiment provides a display device including: a display panel including at least two sub-display regions; the control panel comprises N cascaded time sequence controllers, wherein N is an integer greater than or equal to 2, and the time sequence controllers correspond to the sub-display areas one by one and are used for respectively carrying out speckle removing treatment on the corresponding sub-display areas; the printed circuit board comprises a flash memory chip, wherein the flash memory chip is used for storing the speckle eliminating data of the display device; the display device is directly connected with the flash memory chip through a time sequence controller at the first position in the cascaded time sequence controllers, and the time sequence controller at the rear position is connected with the flash memory chip through the time sequence controller at the front position in each stage, so that the time sequence controllers are connected with the flash memory chip in a sequential time manner, and the corresponding speckle eliminating data is obtained; compared with the prior art, the method avoids the independent connection of each time sequence controller and the flash memory chip, reduces the wiring between the time sequence controller and the flash memory chip, simplifies the circuit, reduces the manufacturing cost, releases the area of the control panel and is beneficial to the layout and wiring of the control panel.
In an embodiment, the invention further provides a speckle removing method for a display device, and the speckle removing method is used for performing speckle removing processing on the display device provided by the embodiment of the invention, the speckle removing system comprises a flash memory chip and N time sequence controllers which are mutually cascaded, wherein N is an integer greater than or equal to 2, the flash memory chip stores speckle removing data of the display device, the time sequence controllers of the flash memory chip are sequentially connected through N buses, and the flash memory chip is connected with the first time sequence controller through the first bus. Referring to fig. 7, fig. 7 is a first flowchart illustrating a speckle reduction method according to an embodiment of the present invention. As shown in the figure, the speckle removing method comprises the following steps:
step S701, in the Mth stage, the Mth time schedule controller is connected with the flash memory chip through the front (M-1) time schedule controllers and the front M buses, and Mth speckle eliminating data in the flash memory chip are read, wherein M is an integer which is more than or equal to 1 and less than N;
step S702, in the Nth stage, the Nth time sequence controller is connected with the flash memory chip through the front (N-1) time sequence controllers and the front N buses, and the Nth speckle eliminating data in the flash memory chip is read.
The embodiment provides a method for eliminating the speckles of a display device, and each step of the method is implemented by the speckle eliminating system provided by the embodiment of the invention, the time schedule controller at the first bit in a cascade time schedule controller is directly connected with a flash memory chip, and the time schedule controller at the rear bit is connected with the flash memory chip through the time schedule controller at the front bit in each stage, so that the time schedule controller is sequentially connected with the flash memory chip, and the corresponding speckle eliminating data is obtained; compared with the prior art, the method avoids independent connection of each time sequence controller and the flash memory chip, reduces wiring between the time sequence controller and the flash memory chip, simplifies circuits, reduces manufacturing cost, releases the area of the control panel, and is favorable for layout and wiring of the control panel.
In an embodiment, referring to fig. 8, fig. 8 is a schematic flow chart illustrating a second speckle reduction method according to an embodiment of the present invention. As shown in the figure, the speckle removing method comprises the following steps:
in the Mth stage, the Mth reading module reads Mth speckle removing data in the flash memory chip; m is an integer which is more than or equal to 1 and less than N, and M starts from 1;
the Mth detection module detects the storage address of the Mth speckle removing data and judges whether the storage address is the last address of the Mth speckle removing data;
if the detection result is that the storage address is not the last address of the first speckle reduction data, repeating the previous step;
if the detection result is that the storage address is the last bit address of the Mth speckle removing data, the Mth switching control module controls the Mth switching module to conduct the (M + 1) th bus and the Mth bus, so that the (M + 1) th reading module is connected with the flash memory chip through the front M time sequence controllers and the front (M + 1) bus, and the speckle removing method enters the (M + 1) th stage;
at the Nth stage, the Nth reading module reads the Nth speckle eliminating data in the flash memory chip;
the Nth detection module detects the storage address of the Nth speckle reduction data and judges whether the storage address is the last address of the Nth speckle reduction data;
if the detection result is that the storage address is not the last address of the Nth speckle reduction data, repeating the previous step;
and if the detection result is that the storage address is the last address of the Nth speckle reduction data, ending.
For a specific implementation manner of each step in the speckle reduction method provided by the embodiment of the present invention, reference may be made to a specific embodiment of the speckle reduction system of the display device provided by the present invention, and details are not described here.
According to the above embodiments:
the embodiment of the invention provides a display device, a spot eliminating system and a spot eliminating method thereof, wherein the spot eliminating system comprises: n time schedule controllers which are mutually cascaded, wherein N is an integer which is more than or equal to 2; the flash memory chip is used for storing the speckle eliminating data of the display device; the flash memory chip and the time sequence controller are connected sequentially through N buses, and the flash memory chip is connected with the first time sequence controller through a first bus; and in the L stage, the L-th time sequence controller is connected with the flash memory chip through the front (L-1) time sequence controllers and the front L buses to read the L-th speckle eliminating data in the flash memory chip, wherein L is an integer which is more than or equal to 1 and less than or equal to N. The speckle eliminating system provided by the embodiment of the invention directly connects the time schedule controller at the first position in the cascaded time schedule controllers with the flash memory chip, and the time schedule controller at the rear position realizes the connection with the flash memory chip through the time schedule controller at the front position in each stage, thereby realizing the sequential connection of the time schedule controller and the flash memory chip and acquiring the corresponding speckle eliminating data; compared with the prior art, the method avoids the independent connection of each time sequence controller and the flash memory chip, reduces the wiring between the time sequence controller and the flash memory chip, simplifies the circuit, reduces the manufacturing cost, releases the area of the control panel and is beneficial to the layout and wiring of the control panel.
In view of the foregoing, it is intended that the present invention cover the preferred embodiment of the invention and not be limited thereto, but that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (10)
1. A speckle reduction system for a display device, comprising:
n time schedule controllers which are mutually cascaded, wherein N is an integer which is more than or equal to 2;
the flash memory chip is used for storing the speckle eliminating data of the display device;
the flash memory chip and the time sequence controller are sequentially connected through N buses, and the flash memory chip is connected with the first time sequence controller through a first bus; the Mth time schedule controller comprises an Mth switching module, an Mth reading module, an Mth detection module and an Mth switching control module, wherein the Mth reading module is used for reading Mth speckle eliminating data in the flash memory chip, the Mth detection module is used for detecting the Mth speckle eliminating data, the Mth switching control module is used for controlling the Mth switching module to carry out switching connection according to the detection result of the Mth detection module, the Mth switching module is used for connecting or disconnecting an Mth bus and an M +1 bus, and M is an integer which is more than or equal to 1 and less than N;
and in the L stage, the L-th time sequence controller is connected with the flash memory chip through the front (L-1) time sequence controllers and the front L buses to read the L-th speckle eliminating data in the flash memory chip, wherein L is an integer which is more than or equal to 1 and less than or equal to N.
2. The speckle reduction system of claim 1, wherein the mth switching module, the mth reading module, and the mth detecting module are located within the mth timing controller.
3. The speckle reduction system of claim 2, wherein the mth switching control module is located within the mth timing controller; the Mth reading module is connected with the flash memory chip through the front (M-1) time sequence controllers and the front M buses, the Mth detection module is connected with the Mth reading module, and the Mth switching control module is connected with the Mth detection module and the Mth switching module.
4. The speckle removing system of claim 2, wherein the mth switching control module is located within the M +1 th timing controller; the Mth reading module is connected with the flash memory chip through the front (M-1) time sequence controllers and the front M buses, the Mth detection module is connected with the Mth reading module, and the Mth switching control module is connected with the Mth switching module.
5. A display device, comprising:
the display panel comprises at least two sub-display areas;
the control panel comprises N time sequence controllers which are mutually cascaded, wherein N is an integer which is more than or equal to 2; the time sequence controllers correspond to the sub-display areas one by one and are used for respectively carrying out speckle removing treatment on the corresponding sub-display areas;
the printed circuit board comprises a flash memory chip, and the flash memory chip is used for storing the speckle eliminating data of the display device;
the flash memory chip and the time sequence controller are connected through N buses in sequence, and the flash memory chip is connected with the first time sequence controller through a first bus; the Mth time schedule controller comprises an Mth switching module, an Mth reading module, an Mth detection module and an Mth switching control module, wherein the Mth reading module is used for reading Mth spot eliminating data in the flash memory chip, the Mth detection module is used for detecting the Mth spot eliminating data, the Mth switching control module is used for controlling the Mth switching module to carry out switching connection according to the detection result of the Mth detection module, the Mth switching module is used for connecting or disconnecting an Mth bus and an M +1 th bus, and M is an integer which is more than or equal to 1 and less than N;
and in the L stage, the L time sequence controller is connected with the flash memory chip through the front (L-1) time sequence controllers and the front L buses to read the L speckle eliminating data in the flash memory chip, wherein L is an integer which is more than or equal to 1 and less than or equal to N.
6. A speckle removing method of a display device is characterized in that the display device of claim 5 is subjected to speckle removing treatment by using the speckle removing system of any one of claims 1 to 4, the speckle removing system comprises a flash memory chip and N time sequence controllers which are mutually cascaded, wherein N is an integer which is more than or equal to 2, the flash memory chip stores speckle removing data of the display device, the flash memory chip and the time sequence controllers are sequentially connected through N buses, and the flash memory chip is connected with a first time sequence controller through a first bus; the Mth time schedule controller comprises an Mth switching module, an Mth reading module, an Mth detection module and an Mth switching control module, wherein the Mth reading module is used for reading Mth spot eliminating data in the flash memory chip, the Mth detection module is used for detecting the Mth spot eliminating data, the Mth switching control module is used for controlling the Mth switching module to carry out switching connection according to the detection result of the Mth detection module, the Mth switching module is used for connecting or disconnecting an Mth bus and an M +1 th bus, and M is an integer which is more than or equal to 1 and less than N;
the speckle removing method comprises the following steps:
in the Mth stage, the Mth time sequence controller is connected with the flash memory chip through the front (M-1) time sequence controllers and the front M buses to read the Mth speckle eliminating data in the flash memory chip, wherein M is an integer which is more than or equal to 1 and less than N;
and in the Nth stage, the Nth time sequence controller is connected with the flash memory chip through the front (N-1) time sequence controllers and the front N buses, and reads the Nth speckle eliminating data in the flash memory chip.
7. The speckle removing method of claim 6, wherein the step of reading the mth speckle removing data in the flash memory chip by connecting the mth timing controller to the flash memory chip through the first (M-1) timing controllers and the first M bus lines in the mth stage comprises:
the Mth reading module reads Mth speckle removing data in the flash memory chip;
the Mth detection module detects the Mth speckle eliminating data to obtain a detection result;
and the Mth switching control module controls the Mth switching module to perform switching connection according to the detection result.
8. The speckle removing method according to claim 7, wherein the step of detecting the mth speckle removing data by the mth detection module to obtain a detection result comprises:
the Mth detection module detects a storage address of the Mth speckle removing data and judges whether the storage address is the last address of the Mth speckle removing data.
9. The speckle removing method according to claim 8, wherein the step of controlling the mth switching module to switch connection according to the detection result by the mth switching control module comprises:
if the detection result is that the storage address is the last bit address of the Mth speckle removing data, the Mth switching control module controls the Mth switching module to conduct an (M + 1) th bus and an Mth bus, so that the (M + 1) th reading module is connected with the flash memory chip through the first M time schedule controllers and the first (M + 1) buses, and the speckle removing method enters an (M + 1) th stage;
if the detection result is that the storage address is not the last address of the Mth speckle reduction data, repeating the steps in the Mth stage.
10. The speckle removing method of claim 9, wherein the step of reading the nth speckle removing data in the flash memory chip by connecting the nth timing controller to the flash memory chip through the first (N-1) timing controllers and the first N bus lines in the nth stage comprises:
the Nth reading module reads the Nth speckle eliminating data in the flash memory chip;
the Nth detection module detects the storage address of the Nth speckle removing data and judges whether the storage address is the last address of the Nth speckle removing data;
if the detection result is that the storage address is the last address of the Nth speckle reduction data, ending; and if the detection result is that the storage address is not the last address of the Nth speckle reduction data, repeating the steps in the Nth stage.
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| CN108597470B (en) * | 2018-05-08 | 2021-01-01 | Tcl华星光电技术有限公司 | Display device driving system and method and display device |
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