CN110808235A - 一种沟槽型绝缘栅双极型晶体管封装结构及其制作方法 - Google Patents

一种沟槽型绝缘栅双极型晶体管封装结构及其制作方法 Download PDF

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CN110808235A
CN110808235A CN201810884478.3A CN201810884478A CN110808235A CN 110808235 A CN110808235 A CN 110808235A CN 201810884478 A CN201810884478 A CN 201810884478A CN 110808235 A CN110808235 A CN 110808235A
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trench
welding
groove
type
metal layer
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梁赛嫦
马颖江
史波
江伟
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Gree Electric Appliances Inc of Zhuhai
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Gree Electric Appliances Inc of Zhuhai
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Priority to CN201810884478.3A priority Critical patent/CN110808235A/zh
Priority to PCT/CN2019/099084 priority patent/WO2020029884A1/zh
Priority to US16/973,304 priority patent/US11688698B2/en
Publication of CN110808235A publication Critical patent/CN110808235A/zh
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Abstract

本发明涉及晶体管封装技术领域，公开了一种沟槽型绝缘栅双极型晶体管封装结构及其制作方法，该沟槽型绝缘栅双极型晶体管封装结构包括：沟槽型绝缘栅双极型晶体管，沟槽型绝缘栅双极型晶体管包括与发射极电连接的发射极金属层以及位于发射极金属层一侧的沟槽型栅极；引线框架，引线框架包括用于固定沟槽型绝缘栅双极型晶体管的芯片放置区以及发射极引出端；连接发射极金属层与发射极引脚的第一焊线，第一焊线一端与发射极金属层背离沟槽型栅极的表面连接形成条形的第一焊点，另一端与发射极引出端连接形成第二焊点，且第一焊点的延伸方向垂直于沟槽型栅极沟槽的延伸方向。该封装结构减小了单个沟槽的应力，提高了焊线良率，提高了芯片的可靠性。

Description

一种沟槽型绝缘栅双极型晶体管封装结构及其制作方法
技术领域
本发明涉及晶体管封装技术领域，特别涉及一种沟槽型绝缘栅双极型晶体管封装结构及其制作方法。
背景技术
绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，简称IGBT)，主要应用于变频空调的交流电机、变频器，开关电源，照明电路，牵引传动等领域。由于IGBT实际是一个电路开关，用在电压几百到几千伏量级，电流几十到几百安量级的强电上，故其可靠性级别会比普通消费类电子要求高很多。
IGBT工艺技术包括两种：平面型结构(planar)和沟槽型结构(trench)。其中沟槽型结构为新型技术，在不影响其它任何电气特性的基础上，提高了单元的单位密度，进而大大改良了传导损耗。因此，沟槽型IGBT比平面型IGBT更薄，更高电流密度及更低成本。
而沟槽型IGBT在可靠性能验证时容易出现漏电流急增而导致芯片烧毁，主要原因为芯片表面或内部某区域工艺上存在薄弱环节而导致。优化沟槽型IGBT可靠性能的方法有：一、通过芯片结构改善；二、通过封装阶段改善。而在IGBT器件的整体设计上，如果器件的芯片具体参数已确认，通过再流片来提高芯片的可靠性已基本不可能(因为流片周期长，成本高)。鉴于此，最快捷、最省成本及最有效的方式是通过芯片的封装方式来提高整个器件的可靠性能。
目前，国内并无成熟的针对薄型沟槽型IGBT的封装技术。对于焊线压焊工艺，只对焊线过程的功率大小、力度大小及时间三个参数协调来改善焊线可靠性，对焊线与芯片连接的第一焊点并不管控，会使第一焊点下方的沟槽数量特别少，导致焊接时少量沟槽承受较大的压应力而出现损伤。
发明内容
本发明提供了一种沟槽型绝缘栅双极型晶体管封装结构及其制作方法，上述一种沟槽型绝缘栅双极型晶体管封装结构中第一焊线压力均匀分布在较多的栅极沟槽上，减小了单个沟槽的应力，提高了焊线良率，进而提高了整个芯片的可靠性。
为达到上述目的，本发明提供以下技术方案：
一种沟槽型绝缘栅双极型晶体管封装结构，包括：
沟槽型绝缘栅双极型晶体管，所述沟槽型绝缘栅双极型晶体管包括与发射极电连接的发射极金属层以及位于所述发射极金属层一侧的沟槽型栅极；
引线框架，所述引线框架包括用于固定所述沟槽型绝缘栅双极型晶体管的芯片放置区以及发射极引出端；
连接所述发射极金属层与所述发射极引脚的第一焊线，所述第一焊线一端与所述发射极金属层背离所述沟槽型栅极的表面连接形成条形的第一焊点，另一端与所述发射极引出端连接形成第二焊点，且所述第一焊点的延伸方向垂直于所述沟槽型栅极沟槽的延伸方向。
上述沟槽型绝缘栅双极型晶体管封装结构，包括沟槽型绝缘栅双极型晶体管、引线框架以及电连接沟槽型绝缘栅双极型晶体管与引线框架的第一焊线，沟槽型绝缘栅双极型晶体管具有与发射极电连接的发射极金属层以及位于发射极金属层一侧的沟槽型栅极，引线框架具有用于固定沟槽型绝缘栅双极型晶体管的芯片放置区以及发射极引出端，沟槽型绝缘栅双极型晶体管固定于芯片放置区，通过第一焊线使发射极金属层与发射极引出端电连接，其中，第一焊线与发射极金属层连接的条形的第一焊点的延伸方向垂直于沟槽型栅极沟槽的延伸方向，由于条形的第一焊点延伸方向与沟槽型栅极上的沟槽延伸方向垂直，导致第一焊点能够压到更多的栅极沟槽，使更多的栅极沟槽分担第一焊点的压力，减少了单个沟槽的应力，避免焊接时的芯片损伤，提高了焊线良率，进而提高了整个芯片的可靠性。
优选地，所述第一焊线位于所述第一焊点和第二焊点之间的部分形成弧形部，所述弧形部的最高点距离所述发射极金属层的弧高为750微米至1000微米。
优选地，所述发射极引出端具有用于与所述第一焊线连接的第一著线垫，所述第二焊点形成于所述第一著线垫上。
优选地，所述发射极金属层与所述第一著线垫之间连接有至少一根所述第一焊线。
优选地，所述引线框架还包括栅极引出端，所述沟槽型栅极通过第二焊线与所述栅极引出端电连接。
优选地，所述沟槽型绝缘栅双极型晶体管包括硅衬底、形成于所述硅衬底上的所述沟槽型栅极、形成于所述沟槽型栅极表面的氧化硅绝缘层以及形成于所述氧化硅绝缘层背离所述硅衬底一侧的所述发射极金属层。
优选地，所述沟槽型绝缘栅双极型晶体管还包括位于所述硅衬底背离所述沟槽型栅极一侧的集电极，所述引线框架还包括集电极引出端，所述集电极通过结合材与所述引线框架的芯片放置区电连接和物理连接。
优选地，还包括由塑封工艺形成的内部完全填充的塑封外壳。
本发明还提供一种制作上述任意技术方案所提供的沟槽型绝缘栅双极型晶体管封装结构的方法，包括：
将沟槽型绝缘栅双极型晶体管固定于引线框架的芯片放置区；
采用超声波焊接劈刀压焊使第一焊线一端与所述沟槽型绝缘栅双极型晶体管的发射极金属层连接且形成延伸方向垂直于沟槽型栅极沟槽延伸方向的条形的第一焊点；
将超声波焊接劈刀垂直提起并且停留一定预设时间使所述第一焊线产生设定高度的弧高；
将超声波焊接劈刀跳到所述引线框架的发射极引出端处压焊，使所述第一焊线与所述发射极引出端连接且形成第二焊点。
上述沟槽型绝缘栅双极型晶体管封装结构的制作方法中，采用超声波焊接劈刀压焊形成垂直于沟槽型栅极沟槽延伸方向的条形的第一焊点，在第一焊点完成后将超声波焊接劈刀垂直提起形成设定高度的弧高后，将超声波劈刀调到引线框架的发射极引出端处压焊出第二焊点，完成对第一焊线的焊压，上述制作方法中由于将条形的第一焊点垂直于沟槽型栅极的沟槽设置，导致第一焊点能够压到更多的栅极沟槽，使更多的栅极沟槽分担第一焊点的压力，减少了单个沟槽的应力，避免焊接时的芯片损伤，提高了焊线良率，进而提高了整个芯片的可靠性。
优选地，所述预设时间为1毫秒至10毫秒。
优选地，所述第一焊线设定高度的弧高为750微米至1000微米。
优选地，完成沟槽型绝缘栅双极型晶体管芯片与引线框架上对应引脚的电连接后，采用塑封料灌充沟槽型绝缘栅双极型晶体管芯片与引线框架的结合器件以形成内部完全填充的塑封外壳。
附图说明
图1为本发明实施例提供的一种沟槽型绝缘栅双极型晶体管的结构示意图；
图2为本发明实施例提供的一种沟槽型栅极的结构示意图；
图3为本发明实施例提供的一种沟槽型绝缘栅双极型晶体管封装结构的结构示意图；
图4为图3中结构示意图的俯视图；
图5为本发明实施例提供的一种沟槽型绝缘栅双极型晶体管封装结构的制作方法流程图。
图标：
1-沟槽型绝缘栅双极型晶体管；11-硅衬底；12-沟槽型栅极；13-氧化硅绝缘层；14-发射极金属层；2-引线框架；21-芯片放置区；22-第一著线垫；23-第二著线垫；24-集电极引出端；3-第一焊线；31-第一焊点；32-第二焊点；33-弧形部；4-结合材。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参考图1至图3，本发明提供一种沟槽型绝缘栅双极型晶体管封装结构，包括：
沟槽型绝缘栅双极型晶体管1，沟槽型绝缘栅双极型晶体管1包括与发射极电连接的发射极金属层14以及位于发射极金属层14一侧的沟槽型栅极12；
引线框架2，引线框架2包括用于固定沟槽型绝缘栅双极型晶体管1的芯片放置区21以及发射极引出端；
连接发射极金属层14与发射极引脚的第一焊线3，第一焊线3一端与发射极金属层14背离沟槽型栅极12的表面连接形成条形的第一焊点31，另一端与发射极引出端连接形成第二焊点32，且第一焊点31的延伸方向垂直于沟槽型栅极12沟槽的延伸方向。
上述发明实施例提供的一种沟槽型绝缘栅双极型晶体管封装结构，包括沟槽型绝缘栅双极型晶体管1、引线框架2以及电连接沟槽型绝缘栅双极型晶体管1与引线框架2的第一焊线3，沟槽型绝缘栅双极型晶体管1具有与发射极电连接的发射极金属层14以及位于发射极金属层14一侧的沟槽型栅极12，引线框架2具有用于固定沟槽型绝缘栅双极型晶体管1的芯片放置区21以及发射极引出端，沟槽型绝缘栅双极型晶体管1固定于芯片放置区21，通过第一焊线3使发射极金属层14与发射极引出端电连接，其中，第一焊线3与发射极金属层14连接的条形的第一焊点31的延伸方向垂直于沟槽型栅极12沟槽的延伸方向，由于条形的第一焊点31延伸方向与沟槽型栅极12上的沟槽延伸方向垂直，导致第一焊点31能够压到更多的栅极沟槽，使更多的栅极沟槽分担第一焊点31的压力，减少了单个沟槽的应力，避免焊接时的芯片损伤，提高了焊线良率，进而提高了整个芯片的可靠性。
上述发明实施例中，具体地，如图3所示，第一焊线3位于第一焊点31和第二焊点32之间的部分形成弧形部33，弧形部33的最高点距离发射极金属层14的弧高为750微米至1000微米。此弧形部33的弧高高于常规焊线的弧高，使焊线压力均匀分布在较多的沟槽上，进一步平衡了各沟槽的受力，避免焊接时的芯片损伤，提高了焊线良率；并且因为第一焊线3的弧形部33被拉高，使第一焊线3与芯片的距离增大，有利于在塑封芯片时塑封料的完全填充，提高焊线焊接良率，并提高器件的整体可靠性。
上述发明实施例中，如图4所示，发射极引出端具有用于与第一焊线3连接的第一著线垫22，第二焊点32形成于第一著线垫22上，实现了发射极金属层14与发射极引出端的电连接。
上述发明实施例中，发射极金属层14与第一著线垫22之间连接有至少一根第一焊线3。例如，如果需要焊一根20mil的第一焊线3，为了达到同等电流等级，可以在同个著线垫上焊两根10mil第一焊线3，焊两根第一焊线3可以扩大第一焊点31与发射极金属层14的接触面积，进而减小焊接应力对芯片的影响。在实际应用中，第一焊线3和第一著线垫22的数量根据实际情况选择，在这里不做限制。例如，第一著线垫22可以为一个，也可以为多个，当第一著线垫22为多个时，多根第一焊线3对应与多个第一著线垫22连接。
上述发明实施例中，如图4所示，引线框架2还包括栅极引出端，沟槽型栅极12通过第二焊线与栅极引出端电连接。具体地，栅极引出端具有用于与第二焊线电连接的第二著线垫23。
上述发明实施例中，具体地，如图1所示，沟槽型绝缘栅双极型晶体管1包括硅衬底11、形成于硅衬底11上的沟槽型栅极12、形成于沟槽型栅极12表面的氧化硅绝缘层13以及形成于氧化硅绝缘层13背离硅衬底11一侧的发射极金属层14。
上述发明实施例中，沟槽型绝缘栅双极型晶体管1还包括位于硅衬底11背离沟槽型栅极12一侧的集电极，引线框架2还包括集电极引出端24，集电极通过结合材4与引线框架2的芯片放置区21电连接和物理连接。可选地，结合材4可以为导电胶，实现集电极与引线框架2的电连接。结合材4的材料还可以为其它能够实现集电极与引线框架2的芯片放置区21电连接和物理连接的材料，在这里不做限制。
需要说明的是，引线框架2上的著线垫的位置排布可能会根据实际生产而设计不同，不限于图4中所示的结构。
上述发明实施例中，还包括由塑封工艺形成的内部完全填充的塑封外壳，能够保证塑封器件内部不留空洞，提高焊线的焊接良率，提高器件整体的可靠性。
上述发明实施例中，第一焊线3为金属导电体，例如铝线或者铜线等，能够节约制作成本。
本发明还提供一种制作上述任意实施例所提供的沟槽型绝缘栅双极型晶体管封装结构的方法，如图5所示，包括以下步骤：
S501：将沟槽型绝缘栅双极型晶体管固定于引线框架的芯片放置区；
S502：采用超声波焊接劈刀压焊使第一焊线一端与沟槽型绝缘栅双极型晶体管的发射极金属层连接且形成延伸方向垂直于沟槽型栅极沟槽延伸方向的条形的第一焊点；
S503：将超声波焊接劈刀垂直提起并且停留一定预设时间使第一焊线产生设定高度的弧高；
S504：将超声波焊接劈刀跳到引线框架的发射极引出端处压焊，使第一焊线与发射极引出端连接且形成第二焊点。
上述发明实施例提供的沟槽型绝缘栅双极型晶体管封装结构的制作方法中，采用超声波焊接劈刀压焊形成垂直于沟槽型栅极沟槽延伸方向的条形的第一焊点，在第一焊点完成后将超声波焊接劈刀垂直提起形成设定高度的弧高后，将超声波劈刀调到引线框架的发射极引出端处压焊出第二焊点，完成对第一焊线的焊压，上述制作方法中由于将条形的第一焊点垂直于沟槽型栅极的沟槽设置，导致第一焊点能够压到更多的栅极沟槽，使更多的栅极沟槽分担第一焊点的压力，减少了单个沟槽的应力，避免焊接时的芯片损伤，提高了焊线良率，进而提高了整个芯片的可靠性。
上述超声波焊接的原理为：在竖直方向施加一定压力，在芯片平面方向施加一定的震动频率，使得芯片上方的金属层与焊线结合，形成第一焊点。
上述发明实施例中，根据工业生产的具体情况，为了提高时间的利用率，预设时间可以设置为1毫秒至10毫秒。
上述发明实施例中，第一焊线设定高度的弧高可以为750微米至1000微米。此范围的弧高高于常规焊线的弧高，使焊线压力均匀分布在较多的沟槽上，进一步平衡了各沟槽的受力，避免焊接时的芯片损伤，提高了焊线良率；并且因为第一焊线3的弧形部33被拉高，使第一焊线3与芯片的距离增大，有利于在塑封芯片时塑封料的完全填充，提高焊线焊接良率，并提高器件的整体可靠性。
上述发明实施例中，完成沟槽型绝缘栅双极型晶体管芯片与引线框架上对应引脚的电连接后，采用塑封料灌充沟槽型绝缘栅双极型晶体管芯片与引线框架的结合器件以形成内部完全填充的塑封外壳，保证塑封器件内部完全填充，不留空洞，提高焊线的焊接良率，并提高器件的整体可靠性。优选地，在塑封料灌充时沿模流方向灌充，即产品在塑封过程中，熔融的塑封料通过塑封模具的注胶口灌进产品。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (12)

1.一种沟槽型绝缘栅双极型晶体管封装结构，其特征在于，包括：
沟槽型绝缘栅双极型晶体管，所述沟槽型绝缘栅双极型晶体管包括与发射极电连接的发射极金属层以及位于所述发射极金属层一侧的沟槽型栅极；
引线框架，所述引线框架包括用于固定所述沟槽型绝缘栅双极型晶体管的芯片放置区以及发射极引出端；
连接所述发射极金属层与所述发射极引脚的第一焊线，所述第一焊线一端与所述发射极金属层背离所述沟槽型栅极的表面连接形成条形的第一焊点，另一端与所述发射极引出端连接形成第二焊点，且所述第一焊点的延伸方向垂直于所述沟槽型栅极沟槽的延伸方向。
2.根据权利要求1所述的沟槽型绝缘栅双极型晶体管封装结构，其特征在于，所述第一焊线位于所述第一焊点和第二焊点之间的部分形成弧形部，所述弧形部的最高点距离所述发射极金属层的弧高为750微米至1000微米。
3.根据权利要求1所述的沟槽型绝缘栅双极型晶体管封装结构，其特征在于，所述发射极引出端具有用于与所述第一焊线连接的第一著线垫，所述第二焊点形成于所述第一著线垫上。
4.根据权利要求3所述的沟槽型绝缘栅双极型晶体管封装结构，其特征在于，所述发射极金属层与所述第一著线垫之间连接有至少一根所述第一焊线。
5.根据权利要求1所述的沟槽型绝缘栅双极型晶体管封装结构，其特征在于，所述引线框架还包括栅极引出端，所述沟槽型栅极通过第二焊线与所述栅极引出端电连接。
6.根据权利要求1所述的沟槽型绝缘栅双极型晶体管封装结构，其特征在于，所述沟槽型绝缘栅双极型晶体管包括硅衬底、形成于所述硅衬底上的所述沟槽型栅极、形成于所述沟槽型栅极表面的氧化硅绝缘层以及形成于所述氧化硅绝缘层背离所述硅衬底一侧的所述发射极金属层。
7.根据权利要求6所述的沟槽型绝缘栅双极型晶体管封装结构，其特征在于，所述沟槽型绝缘栅双极型晶体管还包括位于所述硅衬底背离所述沟槽型栅极一侧的集电极，所述引线框架还包括集电极引出端，所述集电极通过结合材与所述引线框架的芯片放置区电连接和物理连接。
8.根据权利要求1所述的沟槽型绝缘栅双极型晶体管封装结构，其特征在于，还包括由塑封工艺形成的内部完全填充的塑封外壳。
9.一种制作如权利要求1-8任一项所述的沟槽型绝缘栅双极型晶体管封装结构的方法，其特征在于，包括：
将沟槽型绝缘栅双极型晶体管固定于引线框架的芯片放置区；
采用超声波焊接劈刀压焊使第一焊线一端与所述沟槽型绝缘栅双极型晶体管的发射极金属层连接且形成延伸方向垂直于沟槽型栅极沟槽延伸方向的条形的第一焊点；
将超声波焊接劈刀垂直提起并且停留一定预设时间使所述第一焊线产生设定高度的弧高；
将超声波焊接劈刀跳到所述引线框架的发射极引出端处压焊，使所述第一焊线与所述发射极引出端连接且形成第二焊点。
10.根据权利要求9所述的沟槽型绝缘栅双极型晶体管封装结构的制作方法，其特征在于，所述预设时间为1毫秒至10毫秒。
11.根据权利要求9所述的沟槽型绝缘栅双极型晶体管封装结构的制作方法，其特征在于，所述第一焊线设定高度的弧高为750微米至1000微米。
12.根据权利要求9所述的沟槽型绝缘栅双极型晶体管封装结构的制作方法，其特征在于，完成沟槽型绝缘栅双极型晶体管芯片与引线框架上对应引脚的电连接后，采用塑封料灌充沟槽型绝缘栅双极型晶体管芯片与引线框架的结合器件以形成内部完全填充的塑封外壳。
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