CN110798207A - Phase-locked loop bandwidth expanding circuit - Google Patents
Phase-locked loop bandwidth expanding circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention discloses a phase-locked loop bandwidth expanding circuit, which comprises a multiphase signal generating module, a phase discrimination module, a charge pump module, a low-pass filter, a voltage-controlled oscillator and a frequency division module, wherein the phase discrimination module comprises a plurality of phase discriminators, the charge pump module comprises a plurality of charge pumps, reference signals are input from the multiphase signal generating module, output multiphase signals enter the phase discrimination module, the phase discrimination module performs phase discrimination on multi-path reference signals output by the multiphase signal generating module and multi-phase clock signals output by the frequency division module, outputs multi-path signals to control the charge pump module, generates a path of control current signals, forms control voltage through the low-pass filter, adjusts the oscillation frequency of the voltage-controlled oscillator, the voltage-controlled oscillator outputs oscillation signals to the frequency division module, and the clock signals output by the frequency division module are sent to the phase discrimination module; the multi-path reference signals output by the multi-phase signal generating module correspond to the phases of the multi-phase clock signals output by the frequency dividing module one by one. The circuit expands the bandwidth of the phase-locked loop.
Description
Technical Field
The invention relates to the field of radio frequency integrated circuits, in particular to a phase-locked loop bandwidth expanding circuit.
Background
The phase-locked loop is a circuit for tracking the phase of an input signal, and along with the rapid development of the communication industry, the phase-locked loop has wide application in the coming fifth-generation mobile communication market, such as the industries of space communication, radar detection, biomedical treatment and the like. The frequency synthesizer with phase-locked loop as core provides stable and low-noise frequency signal for the frequency mixer, D/A converter and other circuits in the communication transceiver. Meanwhile, in systems requiring sweep frequency or continuous stepping such as radar detection, the fast tuning capability of the phase-locked loop module has a high requirement, and thus a phase-locked loop with high bandwidth needs to be designed. In this regard, a common approach is to use an auxiliary pll module to increase the input reference frequency of the pll, which increases the power consumption and complexity of the system.
For a traditional charge pump phase-locked loop structure (as shown in fig. 1), a phase frequency detector mainly adopting a D flip-flop structure compares an input reference signal with a feedback signal through a frequency divider, and then generates a control voltage through a charge pump and a loop filter to control a voltage-controlled oscillator, if a loop bandwidth is increased, the change of voltage and current is more severe in two consecutive samplings, when the bandwidth is close to 1/10 input reference frequency, the continuous time approximation of the phase detection module is no longer true, and a phase-locked loop system cannot work normally. In an actual circuit, because the phase frequency detector and the charge pump module do not work completely in an ideal working state, in order to ensure the stability of a loop and lower output spurious, the bandwidth is limited to 1/20 input reference frequency, so that the system structure needs to be optimized in order to remarkably improve the actual bandwidth of the charge pump phase-locked loop under the condition of constant reference frequency.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a phase-locked loop bandwidth expansion circuit which can fully utilize the multipath sampling characteristic and improve the updating frequency of the output information of a charge pump module. Therefore, in the practical design, under the condition that the bandwidth of the phase-locked loop exceeds 1/10 input reference frequency, the system still has better phase margin and can normally work in a stable state.
The purpose of the invention is realized by the following technical scheme:
a phase-locked loop bandwidth expanding circuit comprises a multi-phase signal generating module, a phase discrimination module, a charge pump module, a low-pass filter, a voltage-controlled oscillator and a frequency division module, wherein the phase discrimination module comprises a plurality of phase discriminators, the charge pump module comprises a plurality of charge pumps, reference signals are input from the multi-phase signal generating module, the output multi-phase signals enter the phase discrimination module, the phase discrimination module performs phase discrimination on multi-path reference signals output by the multi-phase signal generating module and multi-phase clock signals output by the frequency division module, the multi-path signals are output to control the charge pump module, one path of control current signals are generated, control voltage is formed through the low-pass filter, the oscillation frequency of the voltage-controlled oscillator is adjusted, the voltage-controlled oscillator outputs oscillation signals to the frequency division module, and the clock signals output by the frequency division;
the multi-path reference signals output by the multi-phase signal generating module correspond to the phases of the multi-phase clock signals output by the frequency dividing module one by one.
Further, the oscillation frequencies of the multi-path reference signals output by the multi-phase signal generation module are the same and equal to the frequency of the input reference signals.
Furthermore, the phase discrimination module is a sampling type phase discrimination module.
Further, the input of the charge pump includes an output signal of the phase discrimination module, a multiphase clock signal of the output of the frequency division module, and a reference voltage signal for differential comparison.
Furthermore, the frequency division effect, i.e. the ratio of the input signal frequency to the output frequency, is the frequency division ratio of the circuit design, and the specific frequency division number can be configured according to the circuit design requirement.
Furthermore, the duty ratio of the clock signal output by the frequency dividing module is adjustable.
Further, the voltage-controlled oscillator is a ring oscillator or an LC oscillator.
Furthermore, the charge pump module compares the multi-path voltage signals output by the sampling type phase identification module with the reference voltage signals and outputs a path of current signals; the reference voltage signal adopts one path of fixed level and multiple paths of floating levels.
The invention has the following beneficial effects:
the bandwidth of the phase-locked loop is affected by the phase margin, and the loop delay reduces the phase margin, thereby limiting the size of the bandwidth. The loop delay is reflected in the update speed of the loop information. The phase-locked loop bandwidth expanding circuit of the invention combines a plurality of paths of control signals into one path in one period, thus improving the updating frequency of the control signals, reducing the loop delay and expanding the bandwidth of the phase-locked loop; and the updating speed of the loop information is improved through the synthesis of the multi-path signals, so that the phase influence caused by the loop delay is reduced, and the bandwidth limitation of the phase-locked loop is improved.
Drawings
FIG. 1 is a diagram illustrating a charge pump phase-locked loop according to the prior art;
FIG. 2 is a schematic structural diagram of one embodiment of a phase-locked loop bandwidth extension circuit according to the present invention;
FIG. 3 is a schematic diagram of the four-phase signal generating module according to the present invention;
FIG. 4 is a schematic diagram of the signal transmission of the charge pump module in the pll bandwidth extension circuit according to the present invention;
fig. 5 is a schematic diagram illustrating the principle of signal transmission of the frequency division module in the pll bandwidth extension circuit according to the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments, and the objects and effects of the present invention will become more apparent, it being understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.
The phase-locked loop bandwidth expanding circuit comprises a multi-phase signal generating module, a phase discrimination module, a charge pump module, a low-pass filter, a voltage-controlled oscillator and a frequency division module, wherein the phase discrimination module comprises a plurality of phase discriminators, and the charge pump module comprises a plurality of charge pumps.
As one embodiment, as shown in fig. 2, the multi-phase signal generating module is a four-way adjacent quadrature signal generating circuit, and the phase detecting module is a sampling type phase detector.
A reference signal is input from a four-path signal generating circuit, a four-path signal is output to enter a phase discriminator, the phase discriminator performs phase discrimination on a four-path sampling signal output by the four-path signal generating circuit and a four-phase clock signal output by a frequency dividing module, the four-path signal is output to control a charge pump module, a path of control current signal is generated, a control voltage is formed by a low-pass filter, the oscillation frequency of a voltage-controlled oscillator is adjusted, the voltage-controlled oscillator outputs an oscillation signal to the frequency dividing module, and the clock signal output by the frequency dividing module is sent to the phase discriminating module;
as shown in fig. 3, the input of the four-way signal generating circuit is a reference signal in the form of a differential sine wave, and four-way signals with phases sequentially spaced by 90 degrees are generated by the circuit. The four-way signal generating circuit can be switched into two modes by a switch. These two modes differ in that when the circuit parameters are subject to PVT variations that deviate from the ideal set point, one mode is characterized by: the phase interval of the output four paths of signals is unchanged and is still 90 degrees, and the amplitude of the signals has deviation. Another mode is characterized in that: the phase intervals of the four output signals have certain deviation, and the amplitude of the output signals still keeps the same.
The four reference signals output by the four signal generating circuit correspond to the phases of the four-phase clock signals output by the frequency dividing module one by one. When the loop works, the multi-phase signal equivalently improves the information refresh rate of the system.
The four-way sampling type phase discriminator has four phase discrimination paths, and each path is controlled by two reverse sampling clocks to realize the sampling and holding of the sampled signals. The four paths of reference signals and the four paths of frequency division signals are respectively input, input signals of two different generation sources can be used as sampled signals or sampling clocks according to the structure requirement of the system, and the multi-path voltage signals are obtained through sampling output. The charge pump module converts the four-way phase detection information into one-way current information under the control of the clock signal, and when the four-way phase detection signal is controlled by the clock signal, the charge pump sequentially outputs the current correspondingly generated by each-way phase detection signal within one reference signal period, that is, each-way working time is 1/4 reference periods, as shown in fig. 4.
The voltage-controlled oscillator may be a ring voltage-controlled oscillator or an LC oscillator. One path of current information output by the charge pump module is subjected to integration and filtering by the low-pass filter to generate control voltage to control and adjust the oscillation frequency of the oscillator.
As one embodiment, the frequency dividing module divides the frequency of the oscillator output signal and outputs four paths of square wave signals with adjacent orthogonal duty ratios of 25% after frequency division, as shown in fig. 5.
Considering that adjacent orthogonal signals generated by a four-path signal generating circuit are affected by an actual circuit PVT, the phases of the generated signals are unequal in interval, so that the system has larger stray, a reference comparison signal of the four-path phase discrimination signal in a charge pump module adopts a mode of one-path fixed level and three-path floating level, and the floating level passes through a direct current low-frequency part obtained after the phase discrimination signal passes through a low-pass filter.
When the reference frequency is 50MHz, the update frequency of the maximum effective control loop of the conventional phase-locked loop circuit is 50MHz, and the loop delay is 20nS, and if the loop bandwidth is 1/10, i.e., 5MHz of the reference frequency, the phase lag caused by the loop delay is 36 °. By adopting the four-way phase-locked loop circuit, the maximum effective control loop updating frequency is 200MHz, the caused loop delay is 5nS, and the 5MHz bandwidth is also adopted, the loop delay only causes 9-degree phase lag, and if the 20MHz bandwidth is adopted, the loop delay also causes 36-degree phase lag, but the effective control bandwidth is 4 times of the original one.
The bandwidth expanding circuit of the phase-locked loop can realize that the bandwidth of the charge pump phase-locked loop exceeds the upper limit bandwidth of 1/10 of the input reference frequency.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and although the invention has been described in detail with reference to the foregoing examples, it will be apparent to those skilled in the art that various changes in the form and details of the embodiments may be made and equivalents may be substituted for elements thereof. All modifications, equivalents and the like which come within the spirit and principle of the invention are intended to be included within the scope of the invention.
Claims (8)
1. The utility model provides a phase-locked loop bandwidth extends circuit, it includes heterogeneous signal generation module, phase discrimination module, charge pump module, low pass filter, voltage controlled oscillator and frequency division module, the phase discrimination module include a plurality of phase discriminators, the charge pump module include a plurality of charge pumps, reference signal produces the module input from the multi-phase signal, output multi-phase signal gets into the phase discrimination module, the phase discrimination module carries out the phase discrimination with the multi-phase clock signal of the output of multi-phase signal generation module and frequency division module, output multi-channel signal control charge pump module produces control current signal all the way, forms control voltage through low pass filter, adjusts voltage controlled oscillator's oscillating frequency, voltage controlled oscillator output oscillating signal to the frequency division module, the clock signal of frequency division module output to the phase discrimination module.
The multi-path reference signals output by the multi-phase signal generating module correspond to the phases of the multi-phase clock signals output by the frequency dividing module one by one.
2. The phase-locked loop bandwidth expansion circuit according to claim 1, wherein the oscillation frequencies of the multiple reference signals outputted from the multi-phase signal generation module are the same and equal to the frequency of the inputted reference signal.
3. The phase-locked loop bandwidth expansion circuit according to claim 1, wherein the phase detection module is a sampling type phase detection module.
4. The phase-locked loop bandwidth expansion circuit according to claim 1, wherein the input of the charge pump comprises an output signal of the phase detection module, a multiphase clock signal of the output of the frequency division module, and a reference voltage signal for differential comparison.
5. The phase-locked loop bandwidth expansion circuit according to claim 1, wherein the frequency division effect, i.e. the ratio of the input signal frequency to the output frequency, is the frequency division ratio of the circuit design, and the specific frequency division number can be configured according to the circuit design requirement.
6. The phase-locked loop bandwidth expansion circuit according to claim 1, wherein a duty ratio of the clock signal output by the frequency divider module is adjustable.
7. The phase-locked loop bandwidth expansion circuit of claim 1, wherein the voltage-controlled oscillator is a ring oscillator or an LC oscillator.
8. The phase-locked loop bandwidth expansion circuit according to claim 3, wherein the charge pump module compares a plurality of voltage signals output by the sampling phase discriminator module with a reference voltage signal to output a current signal; the reference voltage signal adopts one path of fixed level and multiple paths of floating levels.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115220512A (en) * | 2022-08-10 | 2022-10-21 | 山东大学 | Automatic phase-locking constant current source circuit and method for driving tunable laser |
| CN116260405A (en) * | 2023-03-30 | 2023-06-13 | 北京安超微电子有限公司 | Method and system for realizing NFC read-write chip digital power amplifier |
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