CN107911114A - A kind of broadband phase-looked loop of constant loop bandwidth - Google Patents
A kind of broadband phase-looked loop of constant loop bandwidth Download PDFInfo
- Publication number
- CN107911114A CN107911114A CN201711126350.2A CN201711126350A CN107911114A CN 107911114 A CN107911114 A CN 107911114A CN 201711126350 A CN201711126350 A CN 201711126350A CN 107911114 A CN107911114 A CN 107911114A
- Authority
- CN
- China
- Prior art keywords
- loop
- controlled oscillator
- voltage controlled
- frequency
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005259 measurement Methods 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 6
- 230000006641 stabilisation Effects 0.000 abstract 1
- 238000011105 stabilization Methods 0.000 abstract 1
- 238000001514 detection method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a kind of broadband phase-looked loop of constant loop bandwidth, including charge pump phase lock loop (1) and digital auto-calibration circuits (2).Charge pump phase lock loop (1) includes phase frequency detector (3), programmable charge pump (4), loop filter (5), voltage controlled oscillator (6), feedback divider (7), first switch (8) and second switch (9).Digital auto-calibration circuits (2) include frequency detector (10), timing control unit (11), PLL loop bandwidth calibration circuit (12), pressuring controlling oscillator frequency calibration circuit (13) and voltage controlled oscillator control voltage generation circuit (14).By the present invention in that it can quickly measure the frequency of voltage controlled oscillator and the frequency calibration for voltage controlled oscillator and the calibration of PLL loop bandwidth with the mode that leggy detects, digital auto-calibration circuits can effectively ensure stabilization of the phaselocked loop in wide frequency ranges inner ring road bandwidth, and effectively overcome the influence of the factors such as technique, voltage, temperature.
Description
Technical field
The present invention relates to PHASE-LOCKED LOOP PLL TECHNIQUE field, and in particular to a kind of broadband phase-looked loop of constant loop bandwidth.
Background technology
PHASE-LOCKED LOOP PLL TECHNIQUE is widely used in integrated circuits as the clock source or transceiver system in digital circuit
In local oscillation signal.For different applications, such as microprocessor, data converter, chip interface, phase-locked loop circuit is proposed
Different requirements, such as working frequency.It is clearly time-consuming consumption wealth to design each phaselocked loop for different applied customizations, because
The phase-locked loop circuit in this design broadband is necessary.
The mode that when voltage controlled oscillator (VCO) designs coarse adjustment and fine tuning would generally be used to combine realizes broadband output,
As shown in Figure 1, relatively low VCO gain is obtained at the same time to reduce its susceptibility to noise.One traditional charge pump phase lock loop
As shown in Fig. 2, its open-loop gain can be expressed as：
Wherein ICPIt is the gain of charge pump, LF (s) is the impedance of loop filter, KVCOIt is the gain of VCO, N is phaselocked loop
Clock Multiplier Factor.The bandwidth and I of closed loopCP、KVCOIt is proportional with N, it is expressed as：
From formula (2) as can be seen that the Circuit Parameter's Influence in Design of PLL the size of loop bandwidth.For single
For frequency, the loop bandwidth that can want by adjusting these gain of parameter ensures the performance such as system stability and shake.
Then, the design comparison of wide reference frequency output phaselocked loop is difficult, is primarily due to the gain of VCO with working frequency, technique,
The Parameters variation such as voltage and temperature.The change of loop bandwidth directly affects the performance of phaselocked loop, such as locking time, phase noise
Deng.
The present invention proposes a kind of broadband phase-looked loop of constant loop bandwidth.Frequency detector measures the working frequency of VCO,
For pressuring controlling oscillator frequency calibration and PLL loop bandwidth calibration.Circuit and knot are calibrated by using pressuring controlling oscillator frequency
The voltage controlled oscillator of coarse adjustment and fine tuning mode is closed, phaselocked loop can shake while wide reference frequency output is obtained by voltage-controlled
The input tuning voltage for swinging device is limited to certain scope, reduces change in gain of the voltage controlled oscillator on single tuning curve.
The gain size of the tuning curve of PLL loop bandwidth calibration circuit On-wafer measurements voltage controlled oscillator work, and accordingly adjustment can
The output circuit size of programmed charges pump, ensures that PLL loop bandwidth is constant.
The content of the invention
In order to solve in wide output area charge pump phase lock loop, due to working frequency, technique, voltage and temperature (PVT)
Loop bandwidth caused by influence changes, and the present invention provides a kind of broadband phase-looked loop of constant loop bandwidth.It has calibration electricity
Route digital circuit, calibration speed is fast, calibration accuracy is high, anti-PVT influence the features such as.
The technical solution adopted by the present invention is：A kind of broadband phase-looked loop of constant loop bandwidth, including charge pump phase lock loop
With digital auto-calibration circuits；Charge pump phase lock loop is responsible for producing frequency output signal；Digital auto-calibration circuits are responsible for
The loop bandwidth of charge pump phase lock loop is calibrated, ensures that it can be worked normally in wide frequency ranges.Charge pump phase lock loop is by reflecting
Frequency phase discriminator, programmable charge pump, loop filter, voltage controlled oscillator, feedback divider, first switch and second switch.Its
In, first switch is responsible for realizing open loop and the closed loop states of cycle of phase-locked loop, and together decides on voltage controlled oscillator with second switch
Control the source of voltage；First switch and second switch working status are on the contrary, second switch disconnects when i.e. first switch closes, instead
It is as the same；Voltage controlled oscillator produces more tuning curve coverage goal frequency bands by the way of coarse adjustment and fine tuning are combined, and
With less gain.Digital auto-calibration circuits include frequency detector, timing control unit, PLL loop bandwidth school
Quasi- circuit, pressuring controlling oscillator frequency calibration circuit and voltage controlled oscillator control voltage generation circuit.Frequency detector passes through to pressure
The counting of the edge change of the multipath output signals and its reverse signal of oscillator is controlled, measures the frequency values N of voltage controlled oscillatorcnt。
Pressuring controlling oscillator frequency calibration circuit utilizes the output N of frequency detectorcntSelect the working band of voltage controlled oscillator.By making
Obtained with pressuring controlling oscillator frequency calibration circuit with the voltage controlled oscillator for combining coarse adjustment and fine tuning mode, charge pump phase lock loop
While wide reference frequency output, the input tuning voltage of voltage controlled oscillator can be limited to certain scope, reduced voltage-controlled
Change in gain of the oscillator on single tuning curve.After pressuring controlling oscillator frequency calibration circuit work is completed, phaselocked loop
Loop bandwidth calibration circuit utilizes the output N of frequency detectorcntThe gain of the tuning curve of On-wafer measurements voltage controlled oscillator work
Size, and the output circuit size of programmable charge pump is accordingly adjusted, ensure charge pump phase lock loop in wide operating frequency range
Loop bandwidth is constant.Timing control unit produces frequency detector, cycle of phase-locked loop calibration, voltage controlled oscillator calibration circuit, the
Sequential needed for one switch and second switch.Voltage controlled oscillator control voltage generation circuit is produced to be calibrated in pressuring controlling oscillator frequency
The required voltage VDD/2 and required voltage V in PLL loop bandwidth calibration circuit work in circuit workHAnd VL.Complete
In the digital auto-calibration circuit course of work, first switch disconnects, and second switch closure, charge pump phase lock loop is in open loop at this time
The control voltage that voltage controlled oscillator control voltage generation circuit produces is connected to the voltage of voltage controlled oscillator by state, second switch
Control terminal.After digital auto-calibration circuits complete calibration, first switch closure, second switch disconnects, at this time charge pump
Phaselocked loop is in closed loop states, and the control voltage that loop filter produces is connected to the voltage control of voltage controlled oscillator by first switch
End processed.
The principle of the present invention is：
Before phaselocked loop Closed loop operation, second switch connects the voltage that voltage controlled oscillator control voltage generation circuit produces
To the control voltage end of voltage controlled oscillator.The multipath output signals and its reverse signal of frequency detector detection voltage controlled oscillator
Edge changes, its work schedule is as shown in Figure 3.With frequency detecting time kTREFExemplified by, frequency detector detects total
Edge, which becomes, turns to Ncnt.In other words, the frequency detecting time is equal to NcntThe delay T of voltage controlled oscillator elementary cell againunit.Can
To be expressed as：
(Ncnt-1)·Tunit＜ kTREF≤Ncnt·Tunit (4)
Or
Ncnt·Tunit≤k·TREF＜ (Ncnt+1)·Tunit (5)
Wherein TREFIt is the cycle of reference clock.The sign of inequality in formula (4) (5) is by reference signal and VCO output signals
Therebetween caused by the irrelevance of start edge.The VCO frequency detected can be expressed as：
Or
Wherein fVCO=1/ (2MTunit)。
The frequency values that pressuring controlling oscillator frequency calibration circuit in digital calibration circuit is obtained using frequency detector are looked into
The alignment frequency sub-band nearest from target frequency is the working band of voltage controlled oscillator.Work having selected voltage controlled oscillator
Optimal sub-band after, voltage controlled oscillator control voltage generation circuit produces voltage VHAnd VL, respectively in both control voltages
Lower frequency detection circuit obtains the working frequency f of voltage controlled oscillatorHAnd fL.PLL loop bandwidth in digital calibration circuit
Calibrate the gain of circuit counting voltage controlled oscillator：
After accurate voltage controlled oscillator gain is obtained, PLL loop bandwidth calibration circuit readjusts programmable electricity
The gain of lotus pump, to compensate due to the change of loop bandwidth caused by voltage controlled oscillator change in gain and frequency dividing ratio change, that is, is adjusted
Whole ICPEnsure that formula (1), the value of (2) do not change.
The present invention compared with prior art the advantages of and good effect be：
1st, the present invention ensure that the loop bandwidth of phaselocked loop is kept not while broadband output area phaselocked loop is realized
Become；
2nd, the frequency detection circuit that the present invention uses can quickly measure the working frequency of voltage controlled oscillator, can be adapted for
Inductance capacitance type voltage controlled oscillator and ring oscillator；
3rd, digital auto-calibration circuits of the invention have the characteristics that calibration accuracy is high, error is small；
4th, phaselocked loop of the invention can provide high performance output signal, and on whole working frequency inner retaining ring road
Stablize.
Brief description of the drawings
The tuning curve schematic diagram for the voltage controlled oscillator that Fig. 1 is realized using the mode that coarse adjustment and fine tuning combine and its gain；
Fig. 2 is the schematic diagram of basic phase-locked loop frequency integrator；
Fig. 3 is frequency detector working timing figure proposed by the present invention；
Fig. 4 is the broadband phase-looked loop structure diagram of constant loop bandwidth proposed by the present invention.
Reference numeral implication is in figure：1 is charge pump phase lock loop, and 2 be digital auto-calibration circuits, and 3 be frequency and phase discrimination
Device, 4 be programmable charge pump, and 5 be loop filter, and 6 be voltage controlled oscillator, and 7 be feedback divider, and 8 be first switch, and 9 are
Second switch, 10 be frequency detector, and 11 be timing control unit, and 12 calibrate circuit for PLL loop bandwidth, and 13 be voltage-controlled
Oscillator frequency calibrates circuit, and 14 control voltage generation circuit for voltage controlled oscillator.
Embodiment
Detailed description of the present invention embodiment referring to the drawings.
As shown in figure 4, a kind of broadband phase-looked loop of constant loop bandwidth, including charge pump phase lock loop 1 and digital automatic
Circuit 2 is calibrated, charge pump phase lock loop 1 is responsible for producing frequency output signal；Digital auto-calibration circuits 2 are responsible for calibration charge pump
The loop bandwidth of phaselocked loop 1, ensures that it can be worked normally in wide frequency ranges.Charge pump phase lock loop 1 includes frequency and phase discrimination
Device 3, programmable charge pump 4, loop filter 5, voltage controlled oscillator 6, feedback divider 7, first switch 8 and second switch 9, it is real
Existing rate-adaptive pacemaker.Wherein, first switch 8 is responsible for realizing open loop and the closed loop states of cycle of phase-locked loop, and common with second switch 9
Determine that voltage controlled oscillator 6 controls the source of voltage；First switch 8 and 9 working status of second switch are on the contrary, i.e. first switch 8 is closed
Second switch 9 disconnects during conjunction, and vice versa；Voltage controlled oscillator produces more tunings by the way of coarse adjustment and fine tuning are combined
Curve coverage goal frequency band, and there is less gain.Digital auto-calibration circuits 2 include frequency detector 10, sequential
Control unit 11, PLL loop bandwidth calibration circuit 12, pressuring controlling oscillator frequency calibration circuit 13 and voltage controlled oscillator control
Voltage generation circuit 14.Frequency detector 10 is become by the edge of the multipath output signals to voltage controlled oscillator and its reverse signal
The counting of change, the frequency values N for the voltage controlled oscillator 6 that measurement output detectscnt.Pressuring controlling oscillator frequency calibration circuit 13 utilizes
The output N of frequency detector 10cntSelect the working band of voltage controlled oscillator 6.Circuit is calibrated by using pressuring controlling oscillator frequency
13 and the voltage controlled oscillator 6 of coarse adjustment and fine tuning mode is combined, charge pump phase lock loop 1 is obtaining the same of wide reference frequency output
When, the input tuning voltage of voltage controlled oscillator can be limited to certain scope, it is bent in single tuning to reduce voltage controlled oscillator
Change in gain on line.After the pressuring controlling oscillator frequency calibration work of circuit 13 is completed, PLL loop bandwidth calibration circuit
12 utilize the output N of frequency detector 10cntThe gain size of the tuning curve of On-wafer measurements voltage controlled oscillator work, and accordingly
The output circuit size of programmable charge pump is adjusted, ensures that charge pump phase lock loop 1 is permanent in wide operating frequency range inner ring road bandwidth
It is fixed.Timing control unit 11 produces frequency detector 10, cycle of phase-locked loop calibration 12, voltage controlled oscillator calibration circuit 13, first
Sequential needed for switch 8 and second switch 9.Voltage controlled oscillator control voltage generation circuit 14 is produced in pressuring controlling oscillator frequency school
The required voltage VDD/2 and required voltage V in PLL loop bandwidth calibration circuit 12 works during quasi- circuit 13 worksHWith
VL.In digital 2 course of work of auto-calibration circuits, first switch 8 disconnects, and second switch 9 closes, at this time charge pump lock phase
Ring 1 is in open loop situations, and the control voltage that voltage controlled oscillator control voltage generation circuit 14 produces is connected to pressure by second switch 9
Control the voltage controling end of oscillator 6.After digital auto-calibration circuits 2 complete calibration, first switch 8 closes, and second opens
Close 9 to disconnect, charge pump phase lock loop 1 is in closed loop states at this time, and the control voltage that first switch 8 produces loop filter 5 connects
It is connected to the voltage controling end of voltage controlled oscillator 6.
Fig. 4 is an example of specific implementation circuit proposed by the present invention, and charge pump phase lock loop is responsible for producing rate-adaptive pacemaker
Signal；Digital auto-calibration circuits are responsible for calibrating the loop bandwidth of charge pump phase lock loop, ensure it in wide frequency ranges all
Can normal work.
What the present invention was not disclosed in detail partly belongs to techniques known.
Although the illustrative embodiment of the present invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the invention is not restricted to the scope of embodiment, to the common skill of the art
For art personnel, if various change appended claim limit and definite the spirit and scope of the present invention in, these
Change is it will be apparent that all utilize the innovation and creation of present inventive concept in the row of protection.
Claims (1)
- A kind of 1. broadband phase-looked loop of constant loop bandwidth, it is characterised in that：Including charge pump phase lock loop (1) and digital automatic Calibrate circuit (2)；Charge pump phase lock loop (1) is used to produce frequency output signal；Digital auto-calibration circuits (2) are responsible for calibration The loop bandwidth of charge pump phase lock loop (1), ensures that it can be worked normally in wide reference frequency output；Charge pump phase lock loop (1) phase frequency detector (3), programmable charge pump (4), loop filter (5), voltage controlled oscillator (6), feedback divider are included (7), first switch (8) and second switch (9), wherein, first switch (8) is responsible for realizing the open loop of cycle of phase-locked loop and loop-like State, and with second switch (9) together decide on voltage controlled oscillator (6) control voltage source；First switch (8) and second switch (9) working status is on the contrary, second switch (9) disconnects when i.e. first switch (8) closes, and vice versa；Voltage controlled oscillator is using thick The mode that reconciliation fine tuning is combined, produces more tuning curve coverage goal frequency bands, and have less gain；It is digital from Dynamic calibration circuit (2) include frequency detector (10), timing control unit (11), PLL loop bandwidth calibration circuit (12), Pressuring controlling oscillator frequency calibration circuit (13) and voltage controlled oscillator control voltage generation circuit (14), frequency detector (10) pass through The counting of the edge change of multipath output signals and its reverse signal to voltage controlled oscillator, the frequency of measurement voltage controlled oscillator (6) Rate value Ncnt, pressuring controlling oscillator frequency calibration circuit (13) utilize frequency detector (10) output NcntSelect voltage controlled oscillator (6) working band, by using pressuring controlling oscillator frequency calibration circuit (13) and combines the voltage-controlled of coarse adjustment and fine tuning mode Oscillator (6), charge pump phase lock loop (1), can be by the input tune of voltage controlled oscillator while wide reference frequency output is obtained Humorous limiting voltage is in certain scope, change in gain of the reduction voltage controlled oscillator on single tuning curve, in voltage controlled oscillator After frequency calibration circuit (12) work is completed, PLL loop bandwidth calibration circuit (12) is defeated using frequency detector (10) Go out NcntThe gain size of the tuning curve of On-wafer measurements voltage controlled oscillator work, and accordingly adjust the output of programmable charge pump Circuit size, ensures that charge pump phase lock loop (1) is constant in wide operating frequency range inner ring road bandwidth, timing control unit (11) production Raw frequency detector (10), cycle of phase-locked loop calibration (12), voltage controlled oscillator calibration circuit (13), first switch (8) and second The sequential needed for (9) is switched, voltage controlled oscillator control voltage generation circuit (14) is produced calibrates circuit in pressuring controlling oscillator frequency (12) the required voltage VDD/2 and required voltage V in PLL loop bandwidth calibration circuit (12) work in workingHAnd VL, In digital auto-calibration circuits (2) course of work, first switch (8) disconnects, second switch (9) closure, at this time charge pump Phaselocked loop (1) is in open loop situations, the control electricity that second switch (9) produces voltage controlled oscillator control voltage generation circuit (14) Pressure is connected to the voltage controling end of voltage controlled oscillator (6), and after digital auto-calibration circuits (2) complete calibration, first opens (8) closure is closed, second switch (9) disconnects, and charge pump phase lock loop (1) is in closed loop states at this time, and first switch (8) filters loop The control voltage that ripple device (5) produces is connected to the voltage controling end of voltage controlled oscillator (6).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711126350.2A CN107911114B (en) | 2017-11-15 | 2017-11-15 | Broadband phase-locked loop with constant loop bandwidth |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711126350.2A CN107911114B (en) | 2017-11-15 | 2017-11-15 | Broadband phase-locked loop with constant loop bandwidth |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107911114A true CN107911114A (en) | 2018-04-13 |
| CN107911114B CN107911114B (en) | 2021-03-09 |
Family
ID=61845509
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711126350.2A Active CN107911114B (en) | 2017-11-15 | 2017-11-15 | Broadband phase-locked loop with constant loop bandwidth |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107911114B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110798207A (en) * | 2019-09-29 | 2020-02-14 | 浙江大学 | Phase-locked loop bandwidth expanding circuit |
| CN113225071A (en) * | 2021-07-07 | 2021-08-06 | 成都爱旗科技有限公司 | Phase calibration method, phase-locked loop circuit and electronic equipment |
| CN113644912A (en) * | 2021-07-27 | 2021-11-12 | 矽力杰半导体技术(杭州)有限公司 | Phase-locked loop circuit and control method thereof |
| CN114401001A (en) * | 2021-12-30 | 2022-04-26 | 北京力通通信有限公司 | Phase-locked loop rapid phase locking method |
| CN114531152A (en) * | 2022-01-04 | 2022-05-24 | 珠海横琴精韵科技有限公司 | Phase-locked loop |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5694068A (en) * | 1995-04-28 | 1997-12-02 | Nec Corporation | Digital phase-locked loop (PLL) having multilevel phase comparators |
| US20020079938A1 (en) * | 2000-12-21 | 2002-06-27 | Nec Corporation | Clock and data recovery circuit and clock control method |
| CN1571280A (en) * | 2003-07-14 | 2005-01-26 | 扬智科技股份有限公司 | Method for generating high frequency signal using multi-phase low frequency signal and related device |
| CN1812268A (en) * | 2005-01-28 | 2006-08-02 | 瑞昱半导体股份有限公司 | Clock generating circuit and related data restoring circuit |
| US20100073051A1 (en) * | 2008-09-22 | 2010-03-25 | Prism Circuits, Inc | Low jitter large frequency tuning lc pll for multi-speed clocking applications |
| CN101686055A (en) * | 2008-09-25 | 2010-03-31 | 凌阳科技股份有限公司 | Frequency synthetic system with self-corrective loop stability and band width |
| CN102970031A (en) * | 2012-11-05 | 2013-03-13 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and method for keeping bandwidth of frequency synthesizer loop to be stable |
| CN103746692A (en) * | 2013-12-24 | 2014-04-23 | 北京时代民芯科技有限公司 | PLL frequency synthesizer based on all-digital dynamic acceleration locking technology |
| CN105610432A (en) * | 2014-11-17 | 2016-05-25 | 英特尔德国有限责任公司 | Low power bipolar 360 degrees time to digital converter |
-
2017
- 2017-11-15 CN CN201711126350.2A patent/CN107911114B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5694068A (en) * | 1995-04-28 | 1997-12-02 | Nec Corporation | Digital phase-locked loop (PLL) having multilevel phase comparators |
| US20020079938A1 (en) * | 2000-12-21 | 2002-06-27 | Nec Corporation | Clock and data recovery circuit and clock control method |
| CN1571280A (en) * | 2003-07-14 | 2005-01-26 | 扬智科技股份有限公司 | Method for generating high frequency signal using multi-phase low frequency signal and related device |
| CN1812268A (en) * | 2005-01-28 | 2006-08-02 | 瑞昱半导体股份有限公司 | Clock generating circuit and related data restoring circuit |
| US20100073051A1 (en) * | 2008-09-22 | 2010-03-25 | Prism Circuits, Inc | Low jitter large frequency tuning lc pll for multi-speed clocking applications |
| CN101686055A (en) * | 2008-09-25 | 2010-03-31 | 凌阳科技股份有限公司 | Frequency synthetic system with self-corrective loop stability and band width |
| CN102970031A (en) * | 2012-11-05 | 2013-03-13 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and method for keeping bandwidth of frequency synthesizer loop to be stable |
| CN103746692A (en) * | 2013-12-24 | 2014-04-23 | 北京时代民芯科技有限公司 | PLL frequency synthesizer based on all-digital dynamic acceleration locking technology |
| CN105610432A (en) * | 2014-11-17 | 2016-05-25 | 英特尔德国有限责任公司 | Low power bipolar 360 degrees time to digital converter |
Non-Patent Citations (1)
| Title |
|---|
| JAEWOOK SHIN等: "A 1.9-3.8GHZ Δ∑ Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency", 《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110798207A (en) * | 2019-09-29 | 2020-02-14 | 浙江大学 | Phase-locked loop bandwidth expanding circuit |
| CN113225071A (en) * | 2021-07-07 | 2021-08-06 | 成都爱旗科技有限公司 | Phase calibration method, phase-locked loop circuit and electronic equipment |
| CN113644912A (en) * | 2021-07-27 | 2021-11-12 | 矽力杰半导体技术(杭州)有限公司 | Phase-locked loop circuit and control method thereof |
| CN113644912B (en) * | 2021-07-27 | 2024-04-16 | 矽力杰半导体技术(杭州)有限公司 | Phase-locked loop circuit and control method thereof |
| CN114401001A (en) * | 2021-12-30 | 2022-04-26 | 北京力通通信有限公司 | Phase-locked loop rapid phase locking method |
| CN114531152A (en) * | 2022-01-04 | 2022-05-24 | 珠海横琴精韵科技有限公司 | Phase-locked loop |
| CN114531152B (en) * | 2022-01-04 | 2023-11-07 | 珠海横琴精韵科技有限公司 | phase locked loop |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107911114B (en) | 2021-03-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107911114A (en) | A kind of broadband phase-looked loop of constant loop bandwidth | |
| US10141941B2 (en) | Differential PLL with charge pump chopping | |
| US9490827B2 (en) | Apparatus and methods for tuning a voltage controlled oscillator | |
| US8515374B2 (en) | PLL circuit, and radio communication apparatus equipped with same | |
| JP4636106B2 (en) | PLL circuit and its IC | |
| WO2015184963A1 (en) | Phase-locked loop frequency correction method and system | |
| US8432204B1 (en) | Current-controlled oscillator (CCO) based PLL | |
| US8698567B2 (en) | Phase-locked loop calibration system and method | |
| US10985762B2 (en) | Compensating for frequency variation of a crystal oscillator and related systems, methods and devices | |
| US9344094B2 (en) | Temperature compensated PLL calibration | |
| US7501900B2 (en) | Phase-locked loop bandwidth calibration | |
| US7148758B1 (en) | Integrated circuit with digitally controlled phase-locked loop | |
| US20090309664A1 (en) | Phase Alignment Circuit for a TDC in a DPLL | |
| US20080297240A1 (en) | Filter Circuit and Semiconductor Device | |
| CN114499512A (en) | Double-loop phase-locked loop | |
| US7439812B1 (en) | Auto-ranging phase-locked loop | |
| CN107846222A (en) | A kind of digital analog converter gain self-calibration circuit | |
| CN105790757B (en) | Automatic frequency correction circuit and frequency calibrating method | |
| CN104467817B (en) | One kind finely tuning algorithm applied to the loop of automatic frequency control system (AFC) | |
| CN109586714B (en) | Calibrating a voltage controlled oscillator to trim its gain using a phase locked loop and a frequency locked loop | |
| US6771102B2 (en) | Common mode feedback technique for a low voltage charge pump | |
| US8269533B2 (en) | Digital phase-locked loop | |
| CN211063586U (en) | Transconductance capacitance filter and circuit | |
| KR102376497B1 (en) | Frequency Synthesizer With Auto Frequency Calibrator Robust To Initial Phase Error | |
| CN107682007B (en) | Fast locking low-jitter clock data recovery circuit based on double loops |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP02 | Change in the address of a patent holder |
Address after: No.443 Huangshan Road, Shushan District, Hefei City, Anhui Province 230022 Patentee after: University of Science and Technology of China Address before: 230026 Jinzhai Road, Baohe District, Hefei, Anhui Province, No. 96 Patentee before: University of Science and Technology of China |
|
| CP02 | Change in the address of a patent holder |