CN113225071A - Phase calibration method, phase-locked loop circuit and electronic equipment - Google Patents
Phase calibration method, phase-locked loop circuit and electronic equipment Download PDFInfo
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
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- H—ELECTRICITY
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- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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Abstract
The invention discloses a phase calibration method, a phase-locked loop circuit and electronic equipment, and relates to the field of frequency calibration. The phase calibration method comprises the following steps: processing the input signals to obtain at least four intermediate input signals; determining a first output signal based on one of said intermediate input signals; controlling the phase-locked loop circuit to be in a normal working state based on the first output signal; determining an actual output signal based on at least four of the intermediate input signals under a condition that the phase-locked loop circuit is in a normal operating state; and calibrating and updating at least four intermediate input signals based on the first output signal and the actual output signal until the phase difference between every two of the at least four intermediate input signals is respectively matched with the corresponding preset phase difference, and outputting at least four target intermediate input signals. The calibration updating of the input signal is realized, the calibration precision is improved, and the effectiveness of reducing the noise of the phase-locked loop DSM is ensured.
Description
Technical Field
The present invention relates to the field of frequency calibration, and in particular, to a phase calibration method, a phase-locked loop circuit, and an electronic device.
Background
In modern wireless communication systems, frequency synthesizers are required to provide high resolution, low phase noise, fast settling local oscillator signals to transceivers.
Usually, the frequency synthesizer is implemented based on a Phase-Locked Loop architecture, which is referred to as a Phase-Locked Loop (PLL) for short. An inductance-capacitance voltage controlled oscillator (LC VCO) or a ring oscillator is generally used in the PLL, but at present, a differential integrator modulator (Delta-Sigma, DSM) noise is generated in a fractional phase-locked loop, so that the quality of an output signal of the PLL is reduced, and further, the stability and reliability of the PLL are reduced.
Disclosure of Invention
The invention aims to provide a phase calibration method, a phase-locked loop circuit and electronic equipment, which are used for solving the problems that the noise of a differential integral modulator can be generated in a decimal phase-locked loop, and the quality of an output signal of a phase-locked loop synthesizer is reduced.
In a first aspect, the present invention provides a phase calibration method applied to a phase-locked loop circuit, the method including:
processing the input signals to obtain at least four intermediate input signals;
determining a first output signal based on one of said intermediate input signals;
controlling the phase-locked loop circuit to be in a normal working state based on the first output signal;
determining an actual output signal based on at least four of the intermediate input signals under a condition that the phase-locked loop circuit is in a normal operating state;
and calibrating and updating at least four intermediate input signals based on the first output signal and the actual output signal until the phase difference between every two of the at least four intermediate input signals is respectively matched with the corresponding preset phase difference, and outputting at least four target intermediate input signals.
Under the condition of adopting the technical scheme, the phase calibration method provided by the invention obtains at least four intermediate input signals by processing the input signals; determining a first output signal based on one of the intermediate input signals; controlling the phase-locked loop circuit to be in a normal working state based on the first output signal; determining an actual output signal based on at least four of the intermediate input signals under a condition that the phase-locked loop circuit is in a normal operating state; the calibration updating is carried out on at least four intermediate input signals based on the first output signal and the actual output signal until the phase difference between every two intermediate input signals in sequence of the at least four intermediate input signals is respectively matched with the corresponding preset phase difference, at least four target intermediate input signals are output, the calibration updating of the input signals is realized, the calibration precision is improved, the effectiveness of reducing the noise of the phase-locked loop DSM is guaranteed, and further, the stability and the reliability of the phase-locked loop circuit can be improved.
In a possible implementation manner, after the phase differences between every two of the up to at least four intermediate input signals respectively match with the corresponding preset phase differences, the method further includes:
a second output signal is determined based on at least four of the target intermediate input signals.
In a possible implementation manner, the signal processing the input signals to obtain at least four intermediate input signals includes:
and respectively carrying out clock acquisition, frequency and phase discrimination, voltage conversion, filtering, voltage control oscillation, difference and multi-phase filtering on the input signals to obtain at least four intermediate input signals.
In one possible implementation, the at least four intermediate input signals comprise two sets of intermediate input signals, each set of intermediate input signals comprising two of the intermediate input signals in opposite phases.
In a second aspect, the present invention further provides a phase-locked loop circuit, including: the phase-locked loop circuit includes: the calibration module is electrically connected with the signal processing module;
the signal processing module is used for processing the input signals to obtain at least four intermediate input signals;
the calibration module is used for determining a first output signal based on one intermediate input signal; controlling the phase-locked loop circuit to be in a normal working state based on the first output signal; determining an actual output signal based on at least four of the intermediate input signals under a condition that the phase-locked loop circuit is in a normal operating state; and calibrating and updating at least four intermediate input signals based on the first output signal and the actual output signal until the phase difference between every two of the at least four intermediate input signals is respectively matched with the corresponding preset phase difference, and outputting at least four target intermediate input signals.
In a possible implementation manner, the signal processing module includes a crystal oscillator, a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a polyphase filter, which are electrically connected in sequence.
In a possible implementation manner, the calibration module includes a counter, a calibration unit, a trigger unit, a gating unit, a phase discrimination unit, and a digital time conversion unit;
the trigger unit comprises a first trigger and a second trigger;
the gating unit includes a first gate, a second gate, and a third gate;
the phase detection unit comprises a first phase detector and a second phase detector;
the digital-to-time conversion unit comprises a first digital-to-time converter, a second digital-to-time converter, a third digital-to-time converter, a fourth digital-to-time converter, a fifth digital-to-time converter and a sixth digital-to-time converter;
the input end of the counter, the input end of the second digital-to-time converter, the input end of the third digital-to-time converter, the input end of the fourth digital-to-time converter and the input end of the first gate are respectively and electrically connected with the output end of the polyphase filter;
the output end of the counter is electrically connected with the input end of the first trigger and the input end of the second trigger respectively;
the output end of the first trigger is electrically connected with the input end of the second gate and the input end of the first digital-to-time converter respectively;
the output end of the second trigger is electrically connected with the input end of the second gate and the input end of the fifth digital time converter respectively;
the output end of the second gate is electrically connected with the input end of the phase frequency detector and the input end of the sixth digital time converter respectively;
the output end of the first gate is electrically connected with the input end of the third gate;
the output end of the third gating device is electrically connected with the input end of the second trigger;
the output end of the sixth digital-to-time converter and the output end of the crystal oscillator are respectively and electrically connected with the input end of the second phase discriminator;
the output end of the second phase discriminator is electrically connected with the input end of the calibration unit;
the output end of the calibration unit is electrically connected with the input end of the sixth digital-to-time converter, the output end of the first phase detector, the input end of the first digital-to-time converter, the input end of the fifth digital-to-time converter, the input end of the third gate, the input end of the first gate, the input end of the second digital-to-time converter, the input end of the third digital-to-time converter, the input end of the fourth digital-to-time converter and the input end of the counter respectively.
In a possible implementation manner, the calibration unit includes a calibrator, a differential-integral modulator, and a phase-locked loop, which are connected in sequence.
The beneficial effect of the phase-locked loop circuit provided by the second aspect is the same as the beneficial effect of the phase calibration method described in the first aspect or any possible implementation manner of the first aspect, and details are not repeated here.
In a third aspect, the present invention also provides an electronic device, including: one or more processors; and one or more machine readable media having instructions stored thereon that, when executed by the one or more processors, cause the apparatus to perform the phase calibration method described in any of the possible implementations of the first aspect.
The beneficial effect of the electronic device provided by the third aspect is the same as that of the phase calibration method described in the second aspect or any possible implementation manner of the second aspect, and details are not repeated here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 illustrates a phase-locked loop circuit according to an embodiment of the present application;
fig. 2 illustrates another phase-locked loop circuit provided by an embodiment of the present application;
fig. 3 is a schematic flowchart illustrating a phase calibration method according to an embodiment of the present application;
fig. 4 is a schematic flowchart illustrating another phase calibration method provided in an embodiment of the present application;
fig. 5 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a chip according to an embodiment of the present invention.
Reference numerals:
10-a signal processing module; 20-a calibration module; 101-a crystal oscillator; 102-phase frequency detector; 103-a charge pump; 104-a loop filter; 105-a voltage controlled oscillator; 106-a polyphase filter; 201-a counter; 202-a calibration unit; 203 a-first flip-flop; 203 b-a second flip-flop; 204 a-a first gate; 204 b-a second gate; 204 c-third gate; 205 a-a first phase detector; 205 b-a second phase detector; 206 a-a first digital-to-time converter; 206 b-a second digital-to-time converter; 206 c-a third digital-to-time converter; 206 d-a fourth digital-to-time converter; 206 e-a fifth digital-to-time converter; 206 f-sixth digital to time converter.
Detailed Description
In order to facilitate clear description of technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish the same items or similar items having substantially the same functions and actions. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the sequence order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.
It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.
In the present invention, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b combination, a and c combination, b and c combination, or a, b and c combination, wherein a, b and c can be single or multiple.
Fig. 1 illustrates a phase-locked loop circuit provided by an embodiment of the present application, and as shown in fig. 1, the phase-locked loop circuit includes a signal processing module 10, and a calibration module 20 electrically connected to the signal processing module 10;
the signal processing module 10 is configured to perform signal processing on an input signal to obtain at least four intermediate input signals;
said calibration module 20 for determining a first output signal based on one of said intermediate input signals; controlling the phase-locked loop circuit to be in a normal working state based on the first output signal; determining an actual output signal based on at least four of the intermediate input signals under a condition that the phase-locked loop circuit is in a normal operating state; and calibrating and updating at least four intermediate input signals based on the first output signal and the actual output signal until the phase difference between every two of the at least four intermediate input signals is respectively matched with the corresponding preset phase difference, and outputting at least four target intermediate input signals.
According to the phase-locked loop circuit provided by the embodiment of the application, the signal processing module is used for processing the input signals to obtain at least four intermediate input signals; determining, by the calibration module, a first output signal based on one of the intermediate input signals; controlling the phase-locked loop circuit to be in a normal working state based on the first output signal; determining an actual output signal based on at least four of the intermediate input signals under a condition that the phase-locked loop circuit is in a normal operating state; the calibration updating is carried out on at least four intermediate input signals based on the first output signal and the actual output signal until the phase difference between every two intermediate input signals in sequence of the at least four intermediate input signals is respectively matched with the corresponding preset phase difference, at least four target intermediate input signals are output, the calibration updating of the input signals is realized, the calibration precision is improved, the effectiveness of reducing the noise of the phase-locked loop DSM is guaranteed, and further, the stability and the reliability of the phase-locked loop circuit can be improved.
Fig. 2 illustrates another phase-locked loop circuit provided in an embodiment of the present application, and as shown in fig. 2, the phase-locked loop circuit includes a signal processing module 10, and a calibration module 20 electrically connected to the signal processing module 10;
the signal processing module 10 is configured to perform signal processing on an input signal to obtain at least four intermediate input signals;
said calibration module 20 for determining a first output signal based on one of said intermediate input signals; controlling the phase-locked loop circuit to be in a normal working state based on the first output signal; determining an actual output signal based on at least four of the intermediate input signals under a condition that the phase-locked loop circuit is in a normal operating state; and calibrating and updating at least four intermediate input signals based on the first output signal and the actual output signal until the phase difference between every two of the at least four intermediate input signals is respectively matched with the corresponding preset phase difference, and outputting at least four target intermediate input signals.
Optionally, referring to fig. 2, the signal processing module includes a crystal oscillator 101, a phase frequency detector 102, a charge pump 103, a loop filter 104, a voltage controlled oscillator 105, and a polyphase filter 106, which are electrically connected in sequence.
Optionally, referring to fig. 2, the calibration module 20 includes a counter 201, a calibration unit 202, a trigger unit, a gating unit, a phase detection unit, and a digital-to-time conversion unit;
the trigger unit includes a first trigger 203a and a second trigger 203 b;
the gating unit includes a first gate 204a, a second gate 204b, and a third gate 204 c;
the phase detection unit comprises a first phase detector 205a and a second phase detector 205 b;
the digital-to-time conversion unit includes a first digital-to-time converter 206a, a second digital-to-time converter 206b, a third digital-to-time converter 206c, a fourth digital-to-time converter 206d, a fifth digital-to-time converter 206e, and a sixth digital-to-time converter 206 f;
an input of the counter 201, an input of the second digital-to-time converter 206b, an input of the third digital-to-time converter 206c, an input of the fourth digital-to-time converter 206d, and an input of the first gate 204a are electrically connected to an output of the polyphase filter 106, respectively;
the output end of the counter 201 is electrically connected with the input end of the first flip-flop 203a and the input end of the second flip-flop 203b respectively;
the output terminal of the first flip-flop 203a is electrically connected to the input terminal of the second gate 204b and the input terminal of the first digital-to-time converter 206a, respectively;
the output end of the second flip-flop 203b is electrically connected to the input end of the second gate 204b and the input end of the fifth digital-to-time converter 206e, respectively;
the output end of the second gate 204b is electrically connected to the input end of the phase frequency detector 102 and the input end of the sixth digital-to-time converter 206f, respectively;
the output end of the first gate 204a is electrically connected with the input end of the third gate 204 c;
the output end of the third gate 204c is electrically connected with the input end of the second flip-flop 203 b;
an output end of the sixth digital-to-time converter 206f and an output end of the crystal oscillator 101 are electrically connected to an input end of the second phase detector 205b, respectively;
the output end of the second phase detector 205b is electrically connected with the input end of the calibration unit 202;
the output terminal of the calibration unit 202 is electrically connected to the input terminal of the sixth digital-to-time converter 206f, the output terminal of the first phase detector 205a, the input terminal of the first digital-to-time converter 206a, the input terminal of the fifth digital-to-time converter 206e, the input terminal of the third gate 204c, the input terminal of the first gate 204a, the input terminal of the second digital-to-time converter 206b, the input terminal of the third digital-to-time converter 206c, the input terminal of the fourth digital-to-time converter 206d, and the input terminal of the counter 201, respectively.
Optionally, the calibration unit includes a calibrator, a differential integral modulator, and a phase locker, which are connected in sequence.
As an example, a Crystal Oscillator (XO) generates an input signal including a reference clock signal, the Crystal Oscillator sequentially outputs the input signal to a phase frequency detector and a charge pump, a Loop Filter (LPF), a Voltage Controlled Oscillator (VCO), the VCO outputs a differential signal to a Poly Phase Filter (PPF), the poly phase Filter may output four intermediate input signals, a first intermediate input signal (clk 1), a second intermediate input signal (clk 2), a third intermediate input signal (clk 3), and a fourth intermediate input signal (clk 4) to a second gate in the calibration block, the second gate may select a first flip-flop to output to the phase frequency detector and the charge pump via a first trigger output signal (clkmmd 1) generated by 1 to control the phase lock Loop to be in a normal operating state, further, after the phase locked loop is locked, calibration of the phase between the four intermediate input signals is started, specifically, a first gate selects a second flip-flop with output values of clk1, clk2, clk3 and clk4, a second trigger output signal (clkmmd 2) is generated at an output terminal of the second flip-flop, phase information data between clk1, clk2, clk3 and clk4 is determined by adjusting a first digital-to-time converter 206a, a second digital-to-time converter 206b, a third digital-to-time converter 206c, a fourth digital-to-time converter 206d, a fifth digital-to-time converter 206e and a sixth digital-to-time converter 206f, the phase information data is calibrated by the calibrator, and after the calibration is completed, the second gate is controlled to be 1, and clkmmd2 is selected as an input signal of the phase frequency detector and the charge pump, and the phase locked loop is locked again.
It should be noted that the phase-locked loop locking may include locking the phase-locked loop in an integer mode, that is, the phase-locked loop is in a normal operating state, the crystal oscillator 101, and the phase frequency detector 102, the charge pump 103, the loop filter 104, the voltage controlled oscillator 105, the polyphase filter 106, and the counter 201, which are sequentially electrically connected to the crystal oscillator 101, are in a normal operating state, and further, calibration of the four intermediate input signals clk1, clk2, clk3, and clk4 is started.
As another example, the calibration unit is a frequency divider, and for example, to adjust the fifth digital-to-time converter 206e, first, the third gate is set to 0, the control signal of the first gate is set to 0, the delay parameter of the fifth digital-to-time converter is adjusted until clkmmd1 is aligned with the rising edge of the first output value (div 1) of the frequency divider, and the phase information data is recorded: code1= T1. Secondly, setting the third gate to be 0, setting the control signal of the first gate to be 1, adjusting the delay parameter of the fifth digital-to-time converter until clkmmd1 is aligned with the rising edge of the second output value (div 2) of the frequency divider, and recording phase information data: code1= T2. Next, setting the third gate to 0 and the control signal of the first gate to 2, adjusting the delay parameter of the fifth digital-to-time converter until clkmmd1 is aligned with the rising edge of the third output value (div 3) of the frequency divider, and recording the phase information data: code1= T3. Setting the third gate to be 0 and the control signal of the first gate to be 3, adjusting the delay parameter of the fifth digital-to-time converter until clkmmd1 is aligned with the rising edge of the fourth output value (div 4) of the frequency divider, and recording the phase information data: code1= T4.
And setting the third gate to be 1, setting the control signal of the first gate to be 0, adjusting the delay parameter of the fifth digital-to-time converter until clkmmd1 is aligned with the rising edge of the first output value (div 1) of the frequency divider, and recording the phase information data: code1= T1-inv, wherein inv represents inverse phase.
Setting the third gate to be 1, setting the control signal of the first gate to be 1, adjusting the delay parameter of the fifth digital-to-time converter until clkmmd1 is aligned with the rising edge of the second output value (div 2) of the frequency divider, and recording the phase information data: code1= T2-inv, wherein inv represents inverse phase. Setting the third gate to be 1 and the control signal of the first gate to be 2, adjusting the delay parameter of the fifth digital-to-time converter until clkmmd1 is aligned with the rising edge of the third output value (div 3) of the frequency divider, and recording the phase information data: code1= T3-inv, wherein inv represents inverse phase. Setting the third gate to be 1 and the control signal of the first gate to be 3, adjusting the delay parameter of the fifth digital-to-time converter until clkmmd1 is aligned with the rising edge of the fourth output value (div 3) of the frequency divider, and recording the phase information data: code1= T4-inv, wherein inv represents inverse phase.
Further, the ideal output signal of clkmmd2 has a phase difference with the actual signal, and the phase difference needs to be calibrated, in this application, the phase difference needs to satisfy 2 × (T2-T1) = T3-T1, T2-T1= T3-T2= T4-T3, so as to determine the phase information data that needs to be adjusted, and the adjustment is repeated by adjusting the second digital-to-time converter 206b, the third digital-to-time converter 206c and the fourth digital-to-time converter 206d until T2, T3 and T4 satisfy the ideal condition that the phase difference needs to satisfy, that is, 2= T2-T1) = T3-T1, T2-T1= T3-T2= T4-T3, and the calibration is completed.
In the present application, the sixth digital-to-time converter 206f may be configured to calibrate the output of the doubled frequency signal of the crystal oscillator in a case where the crystal oscillator 101 outputs the doubled frequency clock, specifically, to perform coarse calibration between clk1 and clk3, and to perform coarse calibration between clk2 and clk4 in a case where the third gate is set to 0 and the second gate is set to 1.
According to the phase-locked loop circuit provided by the embodiment of the application, the signal processing module is used for processing the input signals to obtain at least four intermediate input signals; determining, by the calibration module, a first output signal based on one of the intermediate input signals; controlling the phase-locked loop circuit to be in a normal working state based on the first output signal; determining an actual output signal based on at least four of the intermediate input signals under a condition that the phase-locked loop circuit is in a normal operating state; the calibration updating is carried out on at least four intermediate input signals based on the first output signal and the actual output signal until the phase difference between every two intermediate input signals in sequence of the at least four intermediate input signals is respectively matched with the corresponding preset phase difference, at least four target intermediate input signals are output, the calibration updating of the input signals is realized, the calibration precision is improved, the effectiveness of reducing the noise of the phase-locked loop DSM is guaranteed, and further, the stability and the reliability of the phase-locked loop circuit can be improved.
Fig. 3 is a schematic flowchart illustrating a phase calibration method provided in an embodiment of the present application, where the phase calibration method is applied to a phase-locked loop circuit, and as shown in fig. 3, the phase calibration method includes:
step 301: the input signals are subjected to signal processing to obtain at least four intermediate input signals.
Step 302: a first output signal is determined based on one of the intermediate input signals.
Step 303: and controlling the phase-locked loop circuit to be in a normal working state based on the first output signal.
Step 304: determining an actual output signal based on at least four of the intermediate input signals under normal operating conditions of the phase locked loop circuit.
Step 305: and calibrating and updating at least four intermediate input signals based on the first output signal and the actual output signal until the phase difference between every two of the at least four intermediate input signals is respectively matched with the corresponding preset phase difference, and outputting at least four target intermediate input signals.
According to the phase calibration method provided by the embodiment of the invention, at least four intermediate input signals are obtained by processing the input signals; determining a first output signal based on one of the intermediate input signals; controlling the phase-locked loop circuit to be in a normal working state based on the first output signal; determining an actual output signal based on at least four of the intermediate input signals under a condition that the phase-locked loop circuit is in a normal operating state; the calibration updating is carried out on at least four intermediate input signals based on the first output signal and the actual output signal until the phase difference between every two intermediate input signals in sequence of the at least four intermediate input signals is respectively matched with the corresponding preset phase difference, at least four target intermediate input signals are output, the calibration updating of the input signals is realized, the calibration precision is improved, the effectiveness of reducing the noise of the phase-locked loop DSM is guaranteed, and further, the stability and the reliability of the phase-locked loop circuit can be improved. .
Optionally, fig. 4 shows a schematic flow chart of another phase calibration method provided in an embodiment of the present application, and referring to fig. 4, the phase calibration method includes:
step 401: the input signals are subjected to signal processing to obtain at least four intermediate input signals.
And respectively carrying out clock acquisition, frequency and phase discrimination, voltage conversion, filtering, voltage control oscillation, difference and multi-phase filtering on the input signals to obtain at least four intermediate input signals.
The at least four intermediate input signals comprise two sets of intermediate input signal groups, each set of intermediate input signal groups comprising two of the intermediate input signals in phase opposition.
Step 402: a first output signal is determined based on one of the intermediate input signals.
Step 403: and controlling the phase-locked loop circuit to be in a normal working state based on the first output signal.
Step 404: determining an actual output signal based on at least four of the intermediate input signals under normal operating conditions of the phase locked loop circuit.
Step 405: and calibrating and updating at least four intermediate input signals based on the first output signal and the actual output signal until the phase difference between every two of the at least four intermediate input signals is respectively matched with the corresponding preset phase difference, and outputting at least four target intermediate input signals.
Step 406: a second output signal is determined based on at least four of the target intermediate input signals.
According to the phase calibration method provided by the embodiment of the invention, at least four intermediate input signals are obtained by processing the input signals; determining a first output signal based on one of the intermediate input signals; controlling the phase-locked loop circuit to be in a normal working state based on the first output signal; determining an actual output signal based on at least four of the intermediate input signals under a condition that the phase-locked loop circuit is in a normal operating state; the calibration updating is carried out on at least four intermediate input signals based on the first output signal and the actual output signal until the phase difference between every two intermediate input signals in sequence of the at least four intermediate input signals is respectively matched with the corresponding preset phase difference, at least four target intermediate input signals are output, the calibration updating of the input signals is realized, the calibration precision is improved, the effectiveness of reducing the noise of the phase-locked loop DSM is guaranteed, and further, the stability and the reliability of the phase-locked loop circuit can be improved.
The phase calibration method provided by the present invention is applied to a phase-locked loop circuit including a controller and at least one phase-locked loop circuit electrically connected to the controller as shown in any one of fig. 1 to fig. 2, and is not described herein again to avoid repetition.
The electronic device in the embodiment of the present invention may be a device, or may be a component, an integrated circuit, or a chip in a terminal. The device can be mobile electronic equipment or non-mobile electronic equipment. By way of example, the mobile electronic device may be a mobile phone, a router, a tablet computer, a laptop computer, a palmtop computer, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a Personal Digital Assistant (PDA), and the like, and the non-mobile electronic device may be a server, a Network Attached Storage (NAS), a Personal Computer (PC), a television (television), a teller machine, a self-service machine, and the like, and the embodiments of the present invention are not particularly limited.
The electronic device in the embodiment of the present invention may be an apparatus having an operating system. The operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, and embodiments of the present invention are not limited in particular.
Fig. 5 is a schematic diagram illustrating a hardware structure of an electronic device according to an embodiment of the present invention. As shown in fig. 5, the electronic device 500 includes a processor 510.
As shown in fig. 5, the processor 510 may be a general processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more ics for controlling the execution of programs according to the present invention.
As shown in fig. 5, the electronic device 500 may further include a communication line 540. Communication link 540 may include a path to communicate information between the aforementioned components.
Optionally, as shown in fig. 5, the electronic device may further include a communication interface 520. The communication interface 520 may be one or more. The communication interface 520 may use any transceiver or the like for communicating with other devices or communication networks.
Optionally, as shown in fig. 5, the electronic device may further include a memory 530. The memory 530 is used to store computer-executable instructions for performing aspects of the present invention and is controlled for execution by the processor. The processor is used for executing the computer execution instructions stored in the memory, thereby realizing the method provided by the embodiment of the invention.
As shown in fig. 5, the memory 530 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a Random Access Memory (RAM) or other types of dynamic storage devices that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory 530 may be separate and coupled to the processor 510 via a communication line 540. Memory 530 may also be integrated with processor 510.
Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in this embodiment of the present invention.
In particular implementations, as one embodiment, processor 510 may include one or more CPUs, such as CPU0 and CPU1 in fig. 5, as shown in fig. 5.
In a specific implementation, as an embodiment, as shown in fig. 5, the terminal device may include a plurality of processors, such as the first processor 5101 and the second processor 5102 in fig. 5. Each of these processors may be a single core processor or a multi-core processor.
Fig. 6 is a schematic structural diagram of a chip according to an embodiment of the present invention. As shown in fig. 6, the chip 600 includes one or more than two (including two) processors 510.
Optionally, as shown in fig. 6, the chip further includes a communication interface 520 and a memory 530, and the memory 530 may include a read-only memory and a random access memory and provide operating instructions and data to the processor. The portion of memory may also include non-volatile random access memory (NVRAM).
In some embodiments, as shown in FIG. 6, memory 530 stores elements, execution modules or data structures, or a subset thereof, or an expanded set thereof.
In the embodiment of the present invention, as shown in fig. 6, by calling an operation instruction stored in the memory (the operation instruction may be stored in the operating system), a corresponding operation is performed.
As shown in fig. 6, the processor 510 controls the processing operation of any one of the terminal devices, and the processor 510 may also be referred to as a Central Processing Unit (CPU).
As shown in fig. 6, memory 530 may include both read-only memory and random access memory, and provides instructions and data to the processor. A portion of the memory 530 may also include NVRAM. For example, in applications where the memory, communication interface, and memory are coupled together by a bus system that may include a power bus, a control bus, a status signal bus, etc., in addition to a data bus. For clarity of illustration, however, the various buses are labeled as bus system 640 in fig. 6.
As shown in fig. 6, the method disclosed in the above embodiments of the present invention may be applied to a processor, or may be implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an ASIC, an FPGA (field-programmable gate array) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.
In one aspect, a computer-readable storage medium is provided, in which instructions are stored, and when executed, the instructions implement the functions performed by the terminal device in the above embodiments.
In one aspect, a chip is provided, where the chip is applied in a terminal device, and the chip includes at least one processor and a communication interface, where the communication interface is coupled to the at least one processor, and the processor is configured to execute instructions to implement the functions performed by the phase calibration method in the foregoing embodiments.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the procedures or functions described in the embodiments of the present invention are performed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a terminal, a user device, or other programmable apparatus. The computer program or instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program or instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire or wirelessly. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The usable medium may be a magnetic medium, such as a floppy disk, a hard disk, a magnetic tape; or optical media such as Digital Video Disks (DVDs); it may also be a semiconductor medium, such as a Solid State Drive (SSD).
While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
While the invention has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and figures are merely exemplary of the invention as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. A phase calibration method, applied to a phase-locked loop circuit, the method comprising:
processing the input signals to obtain at least four intermediate input signals;
determining a first output signal based on one of said intermediate input signals;
controlling the phase-locked loop circuit to be in a normal working state based on the first output signal;
determining an actual output signal based on at least four of the intermediate input signals under a condition that the phase-locked loop circuit is in a normal operating state;
and calibrating and updating at least four intermediate input signals based on the first output signal and the actual output signal until the phase difference between every two of the at least four intermediate input signals is respectively matched with the corresponding preset phase difference, and outputting at least four target intermediate input signals.
2. The phase calibration method of claim 1, wherein after outputting at least four target intermediate input signals, the method further comprises:
a second output signal is determined based on at least four of the target intermediate input signals.
3. The phase calibration method of claim 1, wherein the signal processing the input signals to obtain at least four intermediate input signals comprises:
and respectively carrying out clock acquisition, frequency and phase discrimination, voltage conversion, filtering, voltage control oscillation, difference and multi-phase filtering on the input signals to obtain at least four intermediate input signals.
4. A phase calibration method according to any one of claims 1 to 3, wherein said at least four intermediate input signals comprise two sets of intermediate input signals, each set of intermediate input signals comprising two of said intermediate input signals in opposite phase.
5. A phase-locked loop circuit, comprising: the calibration module is electrically connected with the signal processing module;
the signal processing module is used for processing the input signals to obtain at least four intermediate input signals;
the calibration module is used for determining a first output signal based on one intermediate input signal; controlling the phase-locked loop circuit to be in a normal working state based on the first output signal; determining an actual output signal based on at least four of the intermediate input signals under a condition that the phase-locked loop circuit is in a normal operating state; and calibrating and updating at least four intermediate input signals based on the first output signal and the actual output signal until the phase difference between every two of the at least four intermediate input signals is respectively matched with the corresponding preset phase difference, and outputting at least four target intermediate input signals.
6. The phase-locked loop circuit of claim 5, wherein the signal processing module comprises a crystal oscillator, a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a polyphase filter electrically connected in sequence.
7. The phase-locked loop circuit of claim 6, wherein the calibration module comprises a counter, a calibration unit, a trigger unit, a gating unit, a phase detection unit, and a digital time conversion unit;
the trigger unit comprises a first trigger and a second trigger;
the gating unit includes a first gate, a second gate, and a third gate;
the phase detection unit comprises a first phase detector and a second phase detector;
the digital-to-time conversion unit comprises a first digital-to-time converter, a second digital-to-time converter, a third digital-to-time converter, a fourth digital-to-time converter, a fifth digital-to-time converter and a sixth digital-to-time converter;
the input end of the counter, the input end of the second digital-to-time converter, the input end of the third digital-to-time converter, the input end of the fourth digital-to-time converter and the input end of the first gate are respectively and electrically connected with the output end of the polyphase filter;
the output end of the counter is electrically connected with the input end of the first trigger and the input end of the second trigger respectively;
the output end of the first trigger is electrically connected with the input end of the second gate and the input end of the first digital-to-time converter respectively;
the output end of the second trigger is electrically connected with the input end of the second gate and the input end of the fifth digital time converter respectively;
the output end of the second gate is electrically connected with the input end of the phase frequency detector and the input end of the sixth digital time converter respectively;
the output end of the first gate is electrically connected with the input end of the third gate;
the output end of the third gating device is electrically connected with the input end of the second trigger;
the output end of the sixth digital-to-time converter and the output end of the crystal oscillator are respectively and electrically connected with the input end of the second phase discriminator;
the output end of the second phase discriminator is electrically connected with the input end of the calibration unit;
the output end of the calibration unit is electrically connected with the input end of the sixth digital-to-time converter, the output end of the first phase detector, the input end of the first digital-to-time converter, the input end of the fifth digital-to-time converter, the input end of the third gate, the input end of the first gate, the input end of the second digital-to-time converter, the input end of the third digital-to-time converter, the input end of the fourth digital-to-time converter and the input end of the counter respectively.
8. The phase-locked loop circuit of claim 7, wherein the calibration unit comprises a calibrator, a differential-integral modulator, and a phase-locker connected in sequence.
9. An electronic device, comprising a processor, a memory and a computer program stored on the memory and executable on the processor, the computer program, when executed by the processor, implementing the steps of the phase calibration method according to any one of claims 1 to 4.
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