CN110798162B - Radio frequency ultra-wideband driving amplifier chip - Google Patents
Radio frequency ultra-wideband driving amplifier chip Download PDFInfo
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Abstract
The invention discloses a radio frequency ultra-wideband driving amplifier chip, which comprises two input resistors, two feedback resistors and an operational amplifier, wherein the two input resistors are connected with the input resistors; wherein the operational amplifier comprises: three amplifiers, comprising: a first-stage amplifier, a second-stage amplifier and a third-stage amplifier; two common mode feedback circuits comprising: a first-stage common mode feedback circuit and a second-stage common mode feedback circuit; the input end of the three-stage amplifier is connected with the input end of the first-stage amplifier, and the output end of the three-stage amplifier is connected with the output end of the second-stage amplifier to form a feedforward structure; the invention can realize very high bandwidth and linearity, is more suitable for being used in a resistance feedback structure and can realize better performance compared with the traditional two-stage or three-stage amplifier with the compensation capacitor Cc.
Description
Technical Field
The invention belongs to the field of radio frequency integrated circuits, and particularly relates to an ultra-wideband driving amplifier chip working in a radio frequency band.
Background
The radio frequency driving amplifier is used as a basic module and widely applied to various radio frequency integrated systems for improving the transmission quality and driving capability of signals. With the continuous development and perfection of the radio frequency technology, the working frequency of the chip is higher and higher, the high performance of the radio frequency integrated system is more and more embodied in higher frequency and broadband, so that the requirement on the radio frequency driving circuit is higher and higher, the design difficulty is correspondingly increased, and the research on the high-performance radio frequency driving amplifier chip has great application prospect and practical significance.
The current common technology for designing the driving amplifier mainly comprises an active follower structure, a common source amplifier structure, a resistor negative feedback structure and the like, wherein the source follower structure and the resistor negative feedback structure are commonly used for driving analog small signals, low-resistance loads, capacitive loads and the like due to higher linearity and lower output resistance, and the common source amplifier is commonly used for driving high-power signals and full-swing large signals. However, the common source amplifier structure has difficulty in increasing the bandwidth due to the existence of its parasitic capacitance at high frequencies, and the parasitic capacitance deteriorates the linearity of the driving circuit. Therefore, the present technology mainly researches a driving circuit of a resistive feedback structure.
In the resistive feedback amplifier structure, mainly composed of an operational amplifier A1, an input resistor R1 and a feedback resistor R2, the bandwidth of the feedback loop is mainly composed of the gain bandwidth product (GBW) of the amplifier A1 and the ratio of the input resistor R1 to the feedback resistor R2Determining the resistance ratioThe higher the bandwidth of the circuit output is, the smaller the bandwidth is, therefore, in order to improve the bandwidth of the resistive feedback amplifier, on one hand, the GBW of the operational amplifier can be improved, and further the power consumption of the operational amplifier is inevitably larger, or the operational amplifier can be designed by adopting Bicmos technology, and compared with CMOS technology, the GBW can be improved advantageously, on the other hand, the resistance ratio is reducedThe feedback amplifier has a lower operating gain and limited ability to amplify the signal.
The linearity of the driving amplifier should be better than that of the front-end circuit, otherwise, the nonlinearity of the driving circuit may deteriorate the linearity of the output signal, and if used as a separate driving chip, the linearity should be much higher than that of the front-end circuit to meet the application requirement. The related literature indicates that the linearity of the resistive negative feedback structure mainly depends on two aspects, one is the frequency gain of the operational amplifier in the feedback structure, at low frequency, the gain of the amplifier is higher, the gain of the feedback loop is larger, the feedback depth is deeper, the linearity is better, however, as the frequency increases, the gain of the amplifier decreases faster and the gain of the feedback loop decreases correspondingly, the linearity becomes worse, so the idea of improving the linearity of the resistive feedback circuit is to improve the low frequency gain of the amplifier, and under the condition of ensuring that the phase desirability is sufficient, the bandwidth of the amplifier of-3 dB is improved, and the GBW is correspondingly improved. Another aspect is the linearity of the operational amplifier itself, where the linearity of the amplifier itself is high, the coefficient of the provided non-linearity term is small, the linearity of the feedback loop is high, it is generally the output stage, possibly the second or third stage of the operational amplifier, that is decisive for the linearity, and thus the non-linearity optimization of the output stage amplifier is a technical difficulty to be solved.
The noise factor of the driver amplifier is not necessarily important to the performance of the system, because the driver amplifier is often at the output stage of the system and the gain of the front stage is high, the noise of the driver amplifier will not have a great influence on the system, and if the driver amplifier is at the front stage of the system, such as the driver analog-to-digital conversion circuit (ADC), the noise factor of the driver amplifier will have a great influence on the signal-to-noise ratio, dynamic range, and other performances of the ADC. Therefore, the noise of the driving amplifier should be as small as possible. For the structure of the resistor feedback amplifier, the sizes of the input resistor and the feedback resistor play a main role in determining, generally, the size of the feedback resistor is determined along with the determination of the bandwidth, and the value of the input resistor is determined along with the requirement or limitation of the gain of the feedback circuit, so that the noise level is determined according to the design of the system; the other main noise contribution comes from the operational amplifier, and the input stage or the first stage of the operational amplifier determines the noise level of the amplifier, so that the noise coefficient of the input stage of the amplifier is reduced, and the gain of the first stage amplifier is increased, which is beneficial to reducing the noise contribution of the output stage of the amplifier.
In summary, the invention adopts the structure design of the resistor feedback amplifier to drive the amplifier with high radio frequency bandwidth, the thought is basically clear, and the reasonable design of the amplifier structure is required to realize the required performance, thereby realizing the optimization and improvement of the performance.
Disclosure of Invention
It is an object of the present invention to address at least the above problems and/or disadvantages and to provide at least the advantages described below.
The invention provides a radio frequency ultra-wideband driving amplifier chip, which can realize very high bandwidth and linearity, and compared with a traditional two-stage or three-stage amplifier with a compensation capacitor Cc, the amplifier with the novel structure is more suitable for a resistance feedback structure, and can realize better performance.
The invention provides a radio frequency ultra-wideband driving amplifier chip with a novel structure, which adopts a three-stage amplifier, wherein two stages of amplifiers are connected in series to serve as a main channel amplifier, a third stage of amplifier is used for compensating phase desirability, the GBW of the amplifier depends on the input transconductance of the first stage of amplifier and the parasitic capacitance of a corresponding output node, and compared with the traditional two-stage or three-stage amplifier structure with a compensation capacitor Cc, the GBW of the traditional amplifier depends on the ratio of the input transconductance to the compensation capacitor, and the compensation capacitor is always larger than the parasitic capacitance, so that the improvement of the bandwidth of the amplifier is limited, and therefore, the GBW of a feedforward amplifier is much higher than the GBW of the traditional amplifier and is more suitable for high-bandwidth operation. In addition, the novel amplifier structure is consistent with the traditional amplifier structure in the design of the first-stage amplifier (input stage), the noise and the gain are optimized in the same way, and the same level of gain and noise can be achieved, so that the-3 dB of the novel amplifier structure is more distant, and the linearity is improved in the feedback circuit more favorably. In addition, the second stage of the operational amplifier with the novel structure is an output stage, a third stage amplifier is needed to be added, the signal line is reversely connected, the compensation of the phase desirability is realized by inserting a right half plane zero point, and the nonlinear term of the third stage amplifier and the nonlinear term of the second stage amplifier are opposite in sign and can be mutually offset, so that the nonlinearity of the whole operational amplifier is reduced, and the feedback circuit linearity is improved. In the traditional Cc compensated amplifier structure, the output stage is of a common source type or Class-AB structure, which is not beneficial to designing a high-bandwidth amplifier, and the parasitic capacitance of the output stage also enables the high-frequency nonlinearity of the output stage to be larger, and the output linearity to be lower, so that the amplifier with the novel structure is more suitable for designing a high-linearity driving amplifier.
The invention also provides a novel resistor feedback amplifier structure, which has the technical scheme that: by changing the input resistance of the feedback structure, the gain is adjustable on the premise of not changing the bandwidth, so as to adapt to different application environments. The amplification factor of the feedback structure is changed by changing the size of the feedback resistor, so that the output bandwidth is reduced along with the increase of the gain, and the gain is not lost.
The novel structure operational amplifier is brought into a resistor feedback structure, in order to work in a radio frequency band, the gain of the feedback amplifier is generally low, the resistance values of an input resistor and a feedback resistor are generally not very high, the order of magnitude is generally tens to hundreds of ohms, and the size of the feedback resistor is not too large due to parasitic capacitance of the resistor. In order to improve the matching performance of the circuit layout, the sizes and the dimension of the feedback resistor and the input resistor are formed by serially or parallelly connecting small resistors with the same size.
In order not to affect the driving capability of the front-end circuit, the input resistance of the driving amplifier should be as high as possible, and therefore, the bandwidth and the driving capability of the front-end circuit are a trade-off relationship.
The feedforward operational amplifier provided by the invention is based on the traditional feedforward amplifier structure, and the innovative amplifier structure is provided by optimizing the power consumption of the operational amplifier and changing the relation of circuit connection, so that the phase desirability and the linearity are improved.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of the overall circuit of a resistive feedback amplifier according to the present invention;
FIG. 2 is a schematic diagram of the overall structure of the novel feed-forward operational amplifier according to the present invention;
FIG. 3 is a schematic diagram of a first stage amplifier of the operational amplifier according to the present invention;
FIG. 4 is a schematic diagram of a second stage amplifier of the operational amplifier according to the present invention;
FIG. 5 is a schematic diagram of a third stage of an operational amplifier according to the present invention;
FIG. 6 is a schematic diagram of a first stage common mode feedback circuit of an operational amplifier according to the present invention;
fig. 7 is a schematic diagram of a second-stage common mode feedback circuit of the operational amplifier according to the present invention.
Detailed Description
The present invention is described in further detail below with reference to the drawings to enable those skilled in the art to practice the invention by referring to the description.
It will be understood that terms, such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
As shown in fig. 1, the present invention proposes a novel resistive feedback amplifier structure, in which input signals VIN and VIP are connected to one ends of input resistors R1 and R2, the other ends of the input resistors are respectively connected to two input ports of a fully differential operational amplifier, one ends of feedback resistors R3 and R4 are connected to the input port of the amplifier, and the other ends of the feedback resistors are respectively connected to output ports VON and VOP of the amplifier, thereby forming a fully differential feedback structure. The working principle of the circuit is that the gain can be adjusted by changing the input resistors R1 and R2 of the feedback structure without changing the feedback resistors R3 and R4 on the premise of not changing the output bandwidth so as to adapt to different application environments. The amplification factor of the feedback structure can also be changed by changing the sizes of the feedback resistors R3 and R4, but the output bandwidth is reduced along with the increase of the gain due to the existence of the parasitic resistance capacitance, and it should be noted that the input resistance cannot be reduced infinitely, and when the input resistance is reduced to a certain extent, the driving capability of the front-stage circuit to the feedback amplifier is weakened, and the signal transmission quality is affected, so that the method for changing the gain of the feedback amplifier by changing the input resistance is determined according to the specific application environment.
As shown in FIG. 2, the invention provides a novel structure of a feedforward operational amplifier, which adopts a three-stage amplifier and a two-stage common mode feedback circuit, wherein the first-stage amplifier and the second-stage amplifier are in direct current coupling, the input of the third-stage amplifier is connected with the input of the first-stage amplifier, the output of the third-stage amplifier is connected with the output of the second-stage amplifier to form a feedforward structure, the reference voltage of the common mode feedback circuit is VCOM, the first-stage common mode feedback amplifier is the bias common mode level of the first-stage amplifier, the output of the first-stage amplifier is connected with the resistive input of the first-stage common mode feedback circuit, the output of the first-stage common mode feedback circuit is connected with the grid electrode of a load PMOS tube of the first-stage amplifier, the output common mode level of the first-stage amplifier is VCOM under the action of the common mode feedback circuit, and the second-stage common mode feedback amplifier is the bias common mode level of the second-stage amplifier, and the output common mode level of the second-stage amplifier is VCOM. Each stage of amplifier and each stage of common mode feedback circuit are described in detail below.
As shown in fig. 3, the circuit structure of the first-stage amplifier is shown, the amplifier is composed of 4 NMOS tubes (N1, N2, N3, N4) and 4 PMOS tubes (P1, P2, P3, P4), the circuit structure is a fully differential common source amplifier structure, tail tubes N3 and N4 are adopted to provide bias current for input transcatheter tubes N1 and N2, source ends and substrate of N3 and N4 are connected with GND ground wire, the gate is connected with bias potential VNB, drain ends are respectively connected with source ends and substrate ends of N1 and N2, N1 and N2 form a bias structure, the gate ends of N1 and N2 are respectively connected with input signals VIN and VIP, the drain ends are respectively connected with drain ends of load tubes P1 and P2, P3 and P4, the source ends and the substrate are connected with VDD power line, the gate is connected with output vcb 1, P2 and P3 of the first-stage common mode feedback circuit to form a negative resistance structure, the drain ends of P2 and P3 are connected with the drain ends of N2 to the drain ends of P3, the drain ends of the P2 are connected with the drain ends of the P2 to the P2, the drain ends of the P2 are connected with the drain ends of the P2, and the drain ends of the P2 are connected with the P2, the drain ends of the P2 and the P2 are connected with the P2, the load structure is further, the current mirror is further improved, the current-stage amplifier is improved, and the current-stage amplifier has a current-to be improved, and the current-stage-to the current-stage amplifier has a certain impedance-to be improved, and the current-to the current-stage amplifier has a certain impedance-to the current-stage amplifier.
As shown in fig. 4, a circuit configuration diagram of a second stage amplifier is shown, which is composed of 10 NMOS transistors (N5, N6, N7, N8, N9, N10, N11, N12, N13, N14), 6 PMOS transistors (P5, P6, P7, P8, P9, P10) and 2 capacitors C1, C2, the input transistors are supplied with bias currents using N11, N12, N13 and N14 as tail pipes, the source and substrate of the tail pipes are grounded GND, the gates are biased with respect to the bias potentials VNB, the drain terminals of N11 and N12 are grounded with respect to the source and substrate terminals of N5, N6 and N7, the drain terminals of N13 and N14 are grounded with respect to the source and substrate terminals of N8, N9 and N10, N5, N6, N7, N8, N9 and N10, and each of the pipes is connected to form a bias structure, the input stage of N5 is connected to the output VOP1 of the first stage amplifier, the drain terminals are connected to the drain terminals of P5 and P6, and the drain terminals of N24 are connected to the drain terminals of N1 and the drain of N1 of the first stage amplifier are connected to the drain of the first stage amplifier, the drain terminal is connected with the drain terminal VOPP of the P9 and the P10, the grid electrode and the drain terminal of the N8 are connected with the capacitor C2 in a crossing way, the grid electrode of the input tube N6 is connected with the VON1, the drain terminal is connected with the output VCMFB2 of the second-stage common mode feedback circuit, the drain terminal is connected with the output VON, the grid electrode of the input tube N9 is connected with the output VCMFB2 of the second-stage common mode feedback circuit, the drain terminal is connected with the output VOP of the input tube N10, the source terminal of the P5, the P6, the P9 and the P10 are connected with the substrate terminal VDD, the grid terminals of the P5 and the P9 are connected with the grid terminal VONN of the P6 and the P10, the drain terminal of the P6 and the grid terminal are respectively connected with each other to form a diode connection mode, the drain terminal VONN of the N5, the drain terminal of the P7 and the substrate terminal of the P8 are respectively connected with the source terminal and the VOP, the grid terminal of the drain terminal of the P8 are respectively connected with the VONN, the drain terminal VOPP, the drain terminal of the drain terminal is respectively connected with the drain terminal VOP and the drain terminal of the P, the single-ended output amplifier is formed by parallel connection, the differential input ends are respectively the output of the first-stage amplifier and the common mode feedback signal, the output load adopts a small-size pipe and is connected into a current mirror load structure, the driving capability of the output circuit is improved, P5, P10, N6 and N9 are connected in a reverse bias way, the phase pre-degree of the circuit can be improved, the coefficient of the third-order nonlinear item of the pipe is opposite to the coefficient of the third-order nonlinear item of the corresponding parallel connected pipe P6, P9, N7 and N10, the linearity of the second-stage amplifier is improved, and the linearity of the whole operational amplifier is improved.
As shown in fig. 5, the circuit structure diagram of the third-stage amplifier is shown, the amplifier is composed of 4 NMOS tubes (N15, N16, N17, N18) and 2 capacitors (C3, C4), N17 and N18 are adopted as tail tubes, bias currents are respectively provided for the input transcatheter N15 and N16, the source end and the substrate end of N17 and N18 are connected with GND ground, the gate electrode is connected with bias potential VNB, the drain end is respectively connected with the source end and the substrate end of N15 and N16, the two ends of the capacitors C3 and C4 are bridged between two drain end potentials, N15 and N16 form a lining bias structure, the gate electrode is respectively connected with input signals VIN and VIP, the drain end is respectively in VOPP and VONN, the structure of the third-stage amplifier is in a source end negative feedback structure, the source end is connected with the capacitors as negative feedback elements for improving high-frequency impedance, and further improving the bandwidth of the third-stage amplifier. In the overall operational amplifier configuration, a third stage amplifier is connected across the input and output signals to form a feed forward path, providing a half-plane zero in the frequency domain for phase pre-distortion compensation, and enabling reduced output stage nonlinearity and improved amplifier linearity.
As shown in fig. 6, the amplifier is composed of 3 NMOS transistors (N19, N20, N21), 2 PMOS transistors (P11, P12), 2 resistors (R1, R2) and 2 capacitors (C5, C4), N21 is adopted as a tail pipe, a source terminal and a substrate are connected with GND ground, a gate is connected with bias voltage VNB, a drain terminal is connected with a source terminal and a substrate terminal of N19 and N20, and bias current is provided for the input transistors N19 and N20. The capacitor C5 is connected in parallel with the resistor R1, the capacitor C6 is connected in parallel with the resistor R2, and is respectively connected with the output signals VON1 and VOP1 of the first-stage amplifier, the other ends of the two groups of parallel capacitors and resistors are connected together, the grid input of the N19 is commonly connected, the grid input of the N20 is connected with the external reference voltage VCOM, the drain ends of the N19 and the N20 are respectively connected with the drain ends of the P11 and the P12, in order to improve the gain of the common-mode feedback circuit, the P11 and the P12 are connected into a load of a current mirror structure, the drain end of the P11 is connected with the grid, and is connected with the grid of the P12, the source end of the P11 and the P12 are commonly connected with the grid of a VDD line, and the output VCMFB1 of the P12 is connected with the grid of the current mirror load PMOS tube of the first-stage amplifier, so that a working loop of the first-stage amplifier and the common-mode feedback circuit is formed, and the output common-mode voltage of the first-stage amplifier is stabilized as long as the loop stability is ensured, and the output potential of the first-stage amplifier is equal to VCOM.
As shown in fig. 7, the amplifier is composed of 2 NMOS tubes (N22, N23), 3 PMOS tubes (P13, P14, P15), 2 resistors (R3, R4) and 2 capacitors (C7, C8), wherein P13 is adopted as a tail tube, a source terminal and a substrate are connected with a VDD power line, a gate is connected with a bias voltage VPB, and a drain terminal is connected with the source terminal and the substrate terminal of the input tubes P14 and P15 to provide bias current for P14 and P15. The capacitor C7 is connected in parallel with the resistor R3, the capacitor C8 is connected in parallel with the resistor R4 and is respectively connected with the output signals VON and VOP of the second-stage amplifier, the other ends of the two groups of parallel capacitors and resistors are connected together and are commonly connected with the grid input of the P14, the grid input of the P15 is connected with the external reference voltage VCOM, the drain ends of the P14 and the P15 are respectively connected with the drain ends of the N22 and the N23, in order to improve the gain of the common-mode feedback circuit, the N22 and the N23 are connected into a load of a current mirror structure, the drain end of the N22 is connected with the grid and is connected with the grid of the N23, the source end of the N22 and the source end of the N23 are commonly connected with the GND ground wire, the output VCMFB2 of the N23 is connected with the grid of the N7 and the N10 of the second-stage amplifier, and thus a loop of the second-stage amplifier is formed, and the output potential of the second-stage amplifier can be determined according to VCOM as long as the loop stability is ensured.
Although the embodiments of the present invention have been disclosed above, it is not limited to the use listed in the specification and the embodiments, and can be fully applied to various fields suitable for the present invention; additional modifications will readily occur to those skilled in the art. Therefore, the invention is not to be limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.
Claims (3)
1. A radio frequency ultra wideband driver amplifier chip, wherein the operational amplifier comprises:
three amplifiers, comprising: a first-stage amplifier, a second-stage amplifier and a third-stage amplifier;
two common mode feedback circuits comprising: a first-stage common mode feedback circuit and a second-stage common mode feedback circuit;
Wherein,
The input end of the three-stage amplifier is connected with the input end of the first-stage amplifier, and the output end of the three-stage amplifier is connected with the output end of the second-stage amplifier to form a feedforward structure;
the output of the first-stage amplifier is connected with the resistance input of a first-stage common-mode feedback circuit, the output of the first-stage common-mode feedback circuit is connected with the grid electrode of a load PMOS tube of the first-stage amplifier, and the common-mode level of the output of the first-stage amplifier is VCOM under the action of a common-mode feedback loop;
the output of the second-stage amplifier is connected with the resistance input of the second-stage common mode feedback circuit, the output of the second-stage common mode feedback circuit is connected with the grid electrode of the load PMOS tube of the second-stage amplifier, and the common mode level of the output of the second-stage amplifier is VCOM under the action of the common mode feedback loop;
the first-stage amplifier includes: the four NMOS tubes are respectively: n1, N2, N3, and N4; four PMOS tubes are respectively: p1, P2, P3 and P4; wherein,
The N3 and N4 serve as tail pipes to provide bias currents for N1 and N2;
the source end and the substrate end of the N3 and the N4 are both grounded to GND ground, the grid electrode is connected to bias potential VNB, the drain end is respectively connected to the source end and the substrate end of the N1 and the N2, and the N1 and the N2 form a substrate bias structure;
the grid electrodes of the N1 and the N2 are respectively connected with the signal VIN and the VIP, and the drain electrodes of the PMOS tubes P1 and P2, P3 and P4 are connected with the drain electrodes;
the source ends and the substrate ends of the four PMOS tubes are connected with a VDD power line, P1 and P4 form a current load structure, and P2 and P3 form a negative resistance structure;
the grid electrodes of the P1 and the P4 are connected with the output VCMFB1 of the primary common mode feedback circuit; the grid electrode of the P2 is connected with the drain end of the P3, and the grid electrode of the P3 is connected with the drain end of the P2;
The two-stage amplifier includes: ten NMOS tubes are respectively: n5, N6, N7, N8, N9, N10, N11, N12, N13, N14; six PMOS tubes are respectively: p5, P6, P7, P8, P9, P10; two capacitors are respectively: c1, C2; wherein, the N11, N12, N13, N14 is used as a tail pipe to provide bias current for N5, N6, N7, N8, N9, N10; the source ends and the substrate ends of the N11, N12, N13 and N14 are connected with GND ground, the grid electrode is connected with bias potential VNB, the drain ends of the N11, N12 are connected with the source ends and the substrate ends of the N5, N6 and N7, and the drain ends of the N13 and N14 are connected with the source ends and the substrate ends of the N8, N9 and N10; the N5, N6, N7, N8, N9 and N10 form an input stage, and each pipe is connected to form a lining bias structure; the grid electrode of the N5 is connected with the output VOP1 of the primary amplifier, the drain end is connected with the drain ends VONN of the P5 and the P6, the grid electrode and the drain end of the N5 are connected with the capacitor C1 in a crossing way, and the drain end is connected with the VONN; the grid electrode of the N6 is connected with the output VON1 of the primary amplifier, and the drain electrode of the N6 is connected with the output VON; the grid electrode of the N7 is connected with the output VCMFB2 of the two-stage common mode feedback circuit, and the drain electrode is connected with the output VON; the grid electrode of the N8 is connected with the output VON1 of the primary amplifier, the drain ends of the N8 are connected with the drain ends VOPP of the P9 and the P10, the grid electrode of the N8 is connected with the capacitor C2 in a crossing mode, the drain end of the N8 is connected with the VOPP, the grid electrode of the N9 is connected with the VOP1, and the drain end of the N9 is connected with the output VOP; the grid electrode of the N10 is connected with the output VCMFB2 of the two-stage common mode feedback circuit, and the drain electrode is connected with the output VOP; the source end and the substrate end of the P5, the P6, the P9 and the P10 are connected with the VDD, the grid electrode of the P5 and the P9 is connected with the VOPP, the grid electrode of the P6 and the P10 is connected with the VONN, the drain end and the grid electrode of the P6 and the P9 are respectively connected together, and each forms a diode connection mode; the source end and the substrate end of P7 and P8 are connected with VDD, the grid electrode is respectively connected with VONN and VOPP, and the drain end is respectively connected with VON and VOP;
The three-stage amplifier includes: the four NMOS tubes are respectively: n15, N16, N17, N18; two capacitors are respectively: c3 and C4; wherein,
N17 and N18 are used as tail pipes, and bias currents are respectively provided for N15 and N16; the source ends and the substrate ends of N17 and N18 are connected with GND ground, the grid electrode is connected with bias potential VNB, and the drain ends are respectively connected with the source ends and the substrate ends of N15 and N16;
the two ends of the capacitor C3 and the capacitor C4 are connected between the two drain terminal potentials in a bridging way;
N15, N16 constitute lining bias structure, and the grid connects input signal VIN and VIP respectively, and the drain terminal is voPP and VONN respectively.
2. The radio frequency ultra-wideband driver amplifier chip of claim 1, wherein said primary common mode feedback circuit comprises:
the three NMOS tubes are respectively: n19, N20, N21;
The two PMOS tubes are respectively: p11, P12, two capacitances C5, C6;
Wherein,
The N21 is used as a tail pipe to provide bias current for N19 and N20, the source end and the substrate end of the N21 are connected with GND ground, the grid electrode is connected with bias voltage VNB, and the drain end is connected with the source end and the substrate end of the N19 and the N20;
The capacitor C5 is connected in parallel with the resistor R1, the capacitor C6 is connected in parallel with the resistor R2, and is respectively connected with the output signals VON1 and VOP1 of the first-stage amplifier, the other ends of the two groups of parallel capacitors and resistors are connected together, and the two groups of parallel capacitors and resistors are connected with the grid electrode of the N19; the gate input of the N20 is connected to an external reference voltage VCOM,
The drain ends of the N19 and the N20 are respectively connected with the drain ends of the P11 and the P12, the P11 and the P12 are connected into a load of a current mirror structure, the drain end of the P11 is connected with the grid electrode and is connected with the grid electrode of the P12, the source ends and the substrate of the P11 and the P12 are both connected with a VDD line, and the output VCMFB1 of the P12 is connected with the grid electrode of a current mirror load PMOS tube of the primary amplifier.
3. The radio frequency ultra-wideband driver amplifier chip of claim 1, wherein said secondary common mode feedback circuit comprises: two NMOS tubes are respectively: n22, N23; three PMOS tubes are respectively: p13, P14, P15; two resistors are respectively: r5, R6; two capacitances: c7, C8;
Wherein,
The P13 is used as a tail pipe to provide bias current for the P14 and the P15, the source end and the substrate end of the P13 are connected with a VDD power line, the grid electrode is connected with bias voltage VPB, and the drain end is connected with the source end and the substrate end of the P14 and the P15;
the capacitor C7 is connected in parallel with the resistor R5, the capacitor C8 is connected in parallel with the resistor R6 and is respectively connected with the output signals VON and VOP of the second-stage amplifier, and the other ends of the two groups of parallel capacitors and resistors are connected together and are commonly connected with the grid input of the P14; the gate input of P15 is connected to an external reference voltage VCOM,
The drain ends of the P14 and the P15 are respectively connected with the drain ends of the N22 and the N23, the N22 and the N23 are connected into a load of a current mirror structure, the drain end of the N22 is connected with the grid electrode of the N23, the source ends of the N22 and the N23 and the substrate are commonly connected with the GND ground wire, and the output VCMFB2 of the N23 is connected with the grid electrodes of the N7 and the N10 of the second-stage amplifier.
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