CN110797259B - Homoepitaxy gallium nitride substrate processing method and gallium nitride substrate - Google Patents
Homoepitaxy gallium nitride substrate processing method and gallium nitride substrate Download PDFInfo
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- CN110797259B CN110797259B CN201911013915.5A CN201911013915A CN110797259B CN 110797259 B CN110797259 B CN 110797259B CN 201911013915 A CN201911013915 A CN 201911013915A CN 110797259 B CN110797259 B CN 110797259B
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 83
- 239000000758 substrate Substances 0.000 title claims abstract description 82
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 79
- 238000003672 processing method Methods 0.000 title claims abstract description 18
- 238000001657 homoepitaxy Methods 0.000 title abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 76
- 230000008569 process Effects 0.000 claims abstract description 66
- 238000005530 etching Methods 0.000 claims abstract description 52
- 238000001312 dry etching Methods 0.000 claims abstract description 39
- 238000011282 treatment Methods 0.000 claims abstract description 13
- 230000001133 acceleration Effects 0.000 claims abstract description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 238000009616 inductively coupled plasma Methods 0.000 claims description 7
- 230000000694 effects Effects 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000001179 sorption measurement Methods 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30612—Etching of AIIIBV compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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Abstract
The invention is suitable for the technical field of semiconductors, and provides a homoepitaxy gallium nitride substrate processing method and a gallium nitride substrate, wherein the method comprises the following steps: before the epitaxial growth of the heterojunction on the gallium nitride substrate, carrying out dry etching process treatment on the gallium nitride substrate, wherein the etching angle is not equal to 90 degrees, and the etching angle is the included angle between the plasma acceleration direction of the gallium nitride and the gallium nitride substrate. The invention can relieve the uneven characteristic of the surface of the GaN substrate, reduce the adsorption area of silicon and inhibit the secondary channel effect by the bevel dry etching process.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a homoepitaxy gallium nitride substrate processing method and a gallium nitride substrate.
Background
Compared with the existing heteroepitaxial gallium nitride (GaN) HEMT (High Electron Mobility Transistor) device, homoepitaxial GaN has the advantages of low dislocation density, low current collapse, High reliability and High breakdown. However, since the surface of the GaN substrate is prone to absorb impurities, the conventional homoepitaxial GaN HEMT has a side channel and the device leakage is large.
At present, the low-leakage homoepitaxy GaN HEMT device structure adopts an introduced impurity compensation or high-temperature etching process to inhibit a secondary channel and reduce leakage current. However, the unevenness of the substrate surface is not relieved by the structures, or the unevenness is increased, the adsorption area of silicon Si is still large, Si is still adsorbed by exposure to air, and the improvement of the secondary channel effect is limited.
Disclosure of Invention
In view of this, embodiments of the present invention provide a homoepitaxial gallium nitride substrate processing method and a gallium nitride substrate, so as to solve the problem of the sub-channel effect caused by uneven substrate surface in the prior art.
A first aspect of an embodiment of the present invention provides a method for processing a homoepitaxial gallium nitride substrate, including:
before the epitaxial growth of the heterojunction on the gallium nitride substrate, carrying out dry etching process treatment on the gallium nitride substrate, wherein the etching angle is not equal to 90 degrees, and the etching angle is the included angle between the plasma acceleration direction of the gallium nitride and the gallium nitride substrate.
A second aspect of an embodiment of the present invention provides a gallium nitride substrate, which is obtained by processing according to the above homoepitaxial gallium nitride substrate processing method.
According to the homoepitaxy gallium nitride substrate processing method provided by the embodiment of the invention, before the heterojunction is epitaxially grown on the gallium nitride substrate, the gallium nitride substrate is subjected to dry etching process processing, the etching angle is not equal to 90 degrees, and the etching angle is an included angle between the plasma acceleration direction of the gallium nitride and the gallium nitride substrate. According to the embodiment of the invention, the uneven characteristic of the surface of the GaN substrate can be relieved, the adsorption area of silicon is reduced, and the secondary channel effect is inhibited through the bevel dry etching process.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a schematic view of a substrate being processed by a bevel-free etching process according to an embodiment of the present invention;
FIG. 2 is a schematic view of a substrate before being processed by the bevel etch process provided in an embodiment of the present invention;
FIG. 3 is a schematic view of a substrate after being processed by a bevel etch process according to an embodiment of the present invention;
fig. 4 is a schematic diagram of an etching angle of two dry etching processes provided in the embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
The terms "comprises" and "comprising," and any variations thereof, in the description and claims of this invention and the above-described drawings are intended to cover non-exclusive inclusions. For example, a process, method, or system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," and "third," etc. are used to distinguish between different objects and are not used to describe a particular order.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Example 1:
one embodiment of the present invention provides a homoepitaxial gallium nitride substrate processing method, which comprises the following steps:
before the epitaxial growth of the heterojunction on the gallium nitride substrate, carrying out dry etching process treatment on the gallium nitride substrate, wherein the etching angle is not equal to 90 degrees, and the etching angle is the included angle between the plasma acceleration direction of the gallium nitride and the gallium nitride substrate.
At present, impurity compensation is introduced into the structure of the low-leakage-point homoepitaxy GaN HEMT device or a high-temperature etching process is adopted to inhibit a secondary channel, so that leakage current is reduced, but unevenness of the surface of a substrate is not relieved by the structure obtained by the method, as shown in FIG. 1, 1 in FIG. 1 represents a gallium nitride substrate, 2 represents a channel layer, 3 represents a barrier layer, dots at 4 represent main channel electrons, and dots at 5 represent secondary channel electrons. As shown in fig. 1, the surface of the gallium nitride substrate adjacent to the channel layer has an uneven phenomenon, and the dots in fig. 1 represent electrons, and the distribution of the electrons in the sub-channel can be seen from fig. 1.
In this embodiment, fig. 2 shows a schematic view of a substrate before the substrate processing method in the present application is performed, and as shown in fig. 2, the surface of the substrate is uneven before the substrate is processed. In order to solve the problem of uneven surface of the gallium nitride substrate, the gallium nitride substrate is subjected to dry etching process treatment before a heterojunction is grown on the gallium nitride substrate, and the acceleration direction of gallium nitride plasma is not vertical to the surface of the gallium nitride substrate when the dry etching process treatment is carried out.
Fig. 3 shows a schematic diagram of a gallium nitride substrate obtained by the method according to the present application, as shown in fig. 3, the surface of the gallium nitride substrate subjected to bevel etching in the present application is flat, and the distribution of electrons after bevel etching treatment can be found from fig. 3, and the secondary channel electrons are uniformly distributed on the surface of the substrate.
In one embodiment, the dry etching process of the gallium nitride substrate specifically includes:
and carrying out dry etching process treatment on the gallium nitride substrate at least once.
In one embodiment, the etching angle satisfies: 0 < a <180, where a denotes the etch angle.
In one embodiment, the gallium nitride substrate is subjected to at least two dry etching processes, and the etching angle of each dry etching process is different.
In this embodiment, the gallium nitride substrate may be subjected to a dry etching process for a plurality of times. And the etching angle in each dry etching can be the same or different.
In one embodiment, the etching angle satisfies: a is more than or equal to 30 degrees and less than or equal to 60 degrees, wherein a represents an etching angle.
In one embodiment, the etching angle satisfies: a is more than or equal to 120 degrees and less than or equal to 150 degrees, wherein a represents an etching angle.
In one embodiment, the dry etch process comprises an inductively coupled plasma etch process.
In this embodiment, the dry etching process may be an inductively coupled plasma ICP etching process.
In one embodiment, the dry etching process comprises a reactive ion etching process.
In this embodiment, the dry etching process may also be a reactive ion RIE etching process.
In one embodiment, after the dry etching process, the gallium nitride substrate is subjected to a wet etching process.
Specifically, wet etching treatment is performed on the gallium nitride substrate between two dry etching process treatments.
The homoepitaxy gallium nitride substrate processing method provided by the embodiment can effectively relieve the uneven characteristic of the surface of the gallium nitride substrate, reduce the adsorption area of silicon and inhibit the secondary channel effect.
In one embodiment, the gallium nitride substrate is processed according to the homoepitaxial gallium nitride substrate processing method.
In the embodiment, the gallium nitride substrate obtained by the bevel dry etching process has a relatively flat substrate surface, so that the silicon adsorption area can be reduced, and the secondary channel effect can be inhibited.
In one embodiment of the present invention, as a specific embodiment, a method for processing a homoepitaxial gallium nitride substrate is as follows:
before the gallium nitride substrate is subjected to epitaxial growth of a heterojunction, the gallium nitride substrate is subjected to one-time dry etching process treatment, and the etching angle between the acceleration direction of the plasma and the surface of the substrate is greater than 0 degree and less than 180 degrees and is not equal to 90 degrees.
Specifically, the etching angle is an angle of 30 degrees or more and 60 degrees or less, or an angle of 120 degrees or more and 150 degrees or less. Preferably, the etching angle is 60 degree.
The one-time dry etching process can be an ICP (inductively coupled plasma) etching process, and wet etching is carried out after the one-time dry etching process.
In an embodiment of the present invention, as another specific embodiment, before performing epitaxial growth of a heterojunction on a gallium nitride substrate, the gallium nitride substrate may be subjected to two dry etching processes, where both etching processes keep an etching angle greater than 0 degree and less than 180 degrees, and not equal to 90 degrees.
Further, as shown in fig. 4, fig. 4 is a schematic view showing an etching angle in the etching process, fig. 4a is a schematic view of a first etching process, and fig. 4b is a schematic view of a second etching process.
In fig. 4, an angle a' is a first etching angle, an angle a ″ is a second etching angle, the two etching angles are different, and the sum of the first etching angle and the second etching angle is equal to 180 degrees. Preferably, the first etching angle may be 60 degrees, and the second etching angle may be 120 degrees.
The gallium nitride substrate can be processed by RIE etching process, and wet etching process can be performed between two dry etching processes.
In an embodiment of the present invention, as another specific embodiment, before the gallium nitride substrate grows the heterojunction, the gallium nitride substrate may further be subjected to 3 times of dry etching process treatment, where the first two times keep the etching angle of the gallium nitride substrate with the plasma acceleration direction greater than 0 degree and less than 180 degrees and not equal to 90 degrees, and the last time keeps the etching angle at 90 degrees.
Specifically, the first etching angle may be 45 degrees, the second etching angle may be 135 degrees, and the third etching angle may be 90 degrees.
The dry etching process adopted in this embodiment may be an RIE dry etching process, or an ICP dry etching process.
Furthermore, a wet etching process can be performed between the first dry etching process and the second dry etching process, a wet etching process can be performed between the second dry etching process and the third dry etching process, and after the third dry etching process, a wet etching process can be performed on the gallium nitride substrate.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (8)
1. A homoepitaxial gallium nitride substrate processing method is characterized by comprising the following steps:
before a heterojunction is epitaxially grown on a gallium nitride substrate, carrying out dry etching process treatment on the gallium nitride substrate, wherein the etching angle is not equal to 90 degrees, and the etching angle is an included angle between the plasma acceleration direction of the gallium nitride and the gallium nitride substrate;
carrying out dry etching process treatment on the gallium nitride substrate at least twice, wherein the etching angle of each dry etching process is different;
at least one etching angle is less than 90 degrees; at least one etching angle is larger than 90 degrees.
2. The homoepitaxial gallium nitride substrate processing method of claim 1, further comprising: the etching angle satisfies: 0 < a <180, where a denotes the etch angle.
3. The homoepitaxial gallium nitride substrate processing method of claim 1, wherein at least one time the etch angle satisfies: 30 < a <60, where a denotes the etch angle.
4. The homoepitaxial gallium nitride substrate processing method of claim 1, wherein at least one time the etch angle satisfies: 120 < a <150, where a denotes the etch angle.
5. The homoepitaxial gallium nitride substrate processing method of claim 1, wherein the dry etch process comprises an inductively coupled plasma etch process.
6. The homoepitaxial gallium nitride substrate processing method of claim 1, wherein the dry etch process comprises a reactive ion etch process.
7. The homoepitaxial gallium nitride substrate processing method of claim 1, wherein after the dry etching process, the gallium nitride substrate is subjected to a wet etching process.
8. A gallium nitride substrate, characterized in that it is obtained by processing according to the method of any one of claims 1 to 7.
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