CN110783333B - Integrated circuit device including latches with cross-coupled structures - Google Patents

Integrated circuit device including latches with cross-coupled structures Download PDF

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Publication number
CN110783333B
CN110783333B CN201910669988.3A CN201910669988A CN110783333B CN 110783333 B CN110783333 B CN 110783333B CN 201910669988 A CN201910669988 A CN 201910669988A CN 110783333 B CN110783333 B CN 110783333B
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field effect
effect transistor
vertical field
region
substrate
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CN110783333A (en
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都桢湖
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from US16/406,305 external-priority patent/US11282957B2/en
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    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
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    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

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Abstract

An integrated circuit device is provided. The device may include a substrate including a first region, a second region, and a boundary region between the first region and the second region. The first region and the second region may be spaced apart from each other in a first horizontal direction. The device may further include a first latch located on the first region, a second latch located on the second region, and a conductive layer extending in the first horizontal direction and crossing the boundary region. The first latch may include a first Vertical Field Effect Transistor (VFET), a second VFET, a third VFET, and a fourth VFET. The second latch may include a fifth VFET, a sixth VFET, a seventh VFET, and an eighth VFET. The first and seventh VFETs may be arranged along the first horizontal direction. Portions of the conductive layer may include a gate electrode of the first VFET and a gate electrode of the seventh VFET, respectively.

Description

Integrated circuit device including latches with cross-coupled structures
Cross Reference to Related Applications
The present application claims priority from U.S. provisional patent application serial No. 62/702,415 filed by the U.S. patent and trademark office at 24, 7, 2018 and U.S. patent application serial No. 16/406,305 filed by the U.S. patent and trademark office at 8, 5, 2019, the disclosures of which are incorporated herein by reference in their entirety.
Technical Field
The present disclosure relates generally to the field of electronics, and more particularly, to Vertical Field Effect Transistor (VFET) devices.
Background
Due to the high scalability of Vertical Field Effect Transistor (VFET) devices, research has been conducted on VFETs. Furthermore, the interconnection between VFETs may be simpler than the interconnection between planar transistors.
Disclosure of Invention
According to some embodiments of the inventive concept, an integrated circuit device may include a substrate including a first region, a second region, and a boundary region between the first region and the second region. The first region and the second region may be spaced apart from each other in a first horizontal direction parallel to an upper surface of the substrate. The integrated circuit device may further include a first latch located on the first region of the substrate, a second latch located on the second region of the substrate, and a conductive layer extending in the first horizontal direction and crossing the boundary region. The first latch may include a first Vertical Field Effect Transistor (VFET), a second VFET, a third VFET, and a fourth VFET. The second latch may include a fifth VFET, a sixth VFET, a seventh VFET, and an eighth VFET, and the first VFET and the seventh VFET may be arranged along the first horizontal direction. The first portion of the conductive layer may include a gate electrode of the first VFET and the second portion of the conductive layer may include a gate electrode of the seventh VFET.
According to some embodiments of the inventive concept, an integrated circuit device may include a substrate including a first region, a second region, and a boundary region between the first region and the second region. The first region and the second region may be spaced apart from each other in a first horizontal direction parallel to an upper surface of the substrate. The integrated circuit device may further include a first latch located on the first region of the substrate and a second latch located on the second region of the substrate. The first latch may include a first Vertical Field Effect Transistor (VFET), a second VFET, a third VFET, and a fourth VFET, and the second latch may include a fifth VFET, a sixth VFET, a seventh VFET, and an eighth VFET. The second, third, fifth, and eighth VFETs may be arranged along the first horizontal direction, and the second, third, fifth, and eighth VFETs may be configured to share gate signals applied to gate electrodes of the second, third, fifth, and eighth VFETs.
According to some embodiments of the inventive concept, an integrated circuit device may include a substrate including a first region, a second region, and a boundary region between the first region and the second region. The first region and the second region may be spaced apart from each other in a first horizontal direction parallel to an upper surface of the substrate. The first region of the substrate may include an NMOS region and a PMOS region spaced apart from the NMOS region in the first horizontal direction. The integrated circuit device may further include a first latch located on the first region of the substrate. The first latch may include a first Vertical Field Effect Transistor (VFET) and a third VFET on the PMOS region and a second VFET and a fourth VFET on the NMOS region, and the first VFET may include a first channel region and a first top source/drain sequentially stacked on the substrate, the second VFET may include a second channel region and a second top source/drain sequentially stacked on the substrate, the third VFET may include a third channel region and a third top source/drain sequentially stacked on the substrate, and the fourth VFET may include a fourth channel region and a fourth top source/drain sequentially stacked on the substrate. The integrated circuit device may further include a second latch located on the second region of the substrate and a top source/drain contact. The second latch may include a fifth VFET, a sixth VFET, a seventh VFET, and an eighth VFET. The top source/drain contact may be in contact with the first top source/drain, the second top source/drain, the third top source/drain, and the fourth top source/drain.
Drawings
Fig. 1 is a circuit diagram of a device including a master latch and a slave latch.
Fig. 2 is an arrangement of transistors included in the master latch and slave latch shown in fig. 1 according to some embodiments of the inventive concept.
Fig. 3A, 3B, 3C, and 3D illustrate layouts of devices according to some embodiments of the inventive concept.
Fig. 4 is a layout with a line along which a cross-sectional view is taken.
Fig. 5A, 5B, and 5C are cross-sectional views taken along lines A-A ', B-B ', and C-C ' of fig. 4, respectively, according to some embodiments of the inventive concept.
Fig. 6A, 6B, 6C, 6D, 6E, 6F, 6G, and 6H are cross-sectional views taken along lines 1-1', 2-2', 3-3', 4-4', 5-5', 6-6', 7-7', and 8-8', respectively, of fig. 4, according to some embodiments of the inventive concept.
Detailed Description
Example embodiments are described below with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the spirit and teachings of the disclosure, and thus the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout.
Example embodiments of the inventive concepts are described herein with reference to cross-sectional or top views as schematic illustrations of idealized embodiments and intermediate structures of the example embodiments. Thus, variations in the shape of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Therefore, example embodiments of the inventive concepts should not be construed as limited to the particular shapes illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.
Fig. 1 is a circuit diagram of a device including a master latch and a slave latch. The master latch and the slave latch each have a cross-coupling structure. The device shown in fig. 1 may be part of a flip-flop circuit. In some embodiments, the device shown in fig. 1 may be part of a scan flip-flop circuit, but the inventive concept is not so limited. The device shown in fig. 1 may be part of a different type of flip-flop circuit.
Referring to fig. 1, the first, second, third and fourth transistors TR1, TR2, TR3 and TR4 of the master latch form a first cross-coupling structure, and the fifth, sixth, seventh and eighth transistors TR5, TR6, TR7 and TR8 of the slave latch form a second cross-coupling structure. The types and numbers of transistors between VDD and one of the first transistor TR1, the third transistor TR3, the fifth transistor TR5, and the seventh transistor TR7, and the types and numbers of transistors between VSS and one of the second transistor TR2, the fourth transistor TR4, the sixth transistor TR6, and the eighth transistor TR8 may vary according to the types of flip-flop circuits including the master latch and the slave latch. Further, the first feedback loop FL1 and the second feedback loop FL2 may include various types and numbers of transistors according to the type of the flip-flop circuit.
In some embodiments, the first, third, fifth and seventh transistors TR1, TR3, TR5 and TR7 may be P-type transistors, and the second, fourth, sixth and eighth transistors TR2, TR4, TR6 and TR8 may be N-type transistors, as shown in fig. 1.
According to fig. 1, a clock signal (CLK) may be applied to a plurality of transistors (e.g., the second transistor TR2, the third transistor TR3, the fifth transistor TR5, and the eighth transistor TR 8), and an inverted clock signal (/ CLK) may be applied to a plurality of transistors (e.g., the first transistor TR1, the fourth transistor TR4, the sixth transistor TR6, and the seventh transistor TR 7). It should be appreciated that in some embodiments, the clock signal (CLK) may be applied to the first, fourth, sixth and seventh transistors TR1, TR4, TR6 and TR7, and the inverted clock signal (/ CLK) may be applied to the second, third, fifth and eighth transistors TR2, TR3, TR5 and TR8.
Because the clock signal (CLK) and the inverted clock signal (/ CLK) are each shared by a plurality of transistors, a single wire (e.g., conductive layer 220 in fig. 3B) to which one of the clock signal (CLK) and the inverted clock signal (/ CLK) is applied may be shared by a plurality of transistors. It should be appreciated that sharing a single wire by multiple transistors may reduce the total number of wires included in the device, so sharing a single wire may simplify the layout of the device and may reduce the amount of conductive material used to form the device.
Fig. 2 illustrates an arrangement of transistors included in the master latch and the slave latch illustrated in fig. 1 according to some embodiments of the inventive concept. The master latch including the first transistor TR1, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4 may be disposed on a first latch region (i.e., a master latch region), and the slave latch including the fifth transistor TR5, the sixth transistor TR6, the seventh transistor TR7, and the eighth transistor TR8 may be disposed on a second latch region (i.e., a slave latch region). To provide a shared conductor for the plurality of transistors, the master latch region and the slave latch region may be arranged along a first horizontal direction (e.g., X-direction in fig. 2), and the master latch and the slave latch may form a dual height structure, as shown in fig. 2. It should be understood that the term "height" in the "dual height structure" does not mean that the master latch region and the slave latch region are stacked in a vertical direction. The master latch region and the slave latch region may be spaced apart from each other in the first horizontal direction, and the boundary region may be disposed between the master latch region and the slave latch region.
It should be understood that "element a and element B are disposed along direction X" (or similar language) may mean that element a and element B are spaced apart from each other in direction X and aligned along direction X.
The master latch region may include a first NMOS region NR1 and a first PMOS region PR1 located between the first NMOS region NR1 and the boundary region. The P-type transistors (i.e., the first transistor TR1 and the third transistor TR 3) of the main latch may be disposed on the first PMOS region PR1, and the N-type transistors (i.e., the second transistor TR2 and the fourth transistor TR 4) of the main latch may be disposed on the first NMOS region NR 1. As shown in fig. 2, the first transistor TR1 and the third transistor TR3 may be spaced apart from each other in a second horizontal direction (e.g., Y direction in fig. 2), and may be arranged along the second horizontal direction. The second transistor TR2 and the fourth transistor TR4 may be spaced apart from each other in the second horizontal direction, and may be arranged along the second horizontal direction. In some embodiments, the first horizontal direction is perpendicular to the second horizontal direction.
The slave latch region may include a second NMOS region NR2 and a second PMOS region PR2 located between the second NMOS region NR2 and the boundary region. The P-type transistors (i.e., the fifth transistor TR5 and the seventh transistor TR 7) of the slave latch may be disposed on the second PMOS region PR2, and the N-type transistors (i.e., the sixth transistor TR6 and the eighth transistor TR 8) of the slave latch may be disposed on the second NMOS region NR 2.
Referring to fig. 2, the first transistor TR1 of the master latch to which the inverted clock signal (/ CLK) is applied and the seventh transistor TR7 of the slave latch to which the inverted clock signal (/ CLK) is applied may be disposed on a first imaginary line il_1 and may be spaced apart from each other in a first horizontal direction. The first transistor TR1 and the seventh transistor TR7 may be disposed at positions where the first imaginary line il_1 intersects the first PMOS region PR1 and the second PMOS region PR2, respectively. Accordingly, a single conductive layer (e.g., conductive layer 220 in fig. 3B) extending in the first horizontal direction and receiving the inverted clock signal (/ CLK) may be shared by the first transistor TR1 and the seventh transistor TR 7. The first transistor TR1 and the seventh transistor TR7 may share a gate signal (e.g., an inverted clock signal (/ CLK)).
Still referring to fig. 2, the second and third transistors TR2 and TR3 of the master latch to which the clock signal (CLK) is applied and the fifth and eighth transistors TR5 and TR8 of the slave latch to which the clock signal (CLK) is applied may be on the second imaginary line il_2 and may be spaced apart from each other in the first horizontal direction. The second transistor TR2, the third transistor TR3, the fifth transistor TR5, and the eighth transistor TR8 may be disposed at positions where the second imaginary line il_2 intersects the first NMOS region NR1, the first PMOS region PR1, the second PMOS region PR2, and the second NMOS region NR2, respectively. Accordingly, a single conductive layer (e.g., conductive layer 220 in fig. 3B) extending in the first horizontal direction and receiving the clock signal (CLK) may be shared by the second transistor TR2, the third transistor TR3, the fifth transistor TR5, and the eighth transistor TR 8. The second transistor TR2, the third transistor TR3, the fifth transistor TR5, and the eighth transistor TR8 may share a gate signal (e.g., a clock signal (CLK)).
Thus, it should be appreciated that the dual height structure may enable transistors included in different latches (i.e., master and slave latches) to share a conductive layer through which one of a clock signal (CLK) or an inverted clock signal (/ CLK) is applied, thereby sharing a gate signal.
According to fig. 2, the fourth transistor TR4 of the master latch to which the inverted clock signal (/ CLK) is applied and the sixth transistor TR6 of the slave latch to which the inverted clock signal (/ CLK) is applied may be arranged on the third imaginary line il_3 and may be spaced apart from each other in the first horizontal direction. The fourth transistor TR4 and the sixth transistor TR6 may be disposed at positions where the third imaginary line il_3 intersects the first NMOS region NR1 and the second NMOS region NR2, respectively.
In some embodiments, the device may include a dummy region DR that does not provide a transistor. As shown in fig. 2, the device may include two dummy regions DR respectively located at positions where the first imaginary line il_1 respectively intersects the first NMOS region NR1 and the second NMOS region NR 2. As shown in fig. 2, the device may further include two dummy regions DR at positions where the third imaginary line il_3 intersects the first and second PMOS regions PR1 and PR2, respectively.
In some embodiments, the first, second, and third imaginary lines may extend in a first horizontal direction and may be spaced apart from each other in a second horizontal direction parallel to the upper surface of the substrate and perpendicular to the first horizontal direction, as shown in fig. 2. The second imaginary line may be between the first imaginary line and the third imaginary line. It should be appreciated that the first, second, and third notional lines may correspond to the first, second, and third columns, respectively.
It will be appreciated that the use of vertical field effect transistors may further simplify the layout of the device. The VFET includes a vertical channel protruding from the substrate in a vertical direction (e.g., a direction perpendicular to the upper or lower surface of the substrate) and a top source/drain overlying the vertical channel. Since the top source/drain is the uppermost portion of the VFET, the top source/drain of the VFET and the top source/drain of an adjacent VFET may be connected by a horizontal conductive pattern on the top source/drain.
Fig. 3A, 3B, 3C, and 3D illustrate layouts of devices according to some embodiments of the inventive concept. To simplify the drawing, fig. 3A through 3D each show a set of some elements, but not all elements of the device.
Referring to fig. 3A, a substrate (e.g., substrate 100 in fig. 5A) may include a master latch region, a slave latch region spaced apart from the master latch region in a first horizontal direction (e.g., X-direction), and a boundary region between the master latch region and the slave latch region. The first horizontal direction may be parallel to the upper surface or the lower surface of the substrate. Each transistor of the master latch and the slave latch may be a VFET and may include a vertical channel. The first, second, third, fourth, fifth, sixth, seventh, and eighth transistors TR1, TR2, TR3, TR4, TR5, TR6, TR7, and TR8 may include first, second, third, fourth, fifth, sixth, seventh, and eighth vertical channels VC1, VC2, VC3, VC4, VC5, VC6, VC7, and VC8, respectively.
A bottom source/drain 140 may surround each transistor and an isolation region 120 may be disposed between the bottom source/drains 140. The bottom source/drain contacts 160 may extend lengthwise in a second horizontal direction (e.g., the Y-direction). In some embodiments, the second horizontal direction may be parallel to the upper or lower surface of the substrate, and may be perpendicular to the first horizontal direction.
Referring to fig. 3B, each of the conductive layers 220 may extend lengthwise in the first horizontal direction. One of the conductive layers 220 may be shared by the first vertical channel VC1 and the seventh vertical channel VC 7. The conductive layer 220 shared by the first vertical channel VC1 and the seventh vertical channel VC7 includes: a portion surrounding the first vertical channel VC1 and may constitute a gate electrode of the first transistor TR 1; and a portion surrounding the seventh vertical channel VC7 and may constitute a gate electrode of the seventh transistor TR 7.
In some embodiments, one of the conductive layers 220 may be shared by the second vertical channel VC2, the third vertical channel VC3, the fifth vertical channel VC5, and the eighth vertical channel VC 8. The conductive layer 220 shared by the second, third, fifth, and eighth vertical channels VC2, VC3, VC5, and VC8 includes portions surrounding the second, third, fifth, and eighth vertical channels VC2, VC3, VC5, and VC8, respectively. Each surrounding portion of the conductive layer 220 may constitute a gate electrode of one of the second transistor TR2, the third transistor TR3, the fifth transistor TR5, and the eighth transistor TR 8. The two conductive layers 220 may surround the fourth vertical channel VC4 and the sixth vertical channel VC6, respectively, and may constitute a gate electrode of the fourth transistor TR4 and a gate electrode of the sixth transistor TR6, respectively.
The conductive layer 220 shared by the first vertical channel VC1 and the seventh vertical channel VC7 may include a pad region 220P, the pad region 220P extending in the first horizontal direction from a portion surrounding the seventh vertical channel VC7 and being located on the slave latch region. The conductive layer 220 shared by the second, third, fifth, and eighth vertical channels VC2, VC3, VC5, and VC8 may include a pad region 220P located on the boundary region. The gate contacts 240 may overlap the pad regions 220P and may be connected to the pad regions 220P to electrically connect the conductive layers 220 to conductive lines (e.g., 340 in fig. 3C), respectively. The gate contact 240 may overlap the conductive layer 220 surrounding the fourth and sixth vertical channels VC4 and VC6 and may be connected to the conductive layer 220 surrounding the fourth and sixth vertical channels VC4 and VC6, as shown in fig. 3B.
Referring to fig. 3C, in some embodiments, via contacts 320 may be disposed on gate contacts 240, respectively. Each via contact 320 may connect one of the gate contacts 240 to a corresponding wire 340.
Referring to fig. 3D, a top source/drain contact 260 overlapping the first, second, third, and fourth vertical channels VC1, VC2, VC3, and VC4 may be provided, and a top source/drain contact 260 overlapping the fifth, sixth, seventh, and eighth vertical channels VC5, VC6, VC7, and VC8 may be provided. On the main latch area, via contacts 320 may be provided on top source/drain contacts 260 to connect top source/drain contacts 260 to conductive lines 340. On the slave latch region, a single via contact 320 may be provided on the top source/drain contact 260 to connect the top source/drain contact 260 to the wire 340.
Fig. 4 is a layout with a line along which a cross-sectional view is taken. Fig. 5A, 5B, and 5C are cross-sectional views taken along lines A-A ', B-B ', and C-C ', respectively, of fig. 4, according to some embodiments of the inventive concept. Fig. 6A, 6B, 6C, 6D, 6E, 6F, 6G, and 6H are cross-sectional views taken along lines 1-1', 2-2', 3-3', 4-4', 5-5', 6-6', 7-7', and 8-8', respectively, of fig. 4, according to some embodiments of the inventive concept.
It should be appreciated that the cross-sectional view taken along line 9-9 'is the same or similar to the cross-sectional view taken along line 1-1'.
Referring to fig. 5A, the substrate 100 may include a master latch region, a slave latch region, and a boundary region between the master latch region and the slave latch region. The master latch region may be spaced apart from the slave latch region in a first horizontal direction. The master latch may be disposed on a master latch region of the substrate 100 and the slave latch may be disposed on a slave latch region of the substrate 100. The first transistor TR1 includes a first vertical channel VC1 protruding from the upper surface of the substrate 100 and a top source/drain 150 located on the first vertical channel VC 1. The bottom source/drain 140 may be on the substrate 100 and may surround a lower portion of the first vertical channel VC 1. In some embodiments, the bottom source/drain 140 may be formed by an epitaxial growth process, and the bottom source/drain 140 may be referred to as a bottom epitaxial layer. The seventh VFET may have a structure similar to the first VFET, as shown in fig. 5A.
Isolation regions 120 may be disposed between adjacent bottom source/drains 140 to electrically insulate the bottom source/drains 140 from each other. In some embodiments, the isolation region 120 may be formed by a shallow trench isolation process, and the isolation region 120 may be referred to as an STI region.
The conductive layer 220 may surround the vertical channel VC1 and may extend toward the seventh vertical channel VC 7. As shown in fig. 5A, the conductive layer 220 may span (e.g., extend continuously across) a boundary region of the substrate 100. Spacers 280 may be on the lower surface and/or upper surface of conductive layer 220 to electrically insulate conductive layer 220 from bottom source/drain 140. As shown in fig. 5A, the spacer 280 may expose the pad region 220P of the conductive layer 220. The spacers 280 may comprise an insulating material (e.g., silicon oxide).
The top source/drain contacts 260 may contact the top source/drains 150 of the first and seventh VFETs, respectively, as shown in fig. 5A. Referring back to fig. 3D, the top source/drain contact 260 of the master latch may contact the top source/drains 150 of the first, second, third, and fourth transistors TR1, TR2, TR3, and TR4, and the top source/drain contact 260 of the slave latch may contact the top source/drains 150 of the fifth, sixth, seventh, and eighth transistors TR5, TR6, TR7, and TR 8. (see FIGS. 6B and 6C). In some embodiments, the top source/drain contact 260 of the master latch may be electrically connected to wire 340 through via contact 320 located between top source/drain contact 260 and wire 340, as shown in fig. 5A.
The gate contact 240 may be disposed in the insulating layer 420 and may extend in a vertical direction (e.g., a Z-direction) perpendicular to the upper surface of the substrate 100. Signals (e.g., a clock signal and an inverted clock signal) may be applied to the conductive layer 220 through the gate contact 240. As shown in fig. 5A, gate contact 240 may be electrically connected to wire 340 through via contact 320 located between gate contact 240 and wire 340. Bottom source/drain contacts 160 may be disposed on the isolation regions 120.
Referring to fig. 3B and 5B, the conductive layer 220 may extend lengthwise in the first horizontal direction and may span the boundary region of the substrate 100. As shown in fig. 5B, the conductive layer 220 may include portions surrounding the second, third, fifth, and eighth vertical channels VC2, VC3, VC5, and VC8, and each surrounding portion of the conductive layer 220 may constitute a gate (e.g., a gate electrode) of one of the second, third, fifth, and eighth transistors TR2, TR3, TR5, and TR 8. The conductive layer 220 may include a pad region 220P on a boundary region of the substrate 100 to which the gate contact 240 is connected. The gate contact 240 may extend in a vertical direction and may be electrically connected to the wire 340 through the via contact 320 located between the gate contact 240 and the wire 340.
Referring to fig. 5B, top source/drain electrodes 150 of the second, third, fifth and eighth transistors TR2, TR3, TR5 and TR8 are disposed on the second, third, fifth and eighth vertical channels VC2, VC3, VC5 and VC8, respectively. In some embodiments, the top source/drain contacts 260 on the master latch region may contact the top source/drains 150 of the second transistor TR2 and the third transistor TR3, and the top source/drain contacts 260 on the slave latch region may contact the top source/drains 150 of the fifth transistor TR5 and the eighth transistor TR 8. The top source/drain contact 260 on the slave latch region may be electrically connected to wire 340 through via contact 320 located between top source/drain contact 260 and wire 340.
Referring to fig. 5C, the conductive layers 220 may be spaced apart from each other in the first horizontal direction and may surround the fourth and sixth vertical channels VC4 and VC6, respectively. Conductive layer 220 may be electrically connected to each other through gate contact 240, via contact 320, and conductive line 340. The spacer 280 may not be disposed on a portion of the conductive layer 220 connected to the gate contact 240.
Referring to fig. 5A and 5C, the dummy region DR is a portion of the substrate 100 on which a vertical channel is not formed.
Referring to fig. 6A, bottom source/drain contacts 160 may be disposed on the isolation regions 120 and may extend lengthwise in the second horizontal direction.
Referring to fig. 6B, the sixth vertical channel VC6 and the eighth vertical channel VC8 may be spaced apart from each other in the second horizontal direction, and the top source/drain 150 may be disposed on the sixth vertical channel VC6 and the eighth vertical channel VC8, respectively. In some embodiments, the top source/drain contact 260 may contact the top source/drains 150 of the sixth transistor TR6 and the eighth transistor TR 8.
Referring to fig. 6C, a conductive layer 220 may be disposed on the isolation region 120, the isolation region 120 extending between the NMOS region and the PMOS region of the slave latch region. The pad region 220P of the conductive layer 220 may be electrically connected to the conductive line 340 through the gate contact 240 and the via contact 320. The top source/drain contacts 260 may be electrically connected to the conductive lines 340 by via contacts 320. Conductive layer 220 may be electrically connected to conductive line 340 through gate contact 240 and via contact 320.
Referring to fig. 6D, the fifth and seventh vertical channels VC5 and VC7 may be spaced apart from each other in the second horizontal direction, and the top source/drain 150 may be disposed on the fifth and seventh vertical channels VC5 and VC7, respectively. In some embodiments, the top source/drain contact 260 may contact the top source/drains 150 of the fifth transistor TR5 and the seventh transistor TR 7.
Referring to fig. 6E, a conductive layer 220 may be disposed on the isolation region 120 on the boundary region. The pad region 220P of the conductive layer 220 on the boundary region may be electrically connected to the conductive line 340 through the gate contact 240 and the via contact 320.
Referring to fig. 6F, the first and third vertical channels VC1 and VC3 may be spaced apart from each other in the second horizontal direction, and the top source/drain 150 may be disposed on the first and third vertical channels VC1 and VC3, respectively. In some embodiments, the top source/drain contact 260 may contact the top source/drain 150 of the first transistor TR1 and the third transistor TR 3. Via contacts 320 may be disposed on top source/drain contacts 260 to connect top source/drain contacts 260 to conductive lines 340.
Referring to fig. 6G, the conductive layer 220 may be disposed on the isolation region 120, and the isolation region 120 extends between the first NMOS region NR1 and the first PMOS region PR1 of the main latch region. Conductive layer 220 surrounding fourth vertical channel VC4 and extending from fourth vertical channel VC4 may be electrically connected to conductive line 340 through gate contact 240 and via contact 320.
Referring to fig. 6H, the second and fourth vertical channels VC2 and VC4 may be spaced apart from each other in the second horizontal direction, and the top source/drain 150 may be disposed on the second and fourth vertical channels VC2 and VC4, respectively. In some embodiments, the top source/drain contact 260 may contact the top source/drains 150 of the second transistor TR2 and the fourth transistor TR 4.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof.
It should be understood that references herein to "element a vertically overlapping element B" (or similar language) mean that there is a vertical line intersecting both element a and element B.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element could be termed a second element without departing from the teachings of the present inventive concept.
The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present inventive concept. Thus, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims (20)

1. An integrated circuit device, the integrated circuit device comprising:
a substrate comprising a first region, a second region, and a boundary region between the first region and the second region, wherein the first region and the second region are spaced apart from each other in a first horizontal direction parallel to an upper surface of the substrate;
a first latch located on the first region of the substrate, wherein the first latch includes a first vertical field effect transistor, a second vertical field effect transistor, a third vertical field effect transistor, and a fourth vertical field effect transistor;
a second latch located on the second region of the substrate, wherein the second latch includes a fifth vertical field effect transistor, a sixth vertical field effect transistor, a seventh vertical field effect transistor, and an eighth vertical field effect transistor, wherein the first vertical field effect transistor and the seventh vertical field effect transistor are arranged along the first horizontal direction; and
A conductive layer extending in the first horizontal direction and crossing the boundary region, wherein a first portion of the conductive layer includes a gate electrode of the first vertical field effect transistor and a second portion of the conductive layer includes a gate electrode of the seventh vertical field effect transistor.
2. The integrated circuit device of claim 1, wherein the conductive layer is configured to receive a clock signal or an inverted clock signal.
3. The integrated circuit device of claim 2, wherein the conductive layer includes a pad region protruding from the second portion of the conductive layer and located on the second region of the substrate, and
Wherein the integrated circuit device further comprises a gate contact extending in a vertical direction perpendicular to the upper surface of the substrate and connected to the pad region of the conductive layer.
4. The integrated circuit device of claim 3, wherein the first vertical field effect transistor and the seventh vertical field effect transistor are both P-type vertical field effect transistors, and
Wherein the conductive layer is configured to receive the inverted clock signal.
5. The integrated circuit device of claim 2, wherein the conductive layer includes a pad region located on the border region, and
Wherein the integrated circuit device further comprises a gate contact extending in a vertical direction perpendicular to the upper surface of the substrate and connected to the pad region of the conductive layer.
6. The integrated circuit device of claim 1, wherein the first vertical field effect transistor comprises a first channel region and a first top source/drain sequentially stacked on the substrate, the second vertical field effect transistor comprises a second channel region and a second top source/drain sequentially stacked on the substrate, the third vertical field effect transistor comprises a third channel region and a third top source/drain sequentially stacked on the substrate, and the fourth vertical field effect transistor comprises a fourth channel region and a fourth top source/drain sequentially stacked on the substrate, and
Wherein the integrated circuit device further comprises top source/drain contacts contacting the first top source/drain, the second top source/drain, the third top source/drain, and the fourth top source/drain.
7. The integrated circuit device of claim 6, wherein the first region of the substrate comprises an NMOS region and a PMOS region between the NMOS region and the border region,
Wherein the first vertical field effect transistor and the third vertical field effect transistor are both P-type vertical field effect transistors, and the first vertical field effect transistor and the third vertical field effect transistor are located on the PMOS region and arranged along a second horizontal direction parallel to the upper surface of the substrate and perpendicular to the first horizontal direction, and
Wherein the second vertical field effect transistor and the fourth vertical field effect transistor are both N-type vertical field effect transistors, and the second vertical field effect transistor and the fourth vertical field effect transistor are located on the NMOS region and arranged along the second horizontal direction.
8. The integrated circuit device of claim 7, wherein the second vertical field effect transistor and the third vertical field effect transistor are arranged along the first horizontal direction.
9. An integrated circuit device, the integrated circuit device comprising:
a substrate comprising a first region, a second region, and a boundary region between the first region and the second region, wherein the first region and the second region are spaced apart from each other in a first horizontal direction parallel to an upper surface of the substrate;
a first latch located on the first region of the substrate and comprising a first vertical field effect transistor, a second vertical field effect transistor, a third vertical field effect transistor, and a fourth vertical field effect transistor; and
A second latch located on the second region of the substrate and including a fifth vertical field effect transistor, a sixth vertical field effect transistor, a seventh vertical field effect transistor, and an eighth vertical field effect transistor,
Wherein the second vertical field effect transistor, the third vertical field effect transistor, the fifth vertical field effect transistor, and the eighth vertical field effect transistor are arranged along the first horizontal direction, and
Wherein the second vertical field effect transistor, the third vertical field effect transistor, the fifth vertical field effect transistor, and the eighth vertical field effect transistor are configured to share a gate signal applied to a gate electrode of the second vertical field effect transistor, a gate electrode of the third vertical field effect transistor, a gate electrode of the fifth vertical field effect transistor, and a gate electrode of the eighth vertical field effect transistor.
10. The integrated circuit device of claim 9, wherein the gate signal is a clock signal or an inverted clock signal.
11. The integrated circuit device of claim 9, further comprising a conductive layer extending in the first horizontal direction and across the border region,
Wherein a first portion of the conductive layer includes the gate electrode of the second vertical field effect transistor, a second portion of the conductive layer includes the gate electrode of the third vertical field effect transistor, a third portion of the conductive layer includes the gate electrode of the fifth vertical field effect transistor, and a fourth portion of the conductive layer includes the gate electrode of the eighth vertical field effect transistor.
12. The integrated circuit device of claim 11, wherein the conductive layer includes a pad region located on the border region, and
Wherein the integrated circuit device further comprises a gate contact extending in a vertical direction perpendicular to the upper surface of the substrate and connected to the pad region of the conductive layer.
13. The integrated circuit device of claim 11, wherein the first vertical field effect transistor comprises a first channel region and a first top source/drain sequentially stacked on the substrate, the second vertical field effect transistor comprises a second channel region and a second top source/drain sequentially stacked on the substrate, the third vertical field effect transistor comprises a third channel region and a third top source/drain sequentially stacked on the substrate, and the fourth vertical field effect transistor comprises a fourth channel region and a fourth top source/drain sequentially stacked on the substrate, and
Wherein the integrated circuit device further comprises top source/drain contacts contacting the first top source/drain, the second top source/drain, the third top source/drain, and the fourth top source/drain.
14. The integrated circuit device of claim 13, wherein the first top source/drain is located between the substrate and the top source/drain contact.
15. The integrated circuit device of claim 13, wherein the first region of the substrate comprises an NMOS region and a PMOS region between the NMOS region and the border region,
Wherein the first vertical field effect transistor and the third vertical field effect transistor are located on the PMOS region and are arranged along a second horizontal direction parallel to the upper surface of the substrate and perpendicular to the first horizontal direction, and
Wherein the second vertical field effect transistor and the fourth vertical field effect transistor are located on the NMOS region and are arranged along the second horizontal direction.
16. An integrated circuit device, the integrated circuit device comprising:
a substrate comprising a first region, a second region, and a boundary region between the first region and the second region, wherein the first region and the second region are spaced apart from each other in a first horizontal direction parallel to an upper surface of the substrate, wherein the first region of the substrate comprises an NMOS region and a PMOS region spaced apart from the NMOS region in the first horizontal direction;
A first latch on the first region of the substrate, wherein the first latch includes first and third vertical field effect transistors on the PMOS region and second and fourth vertical field effect transistors on the NMOS region, wherein the first vertical field effect transistor includes a first channel region and a first top source/drain sequentially stacked on the substrate, the second vertical field effect transistor includes a second channel region and a second top source/drain sequentially stacked on the substrate, the third vertical field effect transistor includes a third channel region and a third top source/drain sequentially stacked on the substrate, and the fourth vertical field effect transistor includes a fourth channel region and a fourth top source/drain sequentially stacked on the substrate;
A second latch located on the second region of the substrate and including a fifth vertical field effect transistor, a sixth vertical field effect transistor, a seventh vertical field effect transistor, and an eighth vertical field effect transistor; and
Top source/drain contacts with the first top source/drain, the second top source/drain, the third top source/drain, and the fourth top source/drain contacts,
Wherein the second vertical field effect transistor, the third vertical field effect transistor, the fifth vertical field effect transistor, and the eighth vertical field effect transistor are configured to share a gate signal.
17. The integrated circuit device of claim 16, wherein the first vertical field effect transistor is located at a first position where a first imaginary line intersects the PMOS region, the second vertical field effect transistor is located at a second position where a second imaginary line intersects the NMOS region, the third vertical field effect transistor is located at a third position where the second imaginary line intersects the PMOS region, and the fourth vertical field effect transistor is located at a fourth position where a third imaginary line intersects the NMOS region,
Wherein the first, second, and third imaginary lines extend in the first horizontal direction and are spaced apart from each other in a second horizontal direction parallel to the upper surface of the substrate and perpendicular to the first horizontal direction, and
Wherein the second imaginary line is between the first imaginary line and the third imaginary line.
18. The integrated circuit device of claim 17, further comprising a conductive layer extending in the first horizontal direction, wherein a first portion of the conductive layer comprises a gate electrode of the second vertical field effect transistor and a second portion of the conductive layer comprises a gate electrode of the third vertical field effect transistor.
19. The integrated circuit device of claim 18, wherein the conductive layer is configured to receive a clock signal or an inverted clock signal.
20. The integrated circuit device of claim 16, wherein the second vertical field effect transistor, the third vertical field effect transistor, the fifth vertical field effect transistor, and the eighth vertical field effect transistor are arranged along the first horizontal direction,
Wherein the integrated circuit device further comprises a conductive layer extending in the first horizontal direction, and
Wherein the first portion of the conductive layer comprises a gate electrode of the second vertical field effect transistor, the second portion of the conductive layer comprises a gate electrode of the third vertical field effect transistor, the third portion of the conductive layer comprises a gate electrode of the fifth vertical field effect transistor, and the fourth portion of the conductive layer comprises a gate electrode of the eighth vertical field effect transistor.
CN201910669988.3A 2018-07-24 2019-07-23 Integrated circuit device including latches with cross-coupled structures Active CN110783333B (en)

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US16/406,305 US11282957B2 (en) 2018-07-24 2019-05-08 Vertical field-effect transistor (VFET) devices including latches having cross-couple structure

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