CN110767782A - High-brightness light-emitting diode epitaxial wafer and preparation method thereof - Google Patents
High-brightness light-emitting diode epitaxial wafer and preparation method thereof Download PDFInfo
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- CN110767782A CN110767782A CN201810833970.8A CN201810833970A CN110767782A CN 110767782 A CN110767782 A CN 110767782A CN 201810833970 A CN201810833970 A CN 201810833970A CN 110767782 A CN110767782 A CN 110767782A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
Abstract
The invention discloses a high-brightness light-emitting diode epitaxial wafer which comprises a substrate, a buffer layer, a non-doped gallium nitride layer, an N-type layer, a quantum well layer and a P-type layer, wherein the buffer layer, the non-doped gallium nitride layer, the N-type layer, the quantum well layer and the P-type layer are sequentially grown along the surface of the substrate, the buffer layer comprises a first gallium nitride layer and a second gallium nitride layer which are alternately grown, the first layer and the last layer of the buffer layer are both the first gallium nitride layer, the growth temperature of the first gallium nitride layer is lower than that of the second gallium nitride layer, the growth of the P-type layer comprises at least 2 growth stages, and each growth stage comprises the processes of high-temperature growth, annealing. The buffer layer of the high-brightness light-emitting diode epitaxial wafer avoids non-radiative recombination luminescence, improves the mobility of holes of the P-type layer, increases the probability of recombination of the holes in the P-type layer and electrons generated by the N-type layer, and improves the luminous efficiency and the antistatic capability of the light-emitting diode through the synergistic effect of the buffer layer and the P-type layer.
Description
Technical Field
The invention relates to the technical field of semiconductor optoelectronic device equipment, in particular to a high-brightness light-emitting diode epitaxial wafer and a preparation method thereof.
Background
In recent years, the application field of the light emitting diode is becoming wide, the market demand is expanding, and the light emitting diode is widely applied to the fields of displays, television lighting decoration and illumination. The epitaxial wafer in the led is a core part of the led, and therefore, the development of the epitaxial wafer of the led is receiving much attention.
In the conventional light emitting diode manufacturing process, an N-type nitride layer, a P-type nitride layer, and a quantum well layer interposed therebetween are manufactured on a semiconductor substrate, and after the N-type nitride layer is etched and leaked by an etching process, a first region is formed, an N electrode is formed on the first region, the surface of the P-type nitride layer is a second region, and a P electrode is formed on the second region. When the light-emitting diode is electrified, electrons in the N-type nitride layer and holes in the P-type nitride layer are combined in the quantum well layer to emit visible light, and the light-emitting diode emits light.
In the prior art, the preparation process of the epitaxial wafer has a plurality of defects, so that the light-emitting diode has low light-emitting efficiency and poor antistatic capability, and cannot well meet the use requirement.
Disclosure of Invention
The invention aims to solve the technical problem of providing a high-brightness light-emitting diode epitaxial wafer and a preparation method thereof, which can solve the problems of low light-emitting efficiency and poor antistatic capability of a light-emitting diode in the prior art.
In order to solve the problems, the invention adopts the following technical scheme:
the invention provides a high-brightness light-emitting diode epitaxial wafer, which comprises a substrate, and a buffer layer, a non-doped gallium nitride layer, an N-type layer, a quantum well layer and a P-type layer which are sequentially grown along the surface of the substrate, wherein the buffer layer comprises a first gallium nitride layer and a second gallium nitride layer which are alternately grown, the first layer and the last layer of the buffer layer are both the first gallium nitride layer, the growth temperature of the first gallium nitride layer is lower than that of the second gallium nitride layer, the growth of the P-type layer comprises at least 2 growth stages, and each growth stage comprises the processes of high-temperature growth, annealing cooling and low-temperature growth.
Preferably, the thickness of the second gallium nitride layer is smaller than that of the adjacent first gallium nitride layer.
As a preferred technical solution, the thickness corresponding to each growth stage in the P-type layer is the same.
As a preferred technical solution, the thickness of each growth stage in the P-type layer is different.
In a second aspect of the present invention, a method for preparing a high brightness light emitting diode epitaxial wafer is provided, which includes the following steps:
obtaining a substrate;
growing a buffer layer, a non-doped gallium nitride layer, an N-type layer, a quantum well layer and a P-type layer in sequence along the surface of the substrate;
the buffer layer comprises a first gallium nitride layer and a second gallium nitride layer which alternately grow, the first layer and the last layer of the buffer layer are both first gallium nitride layers, and the growth temperature of the first gallium nitride layers is lower than that of the second gallium nitride layers;
the growth of the P-type layer comprises at least 2 growth stages, and each growth stage comprises the processes of high-temperature growth, annealing and cooling and low-temperature growth.
As a preferred technical solution, the operation steps of each growth phase of the P-type layer are as follows: and obtaining the current growth temperature and growth thickness of the P-type layer, and when the growth thickness reaches a preset value, heating according to a set heating rate or cooling according to a set cooling rate.
As a preferred technical scheme: the heating rate is 60-90 ℃ per minute; the cooling rate is 60-90 ℃ per minute.
According to a preferable technical scheme, the growth temperature of the second gallium nitride layer is 30-115 ℃ higher than that of the first gallium nitride layer adjacent to the second gallium nitride layer.
According to a preferable technical scheme, the growth temperature of the first gallium nitride layer is gradually increased along the growth direction of the epitaxial wafer, and the growth temperature of the second gallium nitride layer is gradually increased along the growth direction of the epitaxial wafer.
Preferably, the buffer layer is doped with aluminum.
The quality of the buffer layer crystal grown under the low-temperature condition is poor, so that a plurality of defects can be generated, the non-doped gallium nitride layer can not play an effective blocking role for the defects generated by the buffer layer, and the defects in the buffer layer crystal can extend to the N-type layer, the quantum well layer and the P-type layer, so that non-radiative composite light emitting is caused, and the light emitting efficiency of the light emitting diode is seriously influenced.
According to the buffer layer, the second gallium nitride layer generated at high temperature is inserted into the first gallium nitride layer generated at low temperature, the crystal quality of the second gallium nitride is high, the overall quality of the buffer layer can be improved, the defects generated by the first gallium nitride layer are prevented from being spread to the N-type layer, the quantum well layer and the P-type layer, the non-radiative composite light emitting is avoided, and the light emitting efficiency of the light emitting diode is improved. The first gallium nitride layer preferentially grows on the substrate, which is beneficial to nucleating gallium nitride seed crystals at low temperature, and the second gallium nitride layer and the first gallium nitride layer are both formed by adopting gallium nitride materials, which is beneficial to forming lattice matching between the buffer layer and the undoped gallium nitride layer.
The P-type layer comprises a plurality of growth stages, each growth stage comprises the processes of high-temperature growth, annealing cooling and low-temperature growth, the cooling annealing can break magnesium-hydrogen bonds in the growth process of the P-type layer, the activation rate of magnesium in the P-type layer is improved, the mobility of holes in the P-type layer is further improved, the probability that the holes in the P-type layer are combined with electrons generated by an N-type layer is increased, the electrons and the holes are combined to radiate more visible light, and the light emitting efficiency and the antistatic capacity of the light emitting diode are further improved.
Compared with the prior art, the buffer layer of the high-brightness light-emitting diode epitaxial wafer avoids non-radiative recombination luminescence, improves the mobility of holes of the P-type layer, increases the probability of recombination of the holes in the P-type layer and electrons generated by the N-type layer, enables the electrons and the holes to radiate more visible light in a recombination mode, and greatly improves the luminous efficiency and the antistatic capacity of the light-emitting diode through the synergistic effect of the buffer layer and the P-type layer.
Drawings
The invention is described in further detail below with reference to specific embodiments and with reference to the following drawings.
FIG. 1 is a flow chart of the preparation of a high-brightness LED epitaxial wafer according to the present invention;
FIG. 2 is a schematic structural diagram of an epitaxial wafer of a high-brightness LED according to the present invention;
FIG. 3 is a schematic structural diagram of a buffer layer in an epitaxial wafer of a high-brightness light-emitting diode according to the present invention;
FIG. 4 is a flow chart of the preparation of a P-type layer in an epitaxial wafer of a high-brightness light-emitting diode according to the present invention;
FIG. 5 is a graph of a first growth curve of a P-type layer in an epitaxial wafer for a high brightness LED of the present invention;
fig. 6 is a second growth graph of a P-type layer in an epitaxial wafer for a high brightness light emitting diode according to the present invention.
Wherein the reference numerals are specified as follows: the substrate comprises a substrate 1, a buffer layer 2, an undoped gallium nitride layer 3, an N-type layer 4, a quantum well layer 5, a P-type layer 6, a first gallium nitride layer 7 and a second gallium nitride layer 8.
Detailed Description
Referring to fig. 1, the present embodiment provides a method for preparing an epitaxial wafer of a high-brightness light emitting diode, including the following steps:
And 2, growing a buffer layer 2, a non-doped gallium nitride layer 3, an N-type layer 4, a quantum well layer 5 and a P-type layer 6 on the surface of the substrate 1 in sequence.
In this embodiment, a metal organic compound chemical vapor deposition apparatus is used to realize growth of an epitaxial wafer, a mixed gas of high-purity hydrogen and high-purity nitrogen is used as a carrier gas, high-purity ammonia is used as a nitrogen source, trimethylgallium is used as gallium, trimethylindium is used as an indium source, trimethylaluminum is used as an aluminum source, silane is used as a dopant for an N-type layer 4, and magnesium chloride is used as a dopant for a P-type layer 6.
The structure of the obtained high-brightness light-emitting diode epitaxial wafer is shown in fig. 2, and comprises a substrate 1, and a buffer layer 2, an undoped gallium nitride layer 3, an N-type layer 4, a quantum well layer 5 and a P-type layer 6 which are sequentially grown along the surface of the substrate 1.
The preparation method of the buffer layer 2 comprises the following steps:
step one, growing a first gallium nitride layer 7 on the surface of the substrate 1 at 550 ℃, wherein the growth rate is 7.2 nanometers per minute, and the thickness is 2.8 nanometers.
And step two, growing a second gallium nitride layer 8 on the surface of the first gallium nitride layer 7 prepared in the step one, wherein the growth temperature is 600 ℃, the growth speed is 200 nanometers/minute, and the thickness is 0.3 nanometers.
And step three, growing a first gallium nitride layer 7 on the surface of the second gallium nitride layer 8 prepared in the step two, wherein the growth temperature is 552 ℃, the growth speed is 8.2 nanometers per minute, and the thickness is 3.0 nanometers.
And step four, growing a second gallium nitride layer 8 on the surface of the first gallium nitride layer 7 prepared in the step three, wherein the growth temperature is 650 ℃, the growth speed is 280 nanometers per minute, and the thickness is 0.25 nanometers.
And step five, growing a first gallium nitride layer 7 on the surface of the second gallium nitride layer 8 prepared in the step four, wherein the growth temperature is 555 ℃, the growth speed is 9.0 nanometers per minute, and the thickness is 3.0 nanometers.
Wherein, aluminum is doped between the adjacent first gallium nitride layer 7 and the second gallium nitride layer 8. The growth process of the buffer layer 2 is performed under a pressure of 400 torr in the reaction chamber. The structure of the buffer layer 2 thus obtained is shown in fig. 3.
The preparation method of the undoped gallium nitride layer 3 is as follows: the temperature of the reaction chamber is controlled to be 1000 ℃, the reaction pressure is 400 torr, the growth rate is 3 microns/hour, and the non-doped gallium nitride layer 3 with the thickness of 3 microns is grown on the surface of the buffer layer 2.
The preparation method of the N-type layer 4 is as follows: the temperature of the reaction chamber is controlled to be 1000 ℃, the reaction pressure is 300 torr, the growth rate is 5 microns/hour, and an N-type layer 4 with the thickness of 2.5 microns grows on the surface of the non-doped gallium nitride layer 3.
The quantum well layer 5 is prepared as follows: the reaction pressure of the reaction chamber is controlled to be 330 torr, and the thickness of the N-type layer 4 is grown to be 33 nanometers.
Referring to fig. 4, a method for preparing the P-type layer 6 includes the following steps:
(1) constant temperature three-stage type.
Referring to fig. 5, the growth of the P-type layer 6 includes 3 growth stages, i.e., S1, S2, and S3, each growth stage includes the processes of high temperature growth, annealing, cooling, and low temperature growth, and the predetermined thickness of each growth stage is 25 nm. The annealing cooling rate in each growth stage is 750 ℃ per minute, and the heating rate of low-temperature growth in the previous growth stage and high-temperature growth in the next growth stage is 750 ℃ per minute. The high-temperature growth temperature T1 of each growth stage is 1000 ℃, the low-temperature growth temperature T2 is 750 ℃, the high-temperature preset growth time is 2 minutes, and the low-temperature preset growth time is 2 minutes. And the annealing temperature reduction of each stage adopts a nitrogen gas temperature reduction method.
(2) Temperature-changing three-section type
Referring to fig. 6, the growth of the P-type layer 6 includes 3 growth stages, i.e., S1, S2, and S3, each of which includes the processes of high temperature growth, annealing, cooling, and low temperature growth, and the predetermined thickness of each growth stage is 25 nm. The annealing cooling rate in each growth stage is 750 ℃ per minute, and the heating rate of low-temperature growth in the previous growth stage and high-temperature growth in the next growth stage is 750 ℃ per minute. In S1, the high-temperature growth temperature T1 is 1000 ℃, the low-temperature growth temperature T2 is 750 ℃, the high-temperature preset growth time is 2 minutes, and the low-temperature preset growth time is 2 minutes. In S2, the high-temperature growth temperature T1 is 1000 ℃, the low-temperature growth temperature T3 is 700 ℃, the high-temperature preset growth time is 2 minutes, and the low-temperature preset growth time is 2 minutes. In S3, the high-temperature growth temperature T1 is 1000 ℃, the low-temperature growth temperature T4 is 650 ℃, the high-temperature preset growth time is 2 minutes, and the low-temperature preset growth time is 2 minutes. And the annealing temperature reduction of each stage adopts a nitrogen gas temperature reduction method.
The preparation of the epitaxial wafer is completed, and by the method, the magnesium-hydrogen bond in the P-type layer 6 in the current growth stage can be disconnected in each growth stage of the P-type layer 6, so that the activation rate of magnesium in the P-type layer 6 grown in the current growth stage is improved, and further the mobility of holes in the P-type layer 6 is improved, namely the number of holes combined with electrons generated by the N-type layer 4 is increased, the visible light radiated by the electrons and the holes in a combined mode is increased, and further the luminous efficiency of the light-emitting diode is improved.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. The utility model provides a high brightness emitting diode epitaxial wafer, its characterized in that includes the substrate, follows buffer layer, non-doping gallium nitride layer, N type layer, quantum well layer and the P type layer that the surface of substrate grows in proper order, the buffer layer includes first gallium nitride layer and the second gallium nitride layer of alternate growth, the first layer and the last layer of buffer layer are first gallium nitride layer, the growth temperature on first gallium nitride layer is less than the growth temperature on second gallium nitride layer, the growth on P type layer includes 2 at least growth stages, every growth stage all includes the process of high temperature growth, annealing cooling and low temperature growth.
2. A high brightness light emitting diode epitaxial wafer as claimed in claim 1, wherein: the thickness of the second gallium nitride layer is smaller than that of the adjacent first gallium nitride layer.
3. A high brightness light emitting diode epitaxial wafer as claimed in claim 1, wherein: the thickness of each growth stage in the P-type layer is the same.
4. A high brightness light emitting diode epitaxial wafer as claimed in claim 1, wherein: the thickness of each growth stage in the P-type layer is different.
5. A preparation method of a high-brightness light-emitting diode epitaxial wafer is characterized by comprising the following steps:
obtaining a substrate;
growing a buffer layer, a non-doped gallium nitride layer, an N-type layer, a quantum well layer and a P-type layer in sequence along the surface of the substrate;
the buffer layer comprises a first gallium nitride layer and a second gallium nitride layer which alternately grow, the first layer and the last layer of the buffer layer are both first gallium nitride layers, and the growth temperature of the first gallium nitride layers is lower than that of the second gallium nitride layers;
the growth of the P-type layer comprises at least 2 growth stages, and each growth stage comprises the processes of high-temperature growth, annealing and cooling and low-temperature growth.
6. The method for preparing the high-brightness light-emitting diode epitaxial wafer as claimed in claim 5, wherein the method comprises the following steps: the operation steps of each growth stage of the P-type layer are as follows: and obtaining the current growth temperature and growth thickness of the P-type layer, and when the growth thickness reaches a preset value, heating according to a set heating rate or cooling according to a set cooling rate.
7. The method for preparing the high-brightness light-emitting diode epitaxial wafer as claimed in claim 6, wherein the method comprises the following steps: the heating rate is 60-90 ℃ per minute; the cooling rate is 60-90 ℃ per minute.
8. The method for preparing the high-brightness light-emitting diode epitaxial wafer as claimed in claim 5, wherein the method comprises the following steps: the growth temperature of the second gallium nitride layer is 30-115 ℃ higher than that of the first gallium nitride layer adjacent to the second gallium nitride layer.
9. The method for preparing the high-brightness light-emitting diode epitaxial wafer as claimed in claim 5, wherein the method comprises the following steps: the growth temperature of the first gallium nitride layer gradually rises along the growth direction of the epitaxial wafer, and the growth temperature of the second gallium nitride layer gradually rises along the growth direction of the epitaxial wafer.
10. The method for preparing the high-brightness light-emitting diode epitaxial wafer as claimed in claim 5, wherein the method comprises the following steps: the buffer layer is doped with aluminum.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106252473A (en) * | 2016-08-30 | 2016-12-21 | 圆融光电科技股份有限公司 | The growing method of P-type layer in epitaxial wafer |
| CN108091741A (en) * | 2017-11-15 | 2018-05-29 | 华灿光电(苏州）有限公司 | A kind of growing method of LED epitaxial slice |
| CN108198913A (en) * | 2017-11-30 | 2018-06-22 | 华灿光电(苏州）有限公司 | A kind of growing method of LED epitaxial slice |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106252473A (en) * | 2016-08-30 | 2016-12-21 | 圆融光电科技股份有限公司 | The growing method of P-type layer in epitaxial wafer |
| CN108091741A (en) * | 2017-11-15 | 2018-05-29 | 华灿光电(苏州）有限公司 | A kind of growing method of LED epitaxial slice |
| CN108198913A (en) * | 2017-11-30 | 2018-06-22 | 华灿光电(苏州）有限公司 | A kind of growing method of LED epitaxial slice |
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Application publication date: 20200207 |