CN110764924A - Inter-core communication method and device of multi-core processor - Google Patents
Inter-core communication method and device of multi-core processor Download PDFInfo
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Abstract
The embodiment of the invention provides an inter-core communication method and device of a multi-core processor. The method applied to the sending core comprises the following steps: writing data to be transmitted into a first shared memory queue, and writing data characteristic information corresponding to the data to be transmitted into an idle descriptor in a second shared memory queue; acquiring a descriptor address of an occupied descriptor written with data characteristic information corresponding to data to be transmitted; writing the descriptor address of the occupied descriptor into a third special memory queue corresponding to the receiving core, so that the receiving core obtains the occupied descriptor according to the descriptor address of the occupied descriptor and obtains the data to be transmitted according to the occupied descriptor; the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue. The embodiment of the invention increases the use flexibility of the memory and reduces the consumption of the kernel.
Description
Technical Field
The embodiment of the invention relates to the technical field of communication, in particular to an inter-core communication method and device of a multi-core processor.
Background
With the development of wireless communication base station counting, higher and higher requirements are put forward on the processing speed, the parallel processing capability and the miniaturization integration of a base station core processor, and the development requirements of the technologies can be effectively met by the appearance of a multi-core processor product.
At present, a multi-core processor integrates not only the number of single-type computing Processing cores, but also the types of multiple-type computing Processing cores, for example, the TCI6614 integrates multiple computing units such as an random access memory (ARM) core, a Digital Signal Processing (DSP) core, and a communication coprocessor. In a multi-core processor, data sharing and transmission technology among multiple cores is an important guarantee for realizing multi-core cooperative work and improving processor efficiency.
At present, a shared memory is generally used as a medium for data exchange among a plurality of kernels, the shared memory is a physical space which allows the plurality of kernels to access, a sending core writes data into the shared memory, and a receiving core can read data from the shared memory according to a convention mode. The current commonly used methods for performing inter-core data communication by using a shared memory mainly include the following methods:
the first method comprises the following steps: the shared memory is divided into two storage areas which are respectively used as a transmitting channel and a receiving channel of a transmitting core and a receiving core, and the read-write access of the channels of the transmitting core and the receiving core is realized through a locking mechanism. However, this method results in that the shared memory area can be accessed by only one core at a time, which affects the efficiency of data exchange between the sending core and the receiving core.
And the second method comprises the following steps: the read-write pointer replaces the locking mechanism in the first type, and each channel uses a ring queue to realize circular read-write. The sending core judges whether enough space is available for writing data according to the value of the read-write pointer, if the remaining space is satisfied, the data is written into the queue according to the write pointer, and the write pointer is updated to serve as the initial address of the next write data; and the receiving core polls the annular queue, reads data according to the current read pointer when finding that unread data exists in the queue, and updates the read pointer to be used as the initial address of the next read data. However, this method requires that the length of each packet is agreed when sending a fixed-length data packet, and when there is more short-length data, a certain amount of memory waste is caused; and the problem that when sending data packets with indefinite length, in the process of continuously sending messages, the read-write pointer at the back is easily disturbed due to the fault of a certain packet, and the number of unprocessed packets cannot be judged due to indefinite packet length is caused.
And the third is that: two circular queues are adopted in a data transmission direction, one queue is used for storing a read-write pointer pointing to a data entity, and fixed-length data packets are transmitted by the queue; the other queue holds data entities and the queue delivers packets of indefinite length. However, when the multi-way data transmission is performed among the multiple cores, the number of the required dimension queues is large, the operation is complex, and the memory overhead is large.
In summary, the problems of low flexibility of use of the memory area used for inter-core communication and high memory overhead exist in the prior art.
Disclosure of Invention
The embodiment of the invention provides an inter-core communication method and device of a multi-core processor, and aims to solve the problems that in the prior art, a memory area used for inter-core communication is low in use flexibility and high in memory overhead.
In view of the foregoing problems, in a first aspect, an embodiment of the present invention provides an inter-core communication method for a multi-core processor, where the inter-core communication method is applied to a sending core, and the method includes:
writing data to be transmitted into a first shared memory queue for storing a data packet entity, and writing data characteristic information corresponding to the data to be transmitted into an idle descriptor in a second shared memory queue, wherein the second shared memory queue is used for storing a data packet descriptor with a preset data structure;
obtaining a descriptor address of an occupied descriptor written with data characteristic information corresponding to the data to be transmitted;
writing the descriptor address of the occupied descriptor into a third dedicated memory queue corresponding to a receiving core, so that the receiving core obtains the occupied descriptor according to the descriptor address of the occupied descriptor and obtains the data to be transmitted according to the occupied descriptor; wherein the content of the first and second substances,
the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
In a second aspect, an embodiment of the present invention provides an inter-core communication method for a multi-core processor, where the inter-core communication method is applied to a receiving core, and the method is characterized in that:
obtaining a descriptor address of an occupied descriptor from a third special memory queue corresponding to a receiving core, wherein the occupied descriptor is a descriptor written with data characteristic information corresponding to data to be transmitted;
obtaining the occupied descriptors from a second shared memory queue for storing data packet descriptors with a preset data structure according to the descriptor addresses of the occupied descriptors;
obtaining the data to be transmitted from a first shared memory queue for storing a data packet entity according to the data characteristic information in the occupied descriptor; wherein the content of the first and second substances,
the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
In a third aspect, an embodiment of the present invention provides an inter-core communication apparatus for a multi-core processor, which is applied to a sending core, and the apparatus includes:
the device comprises a first write-in module, a second write-in module and a first data processing module, wherein the first write-in module is used for writing data to be transmitted into a first shared memory queue for storing a data packet entity and writing data characteristic information corresponding to the data to be transmitted into an idle descriptor in a second shared memory queue, and the second shared memory queue is used for storing a data packet descriptor with a preset data structure;
the acquisition module is used for acquiring a descriptor address of an occupied descriptor written with data characteristic information corresponding to the data to be transmitted;
a second writing module, configured to write the descriptor address of the occupied descriptor into a third dedicated memory queue corresponding to a receiving core, so that the receiving core obtains the occupied descriptor according to the descriptor address of the occupied descriptor, and obtains the to-be-transmitted data according to the occupied descriptor; wherein the content of the first and second substances,
the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
In a fourth aspect, an embodiment of the present invention provides an inter-core communication apparatus for a multi-core processor, which is applied to a receiving core, and the apparatus includes:
a first obtaining module, configured to obtain a descriptor address of an occupied descriptor from a third dedicated memory queue corresponding to a receiving core, where the occupied descriptor is a descriptor to which data feature information corresponding to data to be transmitted is written;
a second obtaining module, configured to obtain the occupied descriptor from a second shared memory queue for storing a packet descriptor having a preset data structure according to the descriptor address of the occupied descriptor;
a third obtaining module, configured to obtain the data to be transmitted from a first shared memory queue for storing a data packet entity according to the data feature information in the occupied descriptor; wherein the content of the first and second substances,
the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
In a fifth aspect, an embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of the inter-core communication method of the multi-core processor when executing the computer program.
In a sixth aspect, an embodiment of the present invention provides a non-transitory computer readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the inter-core communication method of a multi-core processor.
According to the inter-core communication method and device of the multi-core processor, data to be transmitted are written into the first shared memory queue for storing the data packet entity, data characteristic information corresponding to the data to be transmitted is written into the idle descriptor in the second shared memory queue, then the descriptor address of the occupied descriptor of the data characteristic information corresponding to the data to be transmitted is obtained, and the descriptor address is written into the third special memory queue corresponding to the receiving core, so that the data packet entity with an indefinite length is separated from the data characteristic information with a definite length, and the use flexibility of the memory area where the data packet is located is improved; in addition, the data packet descriptor and the descriptor address are separated, so that multi-way communication among the cores can be completed by using fewer channels, and convenience is provided for maintenance of the multi-way communication; in addition, all the cores share one memory queue for storing the data packet entity and one memory queue for storing the data packet descriptor, so that the memory overhead is saved; in addition, each core transmits the descriptor address through a special memory queue, and mutual interference between multiple cores during data receiving is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is a flow chart illustrating the steps of an inter-core communication method applied to a multi-core processor of a sending core in an embodiment of the present invention;
FIG. 2 is a flow chart illustrating the steps of an inter-core communication method applied to a multi-core processor of a receiving core in an embodiment of the present invention;
FIG. 3 shows a block diagram of an inter-core communication apparatus of a multi-core processor applied to a transmitting core in an embodiment of the present invention;
FIG. 4 shows a block diagram of an inter-core communication apparatus of a multi-core processor applied to a receiving core in an embodiment of the present invention;
fig. 5 shows a block diagram of an electronic device in an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, which is a flowchart of steps of an inter-core communication method applied to a multi-core processor of a sending core in an embodiment of the present invention, the method includes the following steps:
step 101: and writing the data to be transmitted into a first shared memory queue for storing a data packet entity, and writing data characteristic information corresponding to the data to be transmitted into an idle descriptor in a second shared memory queue.
In this embodiment, specifically, the queues obtained by dividing the preconfigured memory segment include a first shared memory queue, a second shared memory queue, and a third dedicated memory queue, where the first shared memory queue is used to store the data packet entity, the second shared memory queue is used to store the data packet descriptor having the preset data structure, the third dedicated memory queue is used to store the descriptor address of the data packet descriptor in the second shared memory queue, and each receiving core corresponds to one third dedicated memory queue. At this time, specifically, when the multi-core processor has N cores, the number of queues obtained by dividing the memory segment is N +2, where the number of the first shared memory queues is 1, the number of the second shared memory queues is 1, the number of the third dedicated memory queues is N, and N is a positive integer greater than 1.
In addition, specifically, each memory queue is a circular queue, and each queue is provided with a read-write index or a read-write pointer, so as to realize the positioning and updating of the data storage position.
In addition, in this step, specifically, when the sending core needs to transmit the data to be transmitted to a receiving core, the position for writing the data to be transmitted may be obtained in the first shared memory queue for storing the data packet entity, the data to be transmitted may be written in the first shared memory queue, then the idle descriptor for writing the data characteristic information corresponding to the data to be transmitted may be obtained in the second shared memory queue, and the data characteristic information corresponding to the data to be transmitted may be written in the idle descriptor in the second shared memory queue, so as to implement respective transmission of the data characteristic information of the data entity to be transmitted and the data to be transmitted, that is, implement respective transmission of the indefinite length data packet and the fixed length data packet, thereby improving the flexibility of use of the memory queue.
Step 102: and acquiring the descriptor address of the occupied descriptor written with the data characteristic information corresponding to the data to be transmitted.
In this step, specifically, after writing the data characteristic information corresponding to the data to be transmitted into the idle descriptor in the second shared memory queue, the occupied descriptor written with the data characteristic information corresponding to the data to be transmitted is obtained, and at this time, the descriptor address of the occupied descriptor in the second shared memory queue may be obtained, so that the receiving core may find the occupied descriptor according to the descriptor address, so as to find the data corresponding to the data characteristic information in the occupied descriptor, and further implement the whole transmission process of the data between the sending core and the receiving core.
Step 103: writing the descriptor address of the occupied descriptor into a third dedicated memory queue corresponding to the receiving core.
In this step, specifically, after the descriptor address of the occupied descriptor written with the data feature information corresponding to the data to be transmitted is obtained, the descriptor address of the occupied descriptor may be written into a third dedicated memory queue corresponding to the receiving core, so that the receiving core obtains the occupied descriptor according to the descriptor address of the occupied descriptor, and obtains the data to be transmitted according to the occupied descriptor, thereby implementing the transmission process of the data between the sending core and the receiving core.
In addition, specifically, the data entity to be transmitted, the descriptor written in the data characteristic information of the data to be transmitted, and the descriptor address are respectively transmitted through a memory queue, and all cores share a first shared memory queue for storing the data packet entity and a second shared memory queue for storing the data packet descriptor, so that only the first shared memory queue, the second shared memory queue, and a third dedicated memory queue with the same number as that of the cores need to be maintained in the data transmission process.
In this way, in this embodiment, data to be transmitted is written into the first shared memory queue for storing the data packet entity, data feature information corresponding to the data to be transmitted is written into the idle descriptor in the second shared memory queue, then a descriptor address of an occupied descriptor into which the data feature information corresponding to the data to be transmitted is written is obtained, and the descriptor address is written into the third dedicated memory queue corresponding to the receiving core, so that the data packet entity of indefinite length is separated from the data feature information of definite length, and the use flexibility of the memory region in which the data packet is located is improved; in addition, the data packet descriptor and the descriptor address are separated, so that multi-way communication among the cores can be completed by using fewer channels, and convenience is provided for maintenance of the multi-way communication; in addition, all the cores share one memory queue for storing the data packet entity and one memory queue for storing the data packet descriptor, so that the memory overhead is saved; in addition, each core transmits the descriptor address through a special memory queue, and mutual interference between multiple cores during data receiving is avoided.
Furthermore, each memory queue is provided with a read-write pointer or a read-write index for locating and updating data write and read positions in the queue.
At this time, in this embodiment, before writing data to be transmitted into a first shared memory queue for storing a data packet entity and writing data characteristic information corresponding to the data to be transmitted into an idle descriptor in a second shared memory queue, the method further includes, when it is detected that the first shared memory queue meets a data transmission requirement and the second shared memory queue has the idle descriptor, locking a write pointer of the first shared memory queue and a read pointer of the second shared memory queue; and then writing the data to be transmitted into the position pointed by the write pointer in the first shared memory queue, and writing the data characteristic information corresponding to the data to be transmitted into the idle descriptor pointed by the read pointer in the second shared memory queue.
Specifically, when it is detected that the first shared memory queue meets the data sending requirement, the unoccupied space in the first shared memory queue can store the data to be transmitted.
Therefore, by locking the write pointer in the first shared memory queue and the read pointer in the second shared memory queue, access conflict between multiple cores to the memory queue is avoided, normal access of the sending core to the first shared memory queue and the second shared memory queue is guaranteed, namely, the sending core is guaranteed to write the data to be transmitted into the position pointed by the write pointer in the first shared memory queue according to rules, and data characteristic information corresponding to the data to be transmitted is written into the idle descriptor pointed by the read pointer in the second shared memory queue, so that a writing process of separating a data entity from the data characteristic information is realized.
In addition, specifically, when writing the descriptor address of the occupied descriptor into the third dedicated memory queue corresponding to the receiving core, the descriptor address of the occupied descriptor may be written into a position pointed by a write pointer in the third dedicated memory queue corresponding to the receiving core according to the write pointer in the third dedicated memory queue corresponding to the receiving core.
Of course, specifically, the pointed position of the write pointer in the third dedicated memory queue is the tail of the third dedicated memory queue, so that writing can be performed according to a certain order when the descriptor address is written into the third dedicated memory queue.
Therefore, the read-write fingers in the memory queues are used for positioning the write-in positions of the data, and the first shared memory queue, the second shared memory queue and the third special memory queue are normally used.
In addition, specifically, it should be noted herein that before data transmission, the first shared memory queue, the second shared memory queue, and the third dedicated memory queue may be initialized respectively; when the first shared memory queue is initialized, both a read pointer and a write pointer in the first shared memory queue can point to the initial position of the first shared memory queue, and the write pointer is increased progressively from the initial position; when initializing the second shared memory queue, the read pointer and the write pointer in the second shared memory queue may both point to the starting position, the sending core identity and the receiving core identity in the data packet descriptor are initialized to invalid values, the starting address and the length of the data packet entity are initialized to invalid values, and the memory size of the first shared memory queue and the total number of the data packet descriptor are filled; when the third dedicated memory queue is initialized, both the read pointer and the write pointer in the third dedicated memory queue may point to the start position, and the descriptor address stored in each data packet in the queue is initialized to an invalid value. Thus, through the initialization process, convenience is provided for transmitting data through the first shared memory queue, the second shared memory queue and the third dedicated memory queue.
In addition, after the data to be transmitted is written into the first shared memory queue for storing the data packet entity and the data characteristic information corresponding to the data to be transmitted is written into the idle descriptor in the second shared memory queue, the write pointer in the first shared memory queue and the read pointer in the second shared memory queue may also be updated.
Specifically, when the read pointer in the second shared memory queue is updated, and when the read pointer in the second shared memory queue is increased by 1, it indicates that the sending core has acquired an idle descriptor in the second shared memory queue.
Therefore, by updating the write pointer in the first shared memory queue and the read pointer in the second shared memory queue, the sending core can know whether the remaining space in the first shared memory queue and the second shared memory queue have the idle descriptors, so that a basis is provided for data transmission.
Furthermore, the preset data structure of the packet descriptor further includes: the total number of the data packet descriptors in the second shared memory queue, the memory size of the first shared memory queue, the data packet entity start address and the data packet entity length corresponding to the data to be transmitted, the identity of the sending core, and the identity of the receiving core.
At this time, the data characteristic information of the data to be transmitted also includes the total number of the packet descriptors in the second shared memory queue, the memory size of the first shared memory queue, the packet entity start address and the packet entity length corresponding to the data to be transmitted, the identity of the sending core, and the identity of the receiving core. The data characteristic information of the data to be transmitted is written into the idle descriptor according to the preset data structure of the data packet descriptor, so that the receiving core can obtain the data to be transmitted according to the data characteristic information in the occupied descriptor.
In this way, in this embodiment, data to be transmitted is written into the first shared memory queue for storing the data packet entity, data feature information corresponding to the data to be transmitted is written into the idle descriptor in the second shared memory queue, then a descriptor address of an occupied descriptor into which the data feature information corresponding to the data to be transmitted is written is obtained, and the descriptor address is written into the third dedicated memory queue corresponding to the receiving core, so that separation of the data packet entity of an indefinite length from the data feature information of a definite length is achieved, and the use flexibility of the memory region in which the data packet is located is improved; in addition, the data packet descriptor and the descriptor address are separated, so that multi-way communication among the cores can be completed by using fewer channels, and convenience is provided for maintenance of the multi-way communication; in addition, all the cores share one memory queue for storing the data packet entity and one memory queue for storing the data packet descriptor, so that the memory overhead is saved; in addition, each core transmits the descriptor address through a special memory queue, and mutual interference between multiple cores during data receiving is avoided.
As shown in fig. 2, which is a flowchart of steps of an inter-core communication method applied to a multi-core processor of a receiving core in the embodiment of the present invention, the method includes the following steps:
step 201: obtaining descriptor addresses of occupied descriptors from a third private memory queue corresponding to the receiving core.
In this embodiment, specifically, the queues obtained by dividing the preconfigured memory segment include a first shared memory queue, a second shared memory queue, and a third dedicated memory queue, where the first shared memory queue is used to store the data packet entity, the second shared memory queue is used to store the data packet descriptor having the preset data structure, the third dedicated memory queue is used to store the descriptor address of the data packet descriptor in the second shared memory queue, and each receiving core corresponds to one third dedicated memory queue. At this time, specifically, when the multi-core processor has N cores, the number of queues obtained by dividing the memory segment is N +2, where the number of the first shared memory queues is 1, the number of the second shared memory queues is 1, the number of the third dedicated memory queues is N, and N is a positive integer greater than 1.
In addition, specifically, each memory queue is a circular queue, and each queue is provided with a read-write index or a read-write pointer, so as to realize the positioning and updating of the data storage position.
In this step, specifically, the receiving core may obtain a descriptor address of an occupied descriptor from a third dedicated memory queue corresponding to the receiving core, where the occupied descriptor is a descriptor to which data feature information corresponding to the data to be transmitted has been written, so that the receiving core can obtain the occupied descriptor from the second shared memory queue according to the descriptor address.
Step 202: and obtaining the occupied descriptors from a second shared memory queue for storing the data packet descriptors with the preset data structure according to the descriptor addresses of the occupied descriptors.
In this step, specifically, after the descriptor address of the occupied descriptor is obtained, the occupied descriptor may be obtained from the second shared memory queue according to the descriptor address of the occupied descriptor, so that the data to be transmitted may be obtained according to the data feature information in the occupied descriptor.
Step 203: and obtaining the data to be transmitted from the first shared memory queue for storing the data packet entity according to the data characteristic information in the occupied descriptor.
In this step, specifically, after the receiving core obtains the occupied descriptor, the data to be transmitted may be obtained from the first shared memory queue for storing the data packet entity according to the data feature information in the occupied descriptor, so as to implement the data transmission process.
In this way, in this embodiment, the descriptor address of the occupied descriptor is obtained from the third dedicated memory queue corresponding to the receiving core, where the occupied descriptor is a descriptor written with data feature information corresponding to the data to be transmitted, then the occupied descriptor is obtained from the second shared memory queue for storing the data packet descriptor having the preset data structure according to the descriptor address of the occupied descriptor, and finally the data to be transmitted is obtained from the first shared memory queue for storing the data packet entity according to the data feature information in the occupied descriptor, so that the respective obtaining of the data packet entity of indefinite length and the data feature information of definite length is realized, and the flexibility of use of the memory region where the data packet is located is improved; in addition, the data packet descriptor and the descriptor address are respectively obtained, so that the multi-way communication among the cores can be completed by using fewer channels, and convenience is provided for the maintenance of the multi-way communication; in addition, all the cores share one first shared memory queue for storing the data packet entity and one second shared memory queue for storing the data packet descriptor, and memory overhead is saved; in addition, each kernel transmits the descriptor address through the corresponding special memory queue, mutual interference when receiving data among multiple cores is avoided, and safe transmission of the data is guaranteed.
Furthermore, each memory queue is provided with a read-write pointer. At this time, when the descriptor address of the occupied descriptor is obtained from the third dedicated memory queue corresponding to the receiving core, when it is detected that an unread descriptor address exists in the third dedicated memory queue according to the read pointer in the third dedicated memory queue, the descriptor address of the occupied descriptor may be obtained according to the read pointer in the third dedicated memory queue.
In this way, by setting the read pointer, the receiving core can accurately acquire the descriptor address, and omission of the descriptor address which is not acquired is avoided.
In addition, specifically, after the descriptor address of the occupied descriptor is obtained from the third dedicated memory queue corresponding to the receiving core, the read pointer in the third dedicated memory queue may also be updated.
Therefore, by updating the read pointer in the third dedicated memory queue, the accurate acquisition process of the descriptor address in the third dedicated memory queue is ensured, and the receiving core is prevented from missing the unread descriptor address.
In addition, further, after the data to be transmitted is obtained from the first shared memory queue for storing the data packet entity according to the data feature information in the occupied descriptor, the read pointer in the first shared memory queue may be locked and updated, and the write pointer in the second shared memory queue may be locked and updated. Therefore, access conflict of a plurality of receiving cores to the first shared memory queue and the second shared memory queue is avoided, and safety in data receiving is guaranteed.
Specifically, when the write pointer in the second shared memory queue is updated, and when the write pointer is incremented by 1, it indicates that the receiving core releases an occupied descriptor, that is, a free descriptor is added to the second shared memory queue.
Further, the preset data structure of the packet descriptor includes: the total number of the data packet descriptors in the second shared memory queue, the memory size of the first shared memory queue, the data packet entity start address and the data packet entity length corresponding to the data to be transmitted, the identity of the sending core, and the identity of the receiving core.
At this time, the data characteristic information of the data to be transmitted also includes the total number of the packet descriptors in the second shared memory queue, the memory size of the first shared memory queue, the packet entity start address and the packet entity length corresponding to the data to be transmitted, the identity of the sending core, and the identity of the receiving core. The data characteristic information of the data to be transmitted is written into the idle descriptor according to the preset data structure of the data packet descriptor, so that the receiving core can obtain the data to be transmitted according to the data characteristic information in the occupied descriptor.
In this way, in this embodiment, the descriptor address of the occupied descriptor is obtained from the third dedicated memory queue corresponding to the receiving core, where the occupied descriptor is a descriptor written with data feature information corresponding to the data to be transmitted, the occupied descriptor is obtained from the second shared memory queue according to the descriptor address of the occupied descriptor, and finally the data to be transmitted is obtained from the first shared memory queue for storing the data packet entity according to the data feature information in the occupied descriptor, so that the respective obtaining of the data packet entity of indefinite length and the data feature information of definite length is realized, and the use flexibility of the memory region where the data packet is located is improved; in addition, the data packet descriptor and the descriptor address are respectively obtained, so that the multi-way communication among the cores can be completed by using fewer channels, and convenience is provided for the maintenance of the multi-way communication; in addition, all the cores share one first shared memory queue for storing the data packet entity and one second shared memory queue for storing the data packet descriptor, and memory overhead is saved; in addition, each kernel transmits the descriptor address through the corresponding special memory queue, mutual interference when receiving data among multiple cores is avoided, and safe transmission of the data is guaranteed.
Furthermore, as shown in fig. 3, a block diagram of an inter-core communication apparatus applied to a multi-core processor for sending cores in the embodiment of the present invention is shown, where the apparatus includes:
a first writing module 301, configured to write data to be transmitted into a first shared memory queue for storing a data packet entity, and write data characteristic information corresponding to the data to be transmitted into an idle descriptor in a second shared memory queue, where the second shared memory queue is used to store a data packet descriptor with a preset data structure;
an obtaining module 302, configured to obtain a descriptor address of an occupied descriptor written with data feature information corresponding to the to-be-transmitted data;
a second writing module 303, configured to write the descriptor address of the occupied descriptor into a third dedicated memory queue corresponding to a receiving core, so that the receiving core obtains the occupied descriptor according to the descriptor address of the occupied descriptor, and obtains the to-be-transmitted data according to the occupied descriptor; wherein the content of the first and second substances,
the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
Optionally, the first writing module 301 includes:
a locking unit, configured to lock a write pointer of the first shared memory queue and a read pointer of the second shared memory queue when it is detected that the first shared memory queue meets a data sending requirement and a free descriptor exists in the second shared memory queue;
a write-in unit, configured to write the to-be-transmitted data into a position pointed by a write pointer in the first shared memory queue, and write data characteristic information corresponding to the to-be-transmitted data into an idle descriptor pointed by a read pointer in the second shared memory queue;
the second writing module 303 is configured to write the descriptor address of the occupied descriptor into a position pointed by a write pointer in a third dedicated memory queue corresponding to the receiving core according to the write pointer in the third dedicated memory queue corresponding to the receiving core.
Optionally, the apparatus further comprises:
a first updating module, configured to update a write pointer in the first shared memory queue and a read pointer in the second shared memory queue;
and the second updating module is used for updating the write pointer in the third special memory queue corresponding to the receiving core.
Optionally, the preset data structure of the packet descriptor includes: the total number of the data packet descriptors in the second shared memory queue, the memory size of the first shared memory queue, the data packet entity start address and the data packet entity length corresponding to the data to be transmitted, the identity of the sending core, and the identity of the receiving core.
According to the device provided by the embodiment of the invention, the data to be transmitted is written into the first shared memory queue for storing the data packet entity, the data characteristic information corresponding to the data to be transmitted is written into the idle descriptor in the second shared memory queue, then the descriptor address of the occupied descriptor written with the data characteristic information corresponding to the data to be transmitted is obtained, and the descriptor address is written into the third special memory queue corresponding to the receiving core, so that the separation of the data packet entity with an indefinite length from the data characteristic information with a definite length is realized, and the use flexibility of the memory area where the data packet is located is improved; in addition, the data packet descriptor and the descriptor address are separated, so that multi-way communication among the cores can be completed by using fewer channels, and convenience is provided for maintenance of the multi-way communication; in addition, all the cores share one memory queue for storing the data packet entity and one memory queue for storing the data packet descriptor, so that the memory overhead is saved; in addition, each core transmits the descriptor address through a special memory queue, and mutual interference between multiple cores during data receiving is avoided.
Furthermore, as shown in fig. 4, a block diagram of an inter-core communication apparatus applied to a multi-core processor receiving cores in the embodiment of the present invention is shown, where the apparatus includes:
a first obtaining module 401, configured to obtain a descriptor address of an occupied descriptor from a third dedicated memory queue corresponding to a receiving core, where the occupied descriptor is a descriptor written with data feature information corresponding to data to be transmitted;
a second obtaining module 402, configured to obtain the occupied descriptor from a second shared memory queue for storing a packet descriptor having a preset data structure according to the descriptor address of the occupied descriptor;
a third obtaining module 403, configured to obtain, according to the data feature information in the occupied descriptor, the to-be-transmitted data from a first shared memory queue for storing a data packet entity; wherein the content of the first and second substances,
the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
Optionally, the first obtaining module 401 is configured to, when it is detected that an unread descriptor address exists in the third dedicated memory queue according to a read pointer in the third dedicated memory queue, obtain, according to the read pointer in the third dedicated memory queue, the descriptor address of the occupied descriptor;
the device further comprises:
and the first updating module is used for updating the read pointer in the third special memory queue.
Optionally, the apparatus further comprises:
and the second updating module is used for locking and updating the read pointer in the first shared memory queue and locking and updating the write pointer in the second shared memory queue.
Optionally, the preset data structure of the packet descriptor includes: the total number of the data packet descriptors in the second shared memory queue, the memory size of the first shared memory queue, the data packet entity start address and the data packet entity length corresponding to the data to be transmitted, the identity of the sending core, and the identity of the receiving core.
The device provided by this embodiment obtains a descriptor address of an occupied descriptor from a third dedicated memory queue corresponding to a receiving core, where the occupied descriptor is a descriptor written with data feature information corresponding to data to be transmitted, obtains the occupied descriptor from a second shared memory queue for storing data descriptors having a preset data structure according to the descriptor address of the occupied descriptor, and obtains the data to be transmitted from a first shared memory queue for storing a data packet entity according to the data feature information in the occupied descriptor, so that respective obtaining of data packet entities of indefinite length and data feature information of definite length is achieved, and flexibility in use of a memory region where the data packet is located is improved; in addition, the data packet descriptor and the descriptor address are respectively obtained, so that the multi-way communication among the cores can be completed by using fewer channels, and convenience is provided for the maintenance of the multi-way communication; in addition, all the cores share one first shared memory queue for storing the data packet entity and one second shared memory queue for storing the data packet descriptor, and memory overhead is saved; in addition, each kernel transmits the descriptor address through the corresponding special memory queue, mutual interference when receiving data among multiple cores is avoided, and safe transmission of the data is guaranteed.
It should be noted that, in the embodiment of the present invention, the related functional modules may be implemented by a hardware processor (hardware processor), and the same technical effect can be achieved, which is not described herein again.
In yet another embodiment of the present invention, an electronic device is provided, as shown in fig. 5, which includes a memory (memory)501, a processor (processor)502, and a computer program stored on the memory 501 and executable on the processor 502. The memory 501 and the processor 502 are in communication with each other through a bus 503. The processor 502 is configured to call program instructions in the memory 501 to perform the following method: writing data to be transmitted into a first shared memory queue for storing a data packet entity, and writing data characteristic information corresponding to the data to be transmitted into an idle descriptor in a second shared memory queue, wherein the second shared memory queue is used for storing a data packet descriptor with a preset data structure; obtaining a descriptor address of an occupied descriptor written with data characteristic information corresponding to the data to be transmitted; writing the descriptor address of the occupied descriptor into a third dedicated memory queue corresponding to a receiving core, so that the receiving core obtains the occupied descriptor according to the descriptor address of the occupied descriptor and obtains the data to be transmitted according to the occupied descriptor; the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
Alternatively, the processor 502 is configured to call program instructions in the memory 501 to perform the following method: obtaining a descriptor address of an occupied descriptor from a third special memory queue corresponding to a receiving core, wherein the occupied descriptor is a descriptor written with data characteristic information corresponding to data to be transmitted; obtaining the occupied descriptors from a second shared memory queue for storing data packet descriptors with a preset data structure according to the descriptor addresses of the occupied descriptors; obtaining the data to be transmitted from a first shared memory queue for storing a data packet entity according to the data characteristic information in the occupied descriptor; the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
The electronic device provided by the embodiment of the invention can execute specific steps in the inter-core communication method of the multi-core processor and can achieve the same technical effect, and the specific description is not provided herein.
Further, the program instructions in the memory 501 may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In a further embodiment of the invention, a non-transitory computer readable storage medium is provided, having stored thereon a computer program which, when executed by a processor, is operative to perform the method of: writing data to be transmitted into a first shared memory queue for storing a data packet entity, and writing data characteristic information corresponding to the data to be transmitted into an idle descriptor in a second shared memory queue, wherein the second shared memory queue is used for storing a data packet descriptor with a preset data structure; obtaining a descriptor address of an occupied descriptor written with data characteristic information corresponding to the data to be transmitted; writing the descriptor address of the occupied descriptor into a third dedicated memory queue corresponding to a receiving core, so that the receiving core obtains the occupied descriptor according to the descriptor address of the occupied descriptor and obtains the data to be transmitted according to the occupied descriptor; the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
Alternatively, the computer program is executed by a processor to perform the method of: obtaining a descriptor address of an occupied descriptor from a third special memory queue corresponding to a receiving core, wherein the occupied descriptor is a descriptor written with data characteristic information corresponding to data to be transmitted; obtaining the occupied descriptors from a second shared memory queue for storing data packet descriptors with a preset data structure according to the descriptor addresses of the occupied descriptors; obtaining the data to be transmitted from a first shared memory queue for storing a data packet entity according to the data characteristic information in the occupied descriptor; the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
The non-transitory computer-readable storage medium provided in the embodiment of the present invention may execute specific steps in an inter-core communication method of a multi-core processor, and may achieve the same technical effect, which is not described in detail herein.
In yet another embodiment of the present invention, a computer program product is provided, the computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions that when executed by a computer perform the method of: writing data to be transmitted into a first shared memory queue for storing a data packet entity, and writing data characteristic information corresponding to the data to be transmitted into an idle descriptor in a second shared memory queue, wherein the second shared memory queue is used for storing a data packet descriptor with a preset data structure; obtaining a descriptor address of an occupied descriptor written with data characteristic information corresponding to the data to be transmitted; writing the descriptor address of the occupied descriptor into a third dedicated memory queue corresponding to a receiving core, so that the receiving core obtains the occupied descriptor according to the descriptor address of the occupied descriptor and obtains the data to be transmitted according to the occupied descriptor; the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
Alternatively, the program instructions when executed by a computer perform the method of: obtaining a descriptor address of an occupied descriptor from a third special memory queue corresponding to a receiving core, wherein the occupied descriptor is a descriptor written with data characteristic information corresponding to data to be transmitted; obtaining the occupied descriptors from a second shared memory queue for storing data packet descriptors with a preset data structure according to the descriptor addresses of the occupied descriptors; obtaining the data to be transmitted from a first shared memory queue for storing a data packet entity according to the data characteristic information in the occupied descriptor; the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
The computer program product provided by the embodiment of the invention can execute the specific steps in the inter-core communication method of the multi-core processor and can achieve the same technical effect, and the specific description is not provided herein.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (12)
1. An inter-core communication method of a multi-core processor, applied to a sending core, is characterized by comprising the following steps:
writing data to be transmitted into a first shared memory queue for storing a data packet entity, and writing data characteristic information corresponding to the data to be transmitted into an idle descriptor in a second shared memory queue, wherein the second shared memory queue is used for storing a data packet descriptor with a preset data structure;
obtaining a descriptor address of an occupied descriptor written with data characteristic information corresponding to the data to be transmitted;
writing the descriptor address of the occupied descriptor into a third dedicated memory queue corresponding to a receiving core, so that the receiving core obtains the occupied descriptor according to the descriptor address of the occupied descriptor and obtains the data to be transmitted according to the occupied descriptor; wherein the content of the first and second substances,
the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
2. The method of claim 1, wherein writing the data to be transmitted into a first shared memory queue for storing a data packet entity, and writing data characteristic information corresponding to the data to be transmitted into an idle descriptor in a second shared memory queue comprises:
when detecting that the first shared memory queue meets the data sending requirement and the second shared memory queue has an idle descriptor, locking a write pointer of the first shared memory queue and a read pointer of the second shared memory queue;
writing the data to be transmitted into a position pointed by a write pointer in the first shared memory queue, and writing data characteristic information corresponding to the data to be transmitted into an idle descriptor pointed by a read pointer in the second shared memory queue;
the writing the descriptor address of the occupied descriptor into a third dedicated memory queue corresponding to the receiving core includes:
and writing the descriptor address of the occupied descriptor into the position pointed by the write pointer in the third special memory queue corresponding to the receiving core according to the write pointer in the third special memory queue corresponding to the receiving core.
3. The method according to claim 2, wherein after writing the data to be transmitted into the first shared memory queue for storing the data packet entity and writing the data characteristic information corresponding to the data to be transmitted into the idle descriptor in the second shared memory queue, the method further comprises:
updating a write pointer in the first shared memory queue and a read pointer in the second shared memory queue;
after writing the descriptor address of the occupied descriptor into the third private memory queue corresponding to the receiving core, the method further includes:
and updating a write pointer in a third special memory queue corresponding to the receiving core.
4. The method of claim 1, wherein the predetermined data structure of the packet descriptor comprises: the total number of the data packet descriptors in the second shared memory queue, the memory size of the first shared memory queue, the data packet entity start address and the data packet entity length corresponding to the data to be transmitted, the identity of the sending core, and the identity of the receiving core.
5. An inter-core communication method of a multi-core processor, applied to a receiving core, is characterized by comprising the following steps:
obtaining a descriptor address of an occupied descriptor from a third special memory queue corresponding to a receiving core, wherein the occupied descriptor is a descriptor written with data characteristic information corresponding to data to be transmitted;
obtaining the occupied descriptors from a second shared memory queue for storing data packet descriptors with a preset data structure according to the descriptor addresses of the occupied descriptors;
obtaining the data to be transmitted from a first shared memory queue for storing a data packet entity according to the data characteristic information in the occupied descriptor; wherein the content of the first and second substances,
the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
6. The method of claim 5, wherein obtaining the descriptor address of the occupied descriptor from the third private-memory queue corresponding to the receiving core comprises:
when the fact that the descriptor address which is not read exists in the third special memory queue is detected according to the read pointer in the third special memory queue, the descriptor address of the occupied descriptor is obtained according to the read pointer in the third special memory queue;
after obtaining the descriptor address of the occupied descriptor from the third dedicated memory queue corresponding to the receiving core, the method further includes:
and updating the read pointer in the third dedicated memory queue.
7. The method of claim 5, wherein after obtaining the data to be transmitted from the first shared memory queue for storing the data packet entity according to the data characteristic information in the occupied descriptor, the method further comprises:
and locking and updating the read pointer in the first shared memory queue, and locking and updating the write pointer in the second shared memory queue.
8. The method of claim 5, wherein the predetermined data structure of the packet descriptor comprises: the total number of the data packet descriptors in the second shared memory queue, the memory size of the first shared memory queue, the data packet entity start address and the data packet entity length corresponding to the data to be transmitted, the identity of the sending core, and the identity of the receiving core.
9. An inter-core communication apparatus of a multi-core processor, applied to a sending core, the apparatus comprising:
the device comprises a first write-in module, a second write-in module and a first data processing module, wherein the first write-in module is used for writing data to be transmitted into a first shared memory queue for storing a data packet entity and writing data characteristic information corresponding to the data to be transmitted into an idle descriptor in a second shared memory queue, and the second shared memory queue is used for storing a data packet descriptor with a preset data structure;
the acquisition module is used for acquiring a descriptor address of an occupied descriptor written with data characteristic information corresponding to the data to be transmitted;
a second writing module, configured to write the descriptor address of the occupied descriptor into a third dedicated memory queue corresponding to a receiving core, so that the receiving core obtains the occupied descriptor according to the descriptor address of the occupied descriptor, and obtains the to-be-transmitted data according to the occupied descriptor; wherein the content of the first and second substances,
the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
10. An inter-core communication apparatus of a multi-core processor, applied to a receiving core, the apparatus comprising:
a first obtaining module, configured to obtain a descriptor address of an occupied descriptor from a third dedicated memory queue corresponding to a receiving core, where the occupied descriptor is a descriptor to which data feature information corresponding to data to be transmitted is written;
a second obtaining module, configured to obtain the occupied descriptor from a second shared memory queue for storing a packet descriptor having a preset data structure according to the descriptor address of the occupied descriptor;
a third obtaining module, configured to obtain the data to be transmitted from a first shared memory queue for storing a data packet entity according to the data feature information in the occupied descriptor; wherein the content of the first and second substances,
the first shared memory queue, the second shared memory queue and the third dedicated memory queue are queues obtained by dividing in a pre-configured memory segment, and each receiving core corresponds to one third dedicated memory queue.
11. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the inter-core communication method of the multi-core processor according to any of claims 1 to 8 when executing the computer program.
12. A non-transitory computer readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the inter-core communication method of a multi-core processor according to any one of claims 1 to 8.
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Application publication date: 20200207 |