CN112732461A - Inter-algorithm data transmission method and device in system - Google Patents
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 39
- 230000005055 memory storage Effects 0.000 claims abstract description 57
- 238000012546 transfer Methods 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 9
- 238000013500 data storage Methods 0.000 abstract description 6
- 238000007726 management method Methods 0.000 description 8
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- 238000001514 detection method Methods 0.000 description 3
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/544—Buffers; Shared memory; Pipes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/546—Message passing systems or structures, e.g. queues
Abstract
The invention discloses a method and a device for transmitting data among algorithms in a system, wherein the method comprises the following steps: acquiring output data of a first algorithm and storing the output data into a shared memory; outputting data items whose data includes at least one variable; acquiring memory storage structure description information of output data; determining the initial address of a variable required by a second algorithm according to the memory storage structure description information; and reading the data item of the required variable from the shared memory according to the initial address of the required variable and using the data item as the input of the second algorithm. The data are read through the memory storage structure description, the memory storage structure description is irrelevant to the specific memory storage structure definition, the problem of data transmission relevance among algorithms can be decoupled, and meanwhile the problems of transmission compatibility and stability caused by data storage structure differences among different algorithm versions can be solved.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a method and a device for data transmission among algorithms in a system.
Background
In the field of artificial intelligence, a solution for combining a plurality of algorithms to form a specific scene application is generally available, and efficient data transfer among the plurality of algorithms is a key factor for improving data processing throughput. The data transmission mode among algorithms in the same system is usually realized by sharing memory addresses through specific data storage structures, the shared memory has the characteristics of high transmission efficiency, stability, reliability and the like, but the former algorithm and the latter algorithm depend on unified memory space data storage structure definition, and the data storage structure has strong relevance.
Disclosure of Invention
The present invention provides a method and an apparatus for inter-algorithm data transmission within a system, which are directed to the above-mentioned deficiencies of the prior art, and the object is achieved by the following technical solutions.
The first aspect of the present invention provides a method for inter-algorithm data transfer within a system, the method comprising:
acquiring output data of a first algorithm and storing the output data into a shared memory; the output data comprises data items of at least one variable;
acquiring the memory storage structure description information of the output data;
determining the initial address of a variable required by a second algorithm according to the memory storage structure description information, wherein the input of the second algorithm depends on the output data of the first algorithm;
and reading the data item of the required variable from the shared memory according to the starting address of the required variable and using the data item as the input of the second algorithm.
A second aspect of the present invention provides an inter-algorithm data transfer apparatus inside a system, the apparatus comprising:
the storage module is used for acquiring output data of the first algorithm and storing the output data into the shared memory; the output data comprises data items of at least one variable;
the description module is used for acquiring the memory storage structure description information of the output data;
the determining module is used for determining the starting address of a variable required by a second algorithm according to the memory storage structure description information, wherein the input of the second algorithm depends on the output data of the first algorithm;
and the reading module is used for reading the data item of the required variable from the shared memory according to the initial address of the required variable and taking the data item as the input of the second algorithm.
Based on the method and the device for transmitting data among algorithms in the system in the first aspect and the second aspect, the method and the device have the following advantages:
the output data of the first algorithm is stored in the shared memory, the memory storage structure of the output data is described, the second algorithm determines the initial address of the variable required by the algorithm according to the memory storage structure description information of the output data, and reads the data item of the required variable from the shared memory according to the initial address, so that the data is read through the memory storage structure description without changing the efficient data transmission characteristic of the shared memory, the data transmission relevance problem among the algorithms can be decoupled regardless of the specific memory storage structure definition, and the transmission compatibility and stability problems caused by the data storage structure difference among different algorithm versions can be solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart illustrating an embodiment of a method for inter-algorithm data transfer within a system according to an exemplary embodiment of the present invention;
FIG. 2 is a diagram illustrating a relationship between memory storage structure definitions and memory offset addresses according to the embodiment of FIG. 1;
FIG. 3 is a diagram illustrating a memory storage structure description according to the embodiment shown in FIG. 2;
FIG. 4 is a diagram illustrating a hardware configuration of an electronic device in accordance with an exemplary embodiment of the present invention;
fig. 5 is a schematic structural diagram illustrating an inter-algorithm data transfer apparatus within a system according to an exemplary embodiment of the present invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present invention. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
According to the invention, on the premise of ensuring high-efficiency data transmission, the problem of strong data transmission relevance of the shared memory in the prior art is solved by a data decoupling transmission mode which shares the memory and does not depend on a specific memory storage structure.
The inter-algorithm data transfer method in the system according to the present invention is described in detail with specific embodiments below.
Fig. 1 is a flowchart illustrating an embodiment of an inter-algorithm data transfer method in a system according to an exemplary embodiment of the present invention, where the inter-algorithm data transfer method in the system can be applied to an electronic device, as shown in fig. 1, and the inter-algorithm data transfer method in the system includes the following steps:
step 101: and acquiring output data of the first algorithm and storing the output data into the shared memory, wherein the output data comprises at least one data item of a variable.
The shared memory is a segment of storage space which can be commonly used by a plurality of algorithms in the system.
It should be noted that after the output data is stored in the shared memory, the transmission queue of the first algorithm records an initial address of the output data in the shared memory, that is, a shared memory address.
In this embodiment, the system includes multiple algorithms, for example, in a video detection application scenario, multiple algorithms need to be combined to realize detection, a decoding algorithm is performed first, then a detection algorithm is performed, and finally a tracking algorithm is performed.
Step 102: and acquiring the memory storage structure description information of the output data.
In an embodiment, for the process of obtaining the memory storage structure description information of the output data, for each variable in the output data, the type, the length, and the offset address in the shared memory of the variable may be obtained, so that the type, the length, and the offset address of each obtained variable are used as the memory storage structure description information of the output data.
As shown in fig. 2, the definition of the memory storage structure of the output data in the shared memory includes 5 member variables uuid, x, y, w and h; the type of variable uuid is "array _ int 8"; the type of variable x is "int 32"; the type of variable y is "int 32"; the type of variable h is "int 32"; the offset address of each member variable in the shared memory is 0, 16, 20, 24, 28 respectively.
The length can be calculated according to the offset address of the variable and the type of the variable, namely the length of the variable uuid is 16 bytes; the length of the variable x is 4 bytes; the length of the variable y is 4 bytes; the variable h has a length of 4 bytes, so that the memory storage structure description information shown in fig. 3 can be obtained.
In fig. 3, object is a structure name definition of output data, uuid, x, y, w, h are member variable components, type is a type description of the member variables, size is a variable length calculated in bytes, and offset is an offset address of each member variable in the structure.
It should be noted that, because there are multiple algorithms in the system, for convenience of management, one algorithm registry may be set as a service registry for all algorithms.
Based on this, when the memory storage structure description information of the output data is obtained, the algorithm identifier of the first algorithm and the memory storage structure description information may be added to the algorithm registration center, and at the same time, the transmission queue address of the first algorithm is obtained, and the algorithm identifier of the first algorithm corresponding to the transmission queue address is also added to the algorithm registration center.
The obtained transmission queue address is stored with a transmission queue of a first algorithm, and the address of the algorithm output data in the shared memory is recorded in the queue.
In specific implementation, three management modules can be arranged in the algorithm registration center: registration management, storage structure description management, and algorithm routing management. The algorithm identification of all algorithms in the system registers to the registration management, the memory storage structure description information of all algorithms is added to the storage structure description management, and the transmission queue address of all algorithms is added to the algorithm routing management.
It should be further noted that, when the algorithm is registered in the algorithm registration center, an authentication request of the algorithm may be initiated to the algorithm registration center first, and when an authentication permission key of the algorithm returned by the algorithm registration center is received, the algorithm identifier of the algorithm and the memory storage structure description information are added to the algorithm registration center.
Step 103: and determining the starting address of the variable required by the second algorithm according to the memory storage structure description information, wherein the input of the second algorithm depends on the output data of the first algorithm.
Based on the above step 102, the transmission queue address and the memory storage structure description information of the first algorithm are obtained from the algorithm registration center, and the shared memory address of the output data of the first algorithm is read from the transmission queue address, so that the start address of the required variable is determined according to the read shared memory address and the offset address of the required variable of the second algorithm recorded in the memory storage structure description information.
The shared memory address refers to a read start address of the output data in the shared memory. The variables required for the second algorithm refer to variables that the second algorithm needs to input.
Taking the above fig. 3 as an example, assuming that the read shared memory address is aa, the start address of the data item of the read variable uuid is aa, the start address of the data item of the read variable x is aa +16, the start address of the data item of the read variable y is aa +20, the start address of the data item of the read variable w is aa +24, and the start address of the data item of the read variable h is aa + 28.
Step 104: and reading the data item of the required variable from the shared memory according to the initial address of the required variable and using the data item as the input of the second algorithm.
Specifically, when reading the data item, the data item of the required variable needs to be read from the shared memory according to the start address of the required variable and the length of the required variable recorded in the memory storage structure description information, so as to complete data transfer between algorithms.
To this end, the process shown in fig. 1 is completed, the output data of the first algorithm is stored in the shared memory, the memory storage structure of the output data is described, the second algorithm determines the start address of the variable required by the algorithm according to the memory storage structure description information of the output data, and reads the data item of the required variable from the shared memory according to the start address, so that the data is read through the memory storage structure description without changing the efficient data transmission characteristic of the shared memory, the data is irrelevant to the specific memory storage structure definition, the problem of data transmission relevance among the algorithms can be decoupled, and the problems of transmission compatibility and stability caused by the difference of the data storage structures among different algorithm versions can be solved.
Fig. 4 is a hardware block diagram of an electronic device according to an exemplary embodiment of the present invention, the electronic device including: a communication interface 401, a processor 402, a machine-readable storage medium 403, and a bus 404; wherein the communication interface 401, the processor 402 and the machine-readable storage medium 403 communicate with each other via a bus 404. The processor 402 may execute the inter-algorithm data transfer method within the system described above by reading and executing machine executable instructions in the machine readable storage medium 403 corresponding to the control logic of the inter-algorithm data transfer method within the system, and the specific content of the method is described in the above embodiments and will not be described again here.
The machine-readable storage medium 403 referred to in this disclosure may be any electronic, magnetic, optical, or other physical storage device that can contain or store information such as executable instructions, data, and the like. For example, the machine-readable storage medium may be: volatile memory, non-volatile memory, or similar storage media. In particular, the machine-readable storage medium 403 may be a RAM (Random Access Memory), a flash Memory, a storage drive (e.g., a hard disk drive), any type of storage disk (e.g., an optical disk, a DVD, etc.), or similar storage medium, or a combination thereof.
Corresponding to the embodiment of the inter-algorithm data transmission method in the system, the invention also provides an embodiment of an inter-algorithm data transmission device in the system.
Fig. 5 is a schematic structural diagram of an inter-algorithm data transfer apparatus in a system according to an exemplary embodiment of the present invention, where the inter-algorithm data transfer apparatus in the system can be applied to an electronic device, and as shown in fig. 5, the inter-algorithm data transfer apparatus in the system includes:
a storing module 510, configured to obtain output data of the first algorithm and store the output data in the shared memory; the output data comprises data items of at least one variable;
a description module 520, configured to obtain the memory storage structure description information of the output data;
a determining module 530, configured to determine, according to the memory storage structure description information, a start address of a variable required by a second algorithm, where an input of the second algorithm depends on output data of the first algorithm;
a reading module 540, configured to read a data item of a required variable from the shared memory according to a start address of the required variable, start the second algorithm, and input the read data item as an input of the second algorithm.
In an optional implementation manner, the description module 520 is specifically configured to, for each variable in the output data, obtain a type and a length of the variable, and an offset address in a shared memory; and taking the type, the length and the offset address of each acquired variable as the memory storage structure description information of the output data.
In an alternative implementation, the apparatus further comprises (not shown in fig. 5):
a registration module, configured to add the algorithm identifier of the first algorithm and the memory storage structure description information to an algorithm registration center after the description module 520 obtains the memory storage structure description information of the output data; and acquiring a transmission queue address of the first algorithm, and adding an algorithm identifier of the first algorithm corresponding to the transmission queue address to the algorithm registration center.
In an optional implementation manner, the determining module 530 is specifically configured to obtain a transmission queue address and memory storage structure description information of a first algorithm from the algorithm registry; reading a shared memory address of output data of a first algorithm from the transmission queue address; and determining the starting address of the required variable according to the read shared memory address and the offset address of the variable required by the second algorithm recorded in the memory storage structure description information.
In an optional implementation manner, the reading module 540 is specifically configured to, in the process of reading the data item of the required variable from the shared memory according to the start address of the required variable, read the data item of the required variable from the shared memory according to the start address of the required variable and the length of the required variable recorded in the memory storage structure description information.
The implementation process of the functions and actions of each unit in the above device is specifically described in the implementation process of the corresponding step in the above method, and is not described herein again.
For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the invention. One of ordinary skill in the art can understand and implement it without inventive effort.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method for inter-algorithm data transfer within a system, the method comprising:
acquiring output data of a first algorithm and storing the output data into a shared memory; the output data comprises data items of at least one variable;
acquiring the memory storage structure description information of the output data;
determining the initial address of a variable required by a second algorithm according to the memory storage structure description information, wherein the input of the second algorithm depends on the output data of the first algorithm;
and reading the data item of the required variable from the shared memory according to the starting address of the required variable and using the data item as the input of the second algorithm.
2. The method of claim 1, wherein obtaining the in-memory storage structure description information of the output data comprises:
aiming at each variable in the output data, acquiring the type and the length of the variable and an offset address in a shared memory;
and taking the type, the length and the offset address of each acquired variable as the memory storage structure description information of the output data.
3. The method of claim 1, wherein after obtaining the in-memory storage structure description information for the output data, the method further comprises:
adding the algorithm identification of the first algorithm and the memory storage structure description information to an algorithm registration center;
and acquiring a transmission queue address of the first algorithm, and adding an algorithm identifier of the first algorithm corresponding to the transmission queue address to the algorithm registration center.
4. The method of claim 3, wherein determining the start address of the variable required by the second algorithm according to the memory storage structure description information comprises:
acquiring a transmission queue address and memory storage structure description information of a first algorithm from the algorithm registration center;
reading a shared memory address of output data of a first algorithm from the transmission queue address;
and determining the starting address of the required variable according to the read shared memory address and the offset address of the variable required by the second algorithm recorded in the memory storage structure description information.
5. The method of claim 1, wherein reading the data item of the desired variable from the shared memory according to the start address of the desired variable comprises:
and reading data items of the required variables from the shared memory according to the starting addresses of the required variables and the lengths of the required variables recorded in the memory storage structure description information.
6. An inter-algorithm data transfer apparatus within a system, the apparatus comprising:
the storage module is used for acquiring output data of the first algorithm and storing the output data into the shared memory; the output data comprises data items of at least one variable;
the description module is used for acquiring the memory storage structure description information of the output data;
the determining module is used for determining the starting address of a variable required by a second algorithm according to the memory storage structure description information, wherein the input of the second algorithm depends on the output data of the first algorithm;
and the reading module is used for reading the data item of the required variable from the shared memory according to the initial address of the required variable and taking the data item as the input of the second algorithm.
7. The apparatus according to claim 6, wherein the description module is specifically configured to, for each variable in the output data, obtain a type and a length of the variable, and an offset address in a shared memory; and taking the type, the length and the offset address of each acquired variable as the memory storage structure description information of the output data.
8. The apparatus of claim 6, further comprising:
the registration module is used for adding the algorithm identifier of the first algorithm and the memory storage structure description information to an algorithm registration center after the description module acquires the memory storage structure description information of the output data; and acquiring a transmission queue address of the first algorithm, and adding an algorithm identifier of the first algorithm corresponding to the transmission queue address to the algorithm registration center.
9. The apparatus according to claim 8, wherein the determining module is specifically configured to obtain a transmission queue address and memory storage structure description information of a first algorithm from the algorithm registry; reading a shared memory address of output data of a first algorithm from the transmission queue address; and determining the starting address of the required variable according to the read shared memory address and the offset address of the variable required by the second algorithm recorded in the memory storage structure description information.
10. The apparatus according to claim 6, wherein the reading module is specifically configured to, during the process of reading the data item of the required variable from the shared memory according to the start address of the required variable, read the data item of the required variable from the shared memory according to the start address of the required variable and the length of the required variable recorded in the memory storage structure description information.
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| CN110764924A (en) * | 2018-07-27 | 2020-02-07 | 普天信息技术有限公司 | Inter-core communication method and device of multi-core processor |
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| US20020126673A1 (en) * | 2001-01-12 | 2002-09-12 | Nirav Dagli | Shared memory |
| UA100114C2 (en) * | 2008-11-06 | 2012-11-26 | Анатолий Алексеевич Мельник | Method and device for memory data time access |
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