CN110720212B

CN110720212B - Signal processing circuit and method for pixel array and image sensor

Info

Publication number: CN110720212B
Application number: CN201980001720.0A
Authority: CN
Inventors: 徐荣贵
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2019-09-02
Filing date: 2019-09-02
Publication date: 2022-03-22
Anticipated expiration: 2039-09-02
Also published as: WO2021042231A1; CN110720212A

Abstract

The present disclosure provides a signal processing circuit and a signal processing method for a pixel array, and an image sensor. The signal processing circuit (230) includes a signal generation circuit (232), a comparison circuit (234X), and a counting circuit (236X). The signal generating circuit is used for generating a second ramp signal according to the first ramp signal and N first pixel signals output by the pixel array, wherein N is a positive integer, and the second ramp signal comprises noise information carried by the N first pixel signals. The comparison circuit is coupled to the signal generation circuit and used for comparing a second pixel signal output by the pixel array with the second ramp signal to generate a comparison signal. The counting circuit is coupled to the comparing circuit and used for generating a counting value of the second pixel signal according to the comparison signal. The signal processing circuit can deduct noise information which is commonly included by the active pixel signal and the dark pixel signal in real time.

Description

Signal processing circuit and method for pixel array and image sensor

Technical Field

The present disclosure relates to pixel signal processing technologies, and in particular, to a signal processing circuit and a signal processing method for a pixel array, and an image sensor related thereto.

Background

A pixel array of an image sensor employing active noise reduction (ANC) includes active pixels (active pixels) and dark pixels (dark pixels). The image sensor respectively samples an active pixel signal generated by the active pixel and a dark pixel signal generated by the dark pixel, and subtracts the sampling result of the dark pixel from the sampling result of the active pixel signal so as to reduce noise information included in the sampling result of the active pixel signal. However, since the noise interference received by the pixel array varies with time, and the image sensor samples the dark pixel signal and the active pixel signal at different time points, respectively, the noise information carried by the sampling result of the dark pixel signal is quite different from the noise information carried by the sampling result of the active pixel signal, so that the noise reduction effect is limited.

Therefore, an innovative signal processing scheme is needed, which can effectively reduce the noise information included in the pixel signal.

Disclosure of Invention

An object of the present disclosure is to provide a signal processing circuit and a signal processing method for a pixel array, and an image sensor related thereto, to solve the above problems.

An embodiment of the present disclosure provides a signal processing circuit for a pixel array. The signal processing circuit comprises a signal generating circuit, a comparing circuit and a counting circuit. The signal generating circuit is used for generating a second ramp signal according to a first ramp signal and N first pixel signals output by the pixel array, wherein N is a positive integer, and the second ramp signal comprises noise information carried by the N first pixel signals. The comparison circuit is coupled to the signal generation circuit and is used for comparing a second pixel signal output by the pixel array with the second ramp signal so as to generate a comparison signal. The counting circuit is coupled to the comparing circuit and used for generating a counting value of the second pixel signal according to the comparison signal.

An embodiment of the present disclosure provides an image sensor. The image sensor comprises a pixel array and a signal processing circuit. The pixel array includes a plurality of active pixels and a plurality of dark pixels. The signal processing circuit is coupled to the pixel array and comprises a signal generating circuit, a first comparing circuit, a second comparing circuit, a first counting circuit and a second counting circuit. The signal generating circuit is used for generating a second ramp signal according to a first ramp signal and N dark pixel signals respectively output by N dark pixels in the plurality of dark pixels, wherein N is a positive integer, and the second ramp signal comprises noise information carried by the N dark pixel signals. The first comparison circuit is coupled to at least one of the plurality of active pixels and the signal generation circuit, and is configured to compare an active pixel signal output by the active pixel with the second ramp signal to generate a first comparison signal. The second comparison circuit is coupled to at least one dark pixel of the N dark pixels and the signal generation circuit, and is configured to compare a dark pixel signal output by the dark pixel with the second ramp signal to generate a second comparison signal. The first counting circuit is coupled to the first comparing circuit for generating a count value of the active pixel signal according to the first comparing signal. The second counting circuit is coupled to the second comparing circuit for generating a count value of the dark pixel signal according to the second comparing signal.

An embodiment of the present disclosure provides a signal processing method of a pixel array. The signal processing method comprises the following steps: generating a second ramp signal according to a first ramp signal and N first pixel signals output by the pixel array, wherein N is a positive integer, and the second ramp signal comprises noise information carried by the N first pixel signals; comparing a second pixel signal output by the pixel array with the second ramp signal to generate a comparison signal; and generating a count value of the second pixel signal according to the comparison signal.

Drawings

Fig. 1 is a functional block schematic diagram of an embodiment of an image sensor of the present disclosure.

FIG. 2 is a schematic diagram of an embodiment of at least a portion of the signal processing circuit shown in FIG. 1.

Fig. 3 is a flowchart of an embodiment of a signal processing method of a pixel array of the present disclosure.

Wherein the reference numerals are as follows:

100 image sensor

110 pixel array

120 control circuit

130 signal processing circuit

120 control circuit

130. 230 signal processing circuit

132. 232 signal generating circuit

134₁-134_R+Q、234X、234Y Comparison circuit

136₁-136_R+Q、236X、236Y Counting circuit

242 ramp generator

244 preprocessing circuit

246 signal coupling circuit

247 amplifier

248 switch

302. 304, 306 steps

P_1,1-P_M,RActive pixel

P_1,R+1-P_M,R+QDark pixel

CXP, CXN, CYP, CYN coupling capacitance

C1-CN first capacitance

Ca second capacitance

TC1 first end

Second end of TC2

TR reference terminal

IN61, IN71 first input terminal

IN62, IN72 second input terminal

OUT6, OUT7 output terminal

R1 first resistor

R2 second resistor

VR1 first ramp signal

VR2 second ramp signal

APS₁-APS_RAPSX active pixel signal

DPS₁-DPS_QDPSY dark pixel signal

CR₁-CR_R+QCRX, CRY comparison signal

CT₁-CT_R+Q、CTX、CTY Count value

Detailed Description

Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This specification and the preceding claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Further, the term "coupled" is used herein to include any direct or indirect electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Fig. 1 is a functional block schematic diagram of an embodiment of an image sensor of the present disclosure. The image sensor 100 may include, but is not limited to, a pixel array 110, a control circuit 120, and a signal processing circuit 130, wherein the pixel array 110 includes a plurality of active pixels (also referred to as active pixel units or active pixel circuits) P arranged in M rows and R columns_1,1-P_M,RAnd a plurality of dark pixels arranged in M rows and Q columns (also known as "dark pixels")May be referred to as a dark pixel cell or dark pixel circuit) P_1,R+1-P_M,R+QWherein M, R and Q are both positive integers greater than 1. In this embodiment, a plurality of dark pixels P_1,R+1-P_M,R+QMay be disposed on one side of the pixel array 110 (such as a plurality of active pixels P)_1,1-P_M,RRight side of (c), however, the present disclosure is not limited thereto. For example, a plurality of dark pixels P_1,R+1-P_M,R+QMay be disposed on the other side of the pixel array 110 (such as a plurality of active pixels P)_1,1-P_M,RLeft side of). Also for example, a plurality of dark pixels P_1,R+1-P_M,R+QMay be disposed at one side of the pixel array 110, a plurality of dark pixels P_1,R+1-P_M,R+QMay be disposed on the other side of the pixel array 110.

The control circuit 120 is coupled to the pixel array 110 for controlling operations (e.g., charge transfer, signal reset, signal amplification, and/or readout operations) associated with each pixel in the pixel array 110 to cause each pixel to generate a corresponding pixel signal, such as a plurality of active pixel signals APS₁-APS_ROne or more of which are dark pixel signals DPS₁-DPS_QOne of which.

The signal processing circuit 130 is coupled to the pixel array 110 for compensating the active pixel signals output by the one or more active pixels according to the dark pixel signals output by the one or more dark pixels. In this embodiment, the signal processing circuit 130 may further sample the pixel signal output by the pixel array 110 according to a ramp signal carrying pixel noise to reduce/eliminate noise information carried by the pixel signal in real time, where the pixel noise may be noise information carried by a dark pixel signal or noise information carried by an active pixel signal.

For purposes of illustration, the signal processing scheme of the present disclosure is described below based on the signal processing circuit 130 employing a column-parallel single slope analog-to-digital converter architecture (column-parallel SS ADC architecture). However, the present disclosure is not so limited. For example, in some embodiments, the signal processing circuit 130 may utilize a successive approximation register ADC (SAR ADC) or other type of ADC to implement a column parallel analog-to-digital conversion architecture. As another example, the signal processing circuit 130 may employ a pixel-parallel analog-to-digital conversion architecture (pixel-parallel ADC architecture) to process pixel signals.

In this embodiment, the signal processing circuit 130 includes (but is not limited to) a signal generating circuit 132, a plurality of comparing circuits 134₁-134_R+QAnd a plurality of counter circuits 136₁-136_R+Q. The signal generating circuit 132 is configured to generate a second ramp signal VR2 according to a first ramp signal VR1 and N first pixel signals (N is a positive integer) output by the pixel array 110, wherein the second ramp signal VR2 includes noise information carried by the N first pixel signals. The first ramp signal VR1 may be generated by, but is not limited to, a ramp generator (not shown in fig. 1). The N first pixel signals may be N dark pixels (e.g., a plurality of dark pixels P) included in the pixel array 110_1,R+1-P_M,R+QN dark pixels located in the same row) of the image signal.

For example, the signal generation circuit 132 may couple the N first pixel signals to the first ramp signal VR1 such that the second ramp signal VR2 includes noise information carried by the N first pixel signals. Also for example, the signal generation circuit 132 may pre-process (such as signal coupling or signal averaging) the N first pixel signals to combine (or couple) the N first pixel signals into a pre-processed signal, and couple/superimpose the pre-processed signal onto the first ramp signal VR 1.

Multiple comparison circuits 134₁-134_R+QEach of the comparing circuits is coupled to the signal generating circuit 132 for comparing a second pixel signal output by the pixel array 110 with the second ramp signal VR2 to generate a comparison signal. For example, each comparison circuit (a plurality of comparison circuits 134) coupled to the active pixels₁-134_ROne of them) may be referred to as a first comparison circuit, which may convert an active pixel signal (a plurality of active pixel signals APS)₁-APS_RWhereinOne) is compared with the second ramp signal VR2 to generate a first comparison signal (a plurality of comparison signals CR)₁-CR_ROne of them). Also for example, each comparison circuit (plurality of comparison circuits 134) coupled to a dark pixel_R+1-134_R+QOne of them) may be referred to as a second comparison circuit, which may compare the dark pixel signal (a plurality of dark pixel signals DPS)₁-DPS_QOne of them) is compared with the second ramp signal VR2 to generate a second comparison signal (a plurality of comparison signals CR)_R+1-CR_R+QOne of them).

A plurality of counter circuits 136₁-136_R+QEach counting circuit is coupled to the corresponding comparing circuit for generating a counting value (a plurality of counting values CT) of the corresponding second pixel signal according to the corresponding comparing signal₁-CT_R+QOne of them). For example, each counting circuit (a plurality of counting circuits 136) coupled to the first comparing circuit₁-136_ROne of them) may be referred to as a first counting circuit, which may generate a count value of the active pixel signal according to a corresponding first comparison signal. Also for example, each counting circuit (a plurality of counting circuits 136) coupled to the second comparing circuit_R+1-136_R+QOne of them) may be referred to as a second counting circuit, which may generate a count value of the dark pixel signal according to a corresponding second comparison signal.

In operation, the control circuit 120 can control the pixel array 110 to read out the pixel signals of the pixels located in the same row as the plurality of active pixel signals APS one by one₁-APS_RAnd a plurality of dark pixel signals DPS₁-DPS_Q. The signal generating circuit 132 may be responsive to the first ramp signal VR1 and the plurality of dark pixel signals DPS₁-DPS_QGenerates a second ramp signal VR2 that may carry noise information for the N dark pixel signals. Multiple comparison circuits 134₁-134_REach of the comparison circuits may compare an active pixel signal with the second ramp signal VR2 to generate a comparison signal. With a comparison circuit 134₁For example, when comparing the signal CR₁Indicating that the signal level of the second ramp signal VR2 is reachedSource pixel signal APS₁Is coupled to the comparison circuit 134₁ Counter circuit 136₁The generated count value CT₁Can be used as active pixel signal APS₁The counting result or the analog-to-digital conversion result of (a).

Notably, since the second ramp signal VR2 includes real-time noise information carried by the N dark pixel signals, the active pixel signal APS is used₁Comparing circuit 134 with second ramp signal VR2₁Active pixel signal APS capable of being deducted in real time₁The time-varying noise information included in common with the N dark pixel signals may be referred to as common mode noise (common mode noise). That is, the comparison signal CR₁The time-varying noise information can be greatly reduced, so that the counting circuit 136₁A count result may be generated that is obtained by subtracting the active pixel signal from the time-varying noise information.

In addition, a plurality of comparison circuits 134_R+1-134_R+QEach of the comparison circuits may compare a dark pixel signal with the second ramp signal VR2 to generate a comparison signal. With a comparison circuit 134_R+1For example, when comparing the signal CR_R+1Indicating that the signal level of the second ramp signal VR2 reaches the dark pixel signal DPS₁Is coupled to the comparison circuit 134_R+1 Counter circuit 136_R+1The generated count value CT_R+1Can be used as dark pixel signal DPS₁The analog-to-digital conversion result of (1). Similarly, since the second ramp signal VR2 includes real-time noise information carried by the N dark pixel signals, the dark pixel signal DPS is processed by applying the first ramp signal VR₁Comparing circuit 134 with second ramp signal VR2_R+1The dark pixel signal DPS can be subtracted in real time₁Time-varying noise information. Comparison signal CR_R+1The time-varying noise information can be greatly reduced, so that the counting circuit 136_R+1A count result may be generated after subtracting the time-varying noise information from the dark pixel signal.

Furthermore, since the plurality of comparison circuits 134₁-134_RThe noise information included in the active pixel signal and the dark pixel signal can be subtracted in real time, so that the comparison signals CR₁-CR_RAre comparisons where noise information has been subtracted in real time. Multiple count value CT₁-CT_RThe sampling result of active noise reduction can be obtained without subtracting the count value of the dark pixel signal.

For ease of understanding, the signal processing scheme of the present disclosure is described below in conjunction with the respective comparison and counting circuits for the active pixel columns and dark pixel columns in pixel array 110 shown in fig. 1. However, the present disclosure is not so limited. Any signal processing circuit that can copy/couple at least one pixel signal to the ramp signal to subtract the noise information of the pixel signal varying with time in real time is included in the scope of the present disclosure.

Please refer to fig. 2. Fig. 2 is a schematic diagram of an embodiment of at least a portion of the signal processing circuit 130 shown in fig. 1. The signal processing circuit 230 includes, but is not limited to, a signal generating circuit 232, a plurality of comparing

circuits

234X and 234Y, and a plurality of counting

circuits

236X and 236Y. The signal generating circuit 232 may be an embodiment of the signal generating circuit 132 shown in fig. 1. The comparison circuit 234X may be the comparison circuit 134 shown in FIG. 1₁-134_RIn one embodiment of at least one comparison circuit. The comparison circuit 234Y may be the comparison circuit 134 shown in FIG. 1_R+1-134_R+QIn one embodiment of at least one comparison circuit. The counting circuit 236X may be the counting circuit 136 shown in FIG. 1₁-136_RIn one embodiment of at least one counting circuit. The counting circuit 236X may be the counting circuit 136 shown in FIG. 1_R+1-136_R+QIn one embodiment of at least one counting circuit.

The signal generating circuit 232 includes, but is not limited to, a ramp generator 242, a preprocessing circuit 244, and a signal coupling circuit 246. The ramp generator 242 is configured to generate a first ramp signal VR 1. The ramp generator 242 may be controlled by the control circuit 120 shown in fig. 1. In some embodiments, it is also possible to dispose the ramp generator 242 outside the signal generating circuit 232.

The preprocessing circuit 244 is used to combine (or couple) the N first pixel signals output by the pixel array 110 shown in fig. 1 into a preprocessing signal PPS, wherein the preprocessing signal PPS may include noise information carried by the N first pixel signals. In this embodiment, the N first pixel signals may be composed of, but are not limited to, a plurality of dark pixel signals DPS₁-DPS_QOf which N dark pixel signals. For illustrative purposes, the N dark pixel signals may be labeled as DPS₁-DPS_N。

For example, but not limiting to the disclosure, the pre-processing circuit 244 may copy the N dark pixel signals DPS₁-DPS_NTo generate a preprocessed signal PPS, wherein the preprocessed signal PPS may comprise the N dark pixel signals DPS₁-DPS_NThe noise information carried. As another example, the pre-processing circuit 244 may process N dark pixel signals DPS₁-DPS_NAveraging the respective noise levels to generate a preprocessed signal PPS, wherein the noise level of the preprocessed signal PPS is based on the N dark pixel signals DPS₁-DPS_NThe average of the respective noise levels. Thus, the pre-processed signal PPS may comprise N dark pixel signals DPS₁-DPS_NThe noise information carried.

In this embodiment, the preprocessing circuit 244 includes (but is not limited to) N first capacitors C1-CN and a second capacitor Ca. N first capacitances C1-CN are respectively coupled to the N dark pixel signals DPS₁-DPS_NEach of the first capacitors is coupled between the corresponding dark pixel signal and the first terminal TC1 of the second capacitor Ca. The second terminal TC2 of the second capacitor Ca may be coupled to a reference terminal TR (such as ground).

Signal coupling circuit 246 is coupled to ramp generator 242 and preprocessing circuit 244 to couple preprocessed signal PPS to first ramp signal VR1 to generate second ramp signal VR 2. For example (but not limiting to the present disclosure), the signal coupling circuit 246 may couple or superimpose the pre-processed signal PPS to the first ramp signal VR1 such that the second ramp signal VR2 includes N dark pixel signals DPS₁-DPS_NThe noise information carried. Signal couplerThe first input IN61 of the combining circuit 246 is used for receiving the first ramp signal VR1, and the second input IN62 of the signal coupling circuit 246 is used for receiving the pre-processing signal PPS. IN this embodiment, the second input terminal IN62 of the signal coupling circuit 246 is coupled to one terminal of each of the N first capacitors C1-CN and the first terminal TC1 of the second capacitor Ca for receiving the pre-processed signal PPS. In addition, the output terminal OUT6 of the signal coupling circuit 246 is used for outputting a second ramp signal VR 2.

The signal coupling circuit 246 may be implemented by, but not limited to, a gain stage, and may include a first resistor R1, an amplifier 247, and a second resistor R2. The first input terminal IN71 of the amplifier 247 is coupled to the first ramp signal VR1 through a first resistor R1, and the second input terminal IN72 of the amplifier 247 serves as the second input terminal IN62 of the signal coupling circuit 246. The output OUT7 of the amplifier 247 may serve as the output OUT6 of the signal coupling circuit 246. IN addition, the second resistor R2 is coupled between the first input terminal IN71 and the output terminal OUT7 of the amplifier 247.

The comparison circuit 234X may be implemented by a differential comparator (differential comparator) for comparing an active pixel signal APSX (multiple active pixel signals APS)₁-APS_ROne of them) is compared with the second ramp signal VR2 to generate a comparison signal CRX. In this embodiment, the comparison circuit 234X may be coupled to the active pixel signal APSX through the coupling capacitor CXN to receive an ac signal component of the active pixel signal APSX. In addition, the comparison circuit 234X may be coupled to the second ramp signal VR2 through a coupling capacitor CXP to receive the ac signal component of the second ramp signal VR 2.

Similarly, the comparison circuit 234Y may be implemented by a differential comparator for comparing a dark pixel signal DPSY (multiple dark pixel signals DPS)₁-DPS_QOne of them) is compared with the second ramp signal VR2 to generate a comparison signal CRY. The comparing circuit 234Y may be coupled to the dark pixel signal DPSY and the second ramp signal VR2 through a coupling capacitor CYN and a coupling capacitor CYP, respectively, to receive the ac signal components of the dark pixel signal DPSY and the second ramp signal VR 2. In this embodiment, the dark pixel signal DPSY may be N dark pixel signals DPS₁-DPS_NOne of which.

IN this embodiment, the signal processing circuit 230 may further include a switch 248 coupled between a reference voltage Vref and the second input terminal IN62 of the signal coupling circuit 246. The switch 248 is used to reset the second input terminal IN62 to the reference voltage Vref.

IN operation, the switch 248 resets the second input terminal IN62 to the reference voltage Vref, thereby resetting the voltage at the output terminal OUT6 of the signal coupling circuit 246. Next, the switch 248 may be opened and the signal processing circuit 230 may correlate the active pixel signal APSX and the dark pixel signal DPSY. The preprocessing circuit 244 may generate the preprocessing signal PPS using the N first capacitors C1-CN and the second capacitor Ca, so that the signal coupling circuit 246 may generate the signal carrying the N dark pixel signals DPS₁-DPS_NAnd a second ramp signal VR2 of the noise information. The second ramp signal VR2 may be represented by the following equation:

wherein C1]-C[N]Respectively representing the capacitance values, Ca, of the N first capacitors C1-CN]Can represent the capacitance of the second capacitor Ca, and p 1]-p[N]May represent N dark pixel signals DPS, respectively₁-DPS_NThe signal value of (a). It is noted that the second ramp signal VR2 includes N dark pixel signals DPS₁-DPS_NThe real-time noise information carried.

By comparing the active pixel signal APSX with the second ramp signal VR2, the comparison circuit 234X subtracts the active pixel signal APSX and the N dark pixel signals DPS in real time₁-DPS_NTime-varying noise information included in common. For example, but not limiting to the present disclosure, N dark pixel signals DPS₁-DPS_NA certain dark pixel signal DPS_iSignal value p [ i ] of](i is a positive integer less than or equal to N) can be represented by the following formula:

p[i]＝Vncm+Vn[i]

where Vncm may represent noise(s) included in both the active pixel signal and the dark pixel signalE.g., common mode noise), Vn i]May represent a dark pixel signal DPS_iOf the other(s) (which may be dynamically changing over time).

In the case that each of the N first capacitors C1-CN has the same capacitance value, and the capacitance value Ca of the second capacitor Ca is equal to the sum of the capacitance values of the N first capacitors C1-CN, the second ramp signal VR2 can be represented by the following formula:

in the case where the first resistor R1 and the second resistor R2 are implemented by resistors having the same resistance value, the second ramp signal VR2 can be further expressed as follows:

where Vn may represent the respective significant values of N noise levels Vn [1] -Vn [ N ]:

therefore, when the second ramp signal VR2 reaches the signal level of the active pixel signal APSX, the comparing circuit 234X can subtract the noise level Vncm of the noise included in the active pixel signal APSX and the dark pixel signal in real time. It is noted that the number of pixels when used to reproduce the noise information of the dark pixel signal (i.e., N dark pixel signals DPS)₁-DPS_NN) is sufficient, the signal component of the second ramp signal VR2

Negligible with respect to the signal component (Vncm-VR1), so that most (or all) of the noise information in the active pixel signal APSX due to pixel noise can be subtracted by the comparison circuit 234X.

Similarly, the comparison circuit 234Y subtracts the dark pixel signal DPSY from the N dark pixel signals DPS in real time by comparing the dark pixel signal DPSY with the second ramp signal VR2₁-DPS_NTime-varying noise information included in common. For example, when the second ramp signal VR2 reaches the signal level of the dark pixel signal DPSY, the comparing circuit 234Y may subtract the noise level Vncm of the dark pixel signal in real time. The number of pixels when used to reproduce the noise information of the dark pixel signal (i.e., N number of dark pixel signals DPS)₁-DPS_NN), most (or all) of the noise information generated by the pixel noise in the dark pixel signal DPSY can be subtracted by the comparing circuit 234Y. That is, when the second ramp signal VR2 reaches the signal level of the dark pixel signal DPSY, the signal level of the comparison signal CRY may be equal to or substantially equal to zero.

It should be noted that, since the signal processing circuit 230 can subtract the noise information included in the active pixel signal and the dark pixel signal in real time, even if the signal processing circuit 230 samples the active pixel signal APSX and the dark pixel signal DPSY at different time points (i.e., the signal level of the comparison signal CRX and the signal level of the comparison signal CRY are inverted at different time points), the comparison signal CRX and the comparison signal CRY both subtract (or almost subtract) the noise information varying with time. That is, both the count value CTX and the count value CTY have subtracted (or almost subtracted) the noise information that changes with time.

Furthermore, since the count value CTX generated by the counting circuit 236X subtracts (or almost subtracts) the noise information included in the active pixel signal and the dark pixel signal, the signal processing circuit 230 may not need to subtract the count value CTX and the count value CTY to perform a digital active noise reduction (digital ANC). That is, the signal processing circuit 230 is a signal processing circuit that can perform an analog active noise reduction operation (analog ANC).

The foregoing is for the purpose of illustration and is not intended to limit the scope of the disclosure. In some embodiments, N dark pixel signals DPS₁-DPS_NAnd may also be used to eliminate/reduce noise information in other dark pixel signals.For example, the dark pixel signal DPSY to which the comparison circuit 234Y is coupled may be the plurality of dark pixel signals DPS shown in FIG. 1₁-DPS_QAny one of the dark pixel signals.

In some embodiments, the noise information included in common by the active pixel signal and the dark pixel signal may also be replicated using at least one active pixel signal. For example, the pre-processing circuit 244 may apply the APS to the plurality of active pixel signals shown in FIG. 1₁-APS_RThe N active pixel signals are preprocessed to combine the N active pixel signals into a preprocessed signal PPS, wherein the preprocessed signal PPS may include noise information carried by the N active pixel signals.

In some embodiments, the preprocessing circuit 244 may employ other different circuit structures to generate the preprocessing signal PPS carrying the pixel noise information. In some embodiments, the signal coupling circuit 246 may employ other different circuit configurations to couple/superimpose the pre-processed signal PPS to the first ramp signal VR 1. Furthermore, in some embodiments, the signal coupling circuit 246 may directly superimpose the pre-processed signal PPS on the first ramp signal VR 1. All such alternatives are included within the scope of the present disclosure.

Fig. 3 is a flowchart of an embodiment of a signal processing method of a pixel array of the present disclosure. If the results obtained are substantially the same, the steps do not have to be performed in the order shown in fig. 3. For example, certain steps may be interposed therein. For convenience of description, the signal processing method shown in fig. 3 will be described below in conjunction with the signal processing circuit 230 shown in fig. 2. However, it is feasible to apply the signal processing method shown in fig. 3 to the signal processing circuit (such as the signal processing circuit 130 shown in fig. 1) using other signal processing circuits. The signal processing method shown in fig. 3 can be briefly summarized as follows.

Step 302: and generating a second ramp signal according to a first ramp signal and N first pixel signals output by the pixel array, wherein N is a positive integer, and the second ramp signal comprises noise information carried by the N first pixel signals. For example, the signal generating circuit 232 generates the first ramp signal VR1 and N dark pixelsSignal DPS₁-DPS_NA second ramp signal VR2 is generated.

Step 304: comparing a second pixel signal output by the pixel array with the second ramp signal to generate a comparison signal. For example, the comparison circuit 234X compares the active pixel signal APSX with the second ramp signal VR2 to generate a comparison signal CRX. For another example, the comparison circuit 234Y compares the dark pixel signal DPSY with the second ramp signal VR2 to generate a comparison signal CRY.

Step 306: and generating a count value of the second pixel signal according to the comparison signal. For example, the counting circuit 236X generates a count value CTX of the active pixel signal APSX according to the comparison signal CRX. For another example, the counting circuit 236Y generates a count value CTY of the dark pixel signal DPSY according to the comparison signal CRY.

In some embodiments, in step 302, an averaging operation may be performed on the noise levels of the N first pixel signals to generate a pre-processed signal, which is coupled to the first ramp signal to generate the second ramp signal. For example, the pre-processing circuit 244 may employ a plurality of first capacitors C1-CN and second capacitors Ca to align the N dark pixel signals DPS₁-DPS_NRespective noise levels perform an averaging operation to reproduce the N dark pixel signals DPS₁-DPS_NThereby generating the pre-processed signal PPS. The signal coupling circuit 246 may couple the pre-processed signal PPS to the first ramp signal VR1 to generate the second ramp signal VR 2. Furthermore, in some embodiments, the second pixel signal employed in step 304 may be at least one of the N first pixel signals employed in step 302.

Since the details of each step in the signal processing method shown in fig. 3 can be understood by those skilled in the art after reading the paragraphs related to fig. 1 and fig. 2, further description is omitted here for brevity.

The above description is only an example of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A signal processing circuit for a pixel array, comprising:

the signal generating circuit is used for generating a second ramp signal according to the first ramp signal and N first pixel signals output by the pixel array, wherein N is a positive integer, and the second ramp signal comprises real-time noise information carried by the N first pixel signals;

a comparison circuit coupled to the signal generation circuit for comparing the second pixel signal output by the pixel array with the second ramp signal to generate a comparison signal; and

a counting circuit coupled to the comparing circuit for generating a count value of the second pixel signal according to the comparison signal;

wherein the signal generating circuit comprises:

the preprocessing circuit is used for combining the N first pixel signals into a preprocessing signal, and the preprocessing signal comprises real-time noise information carried by the N first pixel signals; and

a signal coupling circuit coupled to the preprocessing circuit for coupling the preprocessed signal to the first ramp signal to generate the second ramp signal, wherein during a period in which the signal coupling circuit outputs the second ramp signal, the signal coupling circuit is configured to couple the preprocessed signal received during the period to the first ramp signal to generate the second ramp signal in real time, such that the second ramp signal includes real-time noise information carried by the N first pixel signals output by the pixel array during the period.

2. The signal processing circuit of claim 1, wherein the second pixel signal is at least one of the N first pixel signals.

3. The signal processing circuit of claim 1, wherein the N first pixel signals are N dark pixel signals generated by each of N dark pixels included in the pixel array.

4. The signal processing circuit of claim 1, wherein the second pixel signal is a dark pixel signal generated by a dark pixel comprised by the pixel array or an active pixel signal generated by an active pixel comprised by the pixel array.

5. The signal processing circuit of any of claims 1-4, wherein a first input of the signal coupling circuit is to receive the first ramp signal, a second input of the signal coupling circuit is to receive the pre-processed signal, and an output of the signal coupling circuit is to output the second ramp signal.

6. The signal processing circuit of claim 5, wherein the pre-processing circuit is configured to perform an averaging operation on the noise levels of the N first pixel signals to generate the pre-processed signal, wherein the noise level of the pre-processed signal is determined according to an average of the noise levels of the N first pixel signals.

7. The signal processing circuit of claim 5, wherein the pre-processing circuit comprises:

n first capacitors respectively coupled to the N first pixel signals, wherein each first capacitor is coupled between the corresponding first pixel signal and the second input terminal of the signal coupling circuit; and

the second capacitor is coupled between the reference end and the second input end of the signal coupling circuit.

8. The signal processing circuit of claim 7, wherein each of the N first capacitors has the same capacitance value, and the capacitance value of the second capacitor is equal to the sum of the capacitance values of the N first capacitors.

9. The signal processing circuit of claim 5, wherein the signal coupling circuit comprises:

a first resistor;

an amplifier, wherein a first input of the amplifier is coupled to the first ramp signal through the first resistor, a second input of the amplifier serves as a second input of the signal coupling circuit, and an output of the amplifier serves as an output of the signal coupling circuit; and

the second resistor is coupled between the first input end of the amplifier and the output end of the amplifier.

10. The signal processing circuit of claim 9, wherein the first resistor and the second resistor have the same resistance value.

11. The signal processing circuit of claim 5, wherein the signal generation circuit further comprises:

a switch coupled between a reference voltage and the second input terminal of the signal coupling circuit for resetting the second input terminal of the signal coupling circuit to the reference voltage.

12. An image sensor, comprising:

a pixel array including a plurality of active pixels and a plurality of dark pixels; and

a signal processing circuit coupled to the pixel array, the signal processing circuit comprising:

the signal generating circuit is used for generating a second ramp signal according to a first ramp signal and N dark pixel signals respectively output by N dark pixels in the plurality of dark pixels, wherein N is a positive integer, and the second ramp signal comprises real-time noise information carried by the N dark pixel signals;

a first comparison circuit coupled to at least one of the plurality of active pixels and the signal generation circuit for comparing an active pixel signal output by the active pixel with the second ramp signal to generate a first comparison signal;

a second comparison circuit coupled to at least one of the N dark pixels and the signal generation circuit for comparing a dark pixel signal output by the dark pixel with the second ramp signal to generate a second comparison signal;

a first counting circuit coupled to the first comparing circuit for generating a count value of the active pixel signal according to the first comparing signal; and

a second counting circuit, coupled to the second comparing circuit, for generating a count value of the dark pixel signal according to the second comparing signal:

wherein the signal generating circuit comprises:

the preprocessing circuit is used for merging the N dark pixel signals into a preprocessing signal, and the preprocessing signal comprises real-time noise information carried by the N dark pixel signals; and

a signal coupling circuit, coupled to the preprocessing circuit, for coupling the preprocessed signal to the first ramp signal to generate the second ramp signal, wherein during a period in which the signal coupling circuit outputs the second ramp signal, the signal coupling circuit is configured to couple the preprocessed signal received during the period to the first ramp signal to generate the second ramp signal in real time, so that the second ramp signal includes real-time noise information carried by the N dark pixel signals respectively output by the N dark pixels during the period.

13. The image sensor of claim 12, wherein a first input of the signal coupling circuit is configured to receive the first ramp signal, a second input of the signal coupling circuit is configured to receive the pre-processed signal, and an output of the signal coupling circuit is configured to output the second ramp signal.

14. The image sensor of claim 13, wherein the pre-processing circuit comprises:

n first capacitors respectively coupled to the N dark pixel signals, wherein each first capacitor is coupled between the corresponding dark pixel signal and the second input terminal of the signal coupling circuit; and

15. The image sensor of claim 13 or 14, wherein the signal coupling circuit comprises:

a first resistor;

16. The image sensor of claim 13 or 14, wherein the signal generation circuit further comprises:

17. A signal processing method of a pixel array, comprising:

generating a second ramp signal according to the first ramp signal and N first pixel signals output by the pixel array, wherein N is a positive integer, and the second ramp signal comprises real-time noise information carried by the N first pixel signals;

comparing a second pixel signal output by the pixel array with the second ramp signal to generate a comparison signal; and

generating a count value of the second pixel signal according to the comparison signal;

wherein the step of generating the second ramp signal according to the first ramp signal and the N first pixel signals comprises:

merging the N first pixel signals into a preprocessed signal, wherein the preprocessed signal comprises real-time noise information carried by the N first pixel signals; and

during a period in which the N first pixel signals are output by the pixel array, coupling the preprocessed signals received during the period to the first ramp signal to generate the second ramp signal in real time, such that the second ramp signal includes real-time noise information carried by the N first pixel signals output by the pixel array during the period in which the second ramp signal is output.

18. The signal processing method of claim 17, wherein the second pixel signal is at least one of the N first pixel signals.

19. The signal processing method of claim 17, wherein the N first pixel signals are N dark pixel signals generated by each of N dark pixels included in the pixel array.

20. The signal processing method of any one of claims 17 to 19, wherein the step of combining the N first pixel signals into the preprocessed signal comprises:

performing an averaging operation on noise levels of the N first pixel signals to generate the preprocessed signal, wherein the noise level of the preprocessed signal is determined according to an average of the noise levels of the N first pixel signals.

21. The signal processing method of any of claims 17 to 19, wherein the step of coupling the pre-processed signal to the first ramp signal to generate the second ramp signal comprises:

the first ramp signal and the pre-processed signal are input to a first input and a second input of an amplifier, respectively, to generate the second ramp signal at an output of the amplifier.

22. The signal processing method of claim 21, further comprising:

resetting the second input of the amplifier to a reference voltage before the pre-processed signal is input to the second input of the amplifier.