CN110718201A

CN110718201A - Liquid crystal driving chip capable of reducing pin number

Info

Publication number: CN110718201A
Application number: CN201911018192.8A
Authority: CN
Inventors: 许源
Original assignee: Xiamen Feiyinghai Technology Co Ltd
Current assignee: Xiamen Feiyinghai Technology Co Ltd
Priority date: 2019-10-24
Filing date: 2019-10-24
Publication date: 2020-01-21
Anticipated expiration: 2039-10-24
Also published as: CN110718201B

Abstract

The invention discloses a liquid crystal driving chip for reducing the number of pins, which belongs to the technical field of liquid crystal driving chips and comprises the following components: the LCD driving and biasing circuit, the display RAM, the time base generator and the serial interface module are all connected with the serial interface module, the display RAM is connected with the LCD driving and biasing circuit, the time base generator is connected with the LCD driving and biasing circuit, 4 public electrodes COM and 12 segment electrodes SEG are arranged on the LCD driving and biasing circuit, each public electrode COM corresponds to 3 COM output ends, and each segment electrode SEG corresponds to 1 SEG output end. The liquid crystal driving chip with the reduced pin number reduces the pin number and the cost.

Description

Liquid crystal driving chip capable of reducing pin number

Technical Field

The invention belongs to the technical field of liquid crystal driving chips, and particularly relates to a liquid crystal driving chip capable of reducing the number of pins.

Background

The total driving segment number of the liquid crystal driving chips is equal to the product of the COM number and the SEG number, and the pin number of the driving liquid crystal chip is equal to the sum of the COM number and the SEG number. Taking HT1621 as an example, the COM number is 4, the SEG number is 32, the total number of drivable segments is 4 × 32 ═ 128, and the number of pins driving the liquid crystal sheet is 4 + 32 ═ 36. In the electronic scale market, 3 display windows are usually driven, namely a weight window, a unit price window and a money amount window, wherein the weight window is 5 bits, the unit price window is 5 bits, the money amount window is 6 bits, and the total required number of segments of the 3 display windows is (5 + 6) × 8 ═ 128, so that HT1621 just meets the application requirement. With the increasing weighing precision of electronic scales, for example, from 1g to 0.5g, the number of display bits in the weight window needs to be increased from 5 bits to 6 bits in order to display a smaller weight, and the total number of segments of the display window in the high-precision electronic scales needs to be (6 + 6) × 8 ═ 144. Obviously, HT1621 cannot meet its application requirements, and therefore HT1622 is selected, the COM number of which is increased to 8, the SEG number of which is reduced to 16 (the SEG number of HT1621 is 32), the total number of segments which can be driven is 8 × 16 ═ 144, and the number of pins driving the lc panel is 8 + 16 ═ 24. Although the number of pins of the HT1622 driven liquid crystal panel is reduced to 24, the HT1622 driven liquid crystal panel needs 8 COMs, and compared with 4 COMs of HT1621, the liquid crystal panels of the HT1622 driven liquid crystal panel and the HT1621 driven liquid crystal panel cannot be used in common, so that the cost of the high-precision electronic scale is greatly increased.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention aims to provide a liquid crystal driving chip with reduced pin number, which increases the number of COM groups, reduces the number of SEGs, reduces the pin number relative to HT1621, and greatly reduces the cost by adopting a liquid crystal chip with 4 COMs compared with 8 COMs of HT 1622.

In order to achieve the purpose, the invention adopts the following technical scheme:

the invention provides a liquid crystal driving chip for reducing the number of pins, which comprises: the LCD driving and biasing circuit is used for generating driving waveforms and driving voltages of a common electrode COM and segment electrodes SEG, the display RAM is used for storing display data, the time base generator is used for generating a clock, all modules in a driving chip work cooperatively, the serial interface module is used for communicating with an external singlechip, updating the value of the display RAM and controlling the working states of the LCD driving and biasing circuit and the time base generator, the LCD driving and biasing circuit, the display RAM and the time base generator are all connected with the serial interface module, the display RAM is connected with the LCD driving and biasing circuit, the time base generator is connected with the LCD driving and biasing circuit, 4 common electrodes COM and 12 segment electrodes SEG are arranged on the LCD driving and biasing circuit, each common electrode COM corresponds to 3 paths of COM output ends, and each segment electrode SEG corresponds to 1 path of SEG output ends.

Preferably, the COM output ends are divided into 3 groups of 12 paths, namely COMA0-COMA3, COMB0-COMB3 and COMC0-COMC 3.

Preferably, the LCD driving and biasing circuit includes two driving modes, LINE and FRAME.

Preferably, the display RAM is internally composed of 12 RAM cells with consecutive addresses, from the cell with address 0 to the cell with address 11, corresponding to SEG outputs SEG0 to SEG11, respectively.

Preferably, the serial interface module is respectively connected to the serial clock input terminal SCK and the serial data terminal SDA.

Preferably, the driving chip is respectively connected to the common ground GND and the voltage input terminal VDD.

The invention has the beneficial effects that:

1. on the premise of adopting 4 COM liquid crystal chips, 3 groups of COM output ends are arranged, the number of SEGs is reduced, and the number of pins is reduced compared with that of HT 1621.

2. Compared with 8 COMs of HT1622, the liquid crystal plate with 4 COMs is adopted, so that the cost is greatly reduced.

Drawings

Fig. 1 is a block diagram of the overall structure of an embodiment of the present invention.

FIG. 2 is a diagram showing a RAM structure according to an embodiment of the present invention.

Fig. 3 is a logic diagram of a driving waveform according to an embodiment of the present invention.

Fig. 4 is an explanatory view of the application of the multi-window liquid crystal panel according to the embodiment of the present invention.

FIG. 5 is a pin diagram of a chip according to an embodiment of the present invention.

Detailed Description

The invention will now be further described with reference to the accompanying drawings and detailed description.

As shown in fig. 1 to 5, the liquid crystal driving chip with reduced pin count provided in this embodiment includes:

an LCD driving and biasing circuit (LCDDriver) for generating driving waveforms and driving voltages for the common electrode COM and the segment electrode SEG, as shown in fig. 3, includes two driving modes of LINE and FRAME, where V0= GND, V1=1/3 × VDD, V2=2/3 × VDD, and V3= VDD. As shown in fig. 3, the driving waveform cyclically drives SEGs 0-11 sequentially for 12 units in units of driving 1 SEG, wherein each SEG and 3 groups COM constitute 12 segments of RAM, and the driving 1 SEG is divided into 8 sections, i.e., COMA, COMB, and COMC are driven simultaneously instead of sequentially driving COMA, COMB, and COMC every time driving 1 SEG unit.

And the display RAM (display RAM) is used for storing display data, the display RAM is mainly used for storing values of all the segments, the value is 1 to represent the display segment, and the value is 0 to represent the non-display segment. As shown in fig. 2, the 12 SEGs and the 3 COM groups of the embodiment constitute 144 segments of storage space.

The Time base generator (Time base generator) is used for generating a clock and driving all modules in the chip to cooperatively work, and when the chip is in a power-saving mode, the clock is turned off, all circuits stop working, and the power consumption is reduced to the lowest.

And a Serial Interface module (Serial Interface) for communicating with an external singlechip, updating and displaying the value of the RAM, and controlling the working states of the LCD driving and biasing circuit and the time base generator.

The LCD driving and biasing circuit, the display RAM and the time base generator are all connected with the serial interface module, the display RAM is connected with the LCD driving and biasing circuit, the time base generator is connected with the LCD driving and biasing circuit, 4 public electrodes COM and 12 segment electrodes SEG are arranged on the LCD driving and biasing circuit, each public electrode COM corresponds to 3 paths of COM output ends, and each segment electrode SEG corresponds to 1 path of SEG output ends.

Furthermore, the COM output ends are divided into 3 groups of 12 paths, namely COMA0-COMA3, COMB0-COMB3 and COMC0-COMC 3.

Further, the display RAM is internally composed of 12 RAM cells with consecutive addresses, and the RAM cells from the cell with address 0 to the cell with address 11 correspond to SEG outputs SEG0 to SEG11, respectively.

Further, the serial interface module is respectively connected to the serial clock input terminal SCK and the serial data terminal SDA.

Furthermore, the driving chip is respectively connected to the common ground terminal GND and the voltage input terminal VDD.

As shown in FIG. 4, on the premise of adopting liquid crystal plates with 4 COMs, on the basis of 1 original group of COM output ends COMA0-COMA3, 2 groups of COMB0-COMB3 and COMC0-COMC3 are added, SEG0-SEG31 is reduced to SEG0-SEG11, the total driving sections are (4 × 12) × 3 ═ 144, and the invention can drive common electronic scales with a 5-bit weight window, a 5-bit unit price window and a 6-bit sum window and high-precision electronic scales with a 6-bit weight window, a 6-bit unit price window and a 6-bit sum window. Therefore, compared with 36 pins of HT1621, the number of pins of the driving liquid crystal plate designed by the invention is 4 + 12-24, and the number of pins of 1/3 is reduced; compared with 8 COMs of HT1622, the liquid crystal display panel can adopt 4 COMs by adopting the design of the invention, thereby greatly reducing the cost of the high-precision electronic scale.

Those not described in detail in this specification are within the skill of the art. The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A liquid crystal driving chip reducing the number of pins includes:

an LCD driving and biasing circuit for generating driving waveforms and driving voltages for the common electrode COM and the segment electrode SEG;

a display RAM for storing display data;

the time base generator is used for generating a clock and driving all modules in the chip to work cooperatively;

the serial interface module is used for communicating with an external singlechip, updating and displaying the value of the RAM and controlling the working states of the LCD driving and biasing circuit and the time base generator;

the LCD driving and biasing circuit, the display RAM and the time base generator are all connected with the serial interface module;

the display RAM is connected with the LCD driving and biasing circuit;

the time base generator is connected with the LCD driving and biasing circuit, and is characterized in that:

4 common electrodes COM and 12 segment electrodes SEG are arranged on the LCD driving and biasing circuit;

each common electrode COM corresponds to 3 paths of COM output ends;

each segment electrode SEG corresponds to 1 SEG output terminal.

2. The liquid crystal driving chip with reduced pin count according to claim 1, wherein:

the COM output ends are divided into 3 groups of 12 paths, namely COMA0-COMA3, COMB0-COMB3 and COMC0-COMC 3.

3. The liquid crystal driving chip with reduced pin count according to claim 1, wherein:

the LCD driving and biasing circuit comprises two driving modes of LINE and FRAME.

4. The liquid crystal driving chip with reduced pin count according to claim 1, wherein:

the display RAM is internally composed of 12 RAM units with continuous addresses, and the RAM units from the unit with the address of 0 to the unit with the address of 11 respectively correspond to SEG output ends SEG0 to SEG 11.

5. The liquid crystal driving chip with reduced pin count according to claim 1, wherein:

the serial interface module is respectively connected with a serial clock input end SCK and a serial data end SDA.

6. The liquid crystal driving chip with reduced pin count according to claim 1, wherein:

the driving chip is respectively connected to a common ground terminal GND and a voltage input terminal VDD.