CN110716891A - Forced downloading method, circuit, terminal equipment and data line - Google Patents
Forced downloading method, circuit, terminal equipment and data line Download PDFInfo
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- CN110716891A CN110716891A CN201910955625.6A CN201910955625A CN110716891A CN 110716891 A CN110716891 A CN 110716891A CN 201910955625 A CN201910955625 A CN 201910955625A CN 110716891 A CN110716891 A CN 110716891A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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Abstract
The application is applicable to the technical field of terminals and provides a forced downloading method, a circuit, terminal equipment and a data line. According to the embodiment of the application, when the Type-C female socket is connected with a data line, voltage values of a first channel configuration signal pin and a second channel configuration signal pin are detected; calculating the resistance value of at least one pull-up resistor electrically connected with the first channel configuration signal pin and/or the second channel configuration signal pin in the data line according to the voltage values of the first channel configuration signal pin and the second channel configuration signal pin; when the resistance value of at least one pull-up resistor is equal to the preset resistance value, the application processor is triggered to enter a forced downloading mode, the data line of the pull-up resistor with the preset resistance value is connected through the Type-C female socket, the forced downloading mode can be entered, the short circuit test point does not need to be dismounted, and the operation is simple.
Description
Technical Field
The application belongs to the technical field of terminals, and particularly relates to a forced downloading method, a circuit, terminal equipment and a data line.
Background
With the continuous development of terminal technology, terminal devices such as mobile phones, tablet computers, smart wristbands and personal digital assistants come out endlessly, and great convenience is brought to daily production and life of people. In the process of research and development before leaving factory or in the process of use after leaving factory, when the problems of abnormal halt and incapability of starting up due to instability of the running software program occur, the terminal equipment can be started up only by downloading the software program again. At present, a commonly used method for controlling terminal equipment to download forcibly is to reserve a test point on a main board of the terminal equipment, and to make the terminal equipment enter a forced downloading mode by short-circuit of the test point, which can be realized only by disassembling the terminal equipment, and the operation is complex.
Content of application
In view of this, embodiments of the present application provide a forced download method, a circuit, a terminal device, and a data line, so as to solve the problem in the prior art that the terminal device enters a forced download mode by means of short-circuiting a test point, which can be realized only by disassembling the device, and is complicated to operate.
A first aspect of an embodiment of the present application provides a forced download circuit, including:
a Type-C female seat;
an application processor;
the power management chip is electrically connected with the first channel configuration signal pin, the second channel configuration signal pin and the application processor of the Type-C female socket and is used for detecting the voltage values of the first channel configuration signal pin and the second channel configuration signal pin when the Type-C female socket is connected with a data line; calculating the resistance value of at least one pull-up resistor electrically connected with the first channel configuration signal pin and/or the second channel configuration signal pin in the data line according to the voltage values of the first channel configuration signal pin and the second channel configuration signal pin; and when the resistance value of the at least one pull-up resistor is equal to a preset resistance value, triggering the application processor to enter a forced downloading mode.
A second aspect of an embodiment of the present application provides a terminal device, including the forced download circuit according to the first aspect of an embodiment of the present application.
A third aspect of the embodiments of the present application provides a data line, which is applied to the forced download circuit according to the first aspect of the embodiments of the present application or the terminal device according to the second aspect of the embodiments of the present application, where the data line includes a Type-a male header and a Type-C male header matching with the Type-C female socket;
the Type-C male connector comprises a data line positive signal pin, a data line negative signal pin and one or two channel configuration signal pins, and at least one pull-up resistor is connected in series between each channel configuration signal pin of the Type-C male connector and the power supply signal pin of the Type-A male connector.
A fourth aspect of the present embodiment provides a forced download method, including:
when the Type-C female socket is connected with a data line, detecting voltage values of a first channel configuration signal pin and a second channel configuration signal pin of the Type-C female socket;
calculating the resistance value of at least one pull-up resistor electrically connected with the first channel configuration signal pin and/or the second channel configuration signal pin in the data line according to the voltage values of the first channel configuration signal pin and the second channel configuration signal pin;
and when the resistance value of the at least one pull-up resistor is equal to the preset resistance value, triggering the application processor to enter a forced downloading mode.
According to the embodiment of the application, when the Type-C female socket is connected with a data line, voltage values of a first channel configuration signal pin and a second channel configuration signal pin are detected; calculating the resistance value of at least one pull-up resistor electrically connected with the first channel configuration signal pin and/or the second channel configuration signal pin in the data line according to the voltage values of the first channel configuration signal pin and the second channel configuration signal pin; when the resistance value of at least one pull-up resistor is equal to the preset resistance value, the application processor is triggered to enter a forced downloading mode, the data line of the pull-up resistor with the preset resistance value is connected through the Type-C female socket, the forced downloading mode can be entered, the short circuit test point does not need to be dismounted, and the operation is simple.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic diagram of a first structure of a forced download circuit provided in an embodiment of the present application;
FIG. 2 is a diagram illustrating a second structure of a forced download circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a third structure of a forced download circuit according to an embodiment of the present application;
FIG. 4 is a schematic structural diagram of a data line provided in an embodiment of the present application;
fig. 5 is a schematic flowchart of a forced download method according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "comprises" and "comprising," and any variations thereof, in the description and claims of this application and the drawings described above, are intended to cover non-exclusive inclusions. For example, a process, method, or system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," and "third," etc. are used to distinguish between different objects and are not used to describe a particular order.
The embodiment of the application provides a forced downloading circuit, which is applied to a terminal device and used for enabling the terminal device to enter a forced downloading mode when the terminal device is halted or cannot be started.
In application, the terminal device may be a mobile terminal such as a mobile phone, a tablet computer, an intelligent bracelet, and a personal digital assistant.
As shown in fig. 1, the forced download circuit 100 provided in this embodiment includes:
a Type-C female seat 10;
an Application Processor (AP) 20;
a Power Management chip (PMIC) 30 electrically connected to the first Channel Configuration signal pin CC1, the second Channel Configuration signal pin CC2 of the Type-C mother socket 10 and the application processor 20, for detecting the voltage values of the first Channel Configuration signal pin CC1 and the second Channel Configuration signal pin CC2 of the Type-C mother socket 10 when the Type-C mother socket 10 is connected to the data line; calculating the resistance value of at least one pull-up resistor electrically connected with the first channel configuration signal pin CC1 and/or the second channel configuration signal pin CC2 in the data line according to the voltage values of the first channel configuration signal pin CC1 and the second channel configuration signal pin CC 2; when the resistance value of at least one pull-up resistor is equal to the preset resistance value, the application processor 20 is triggered to enter the forced download mode.
In using, the female seat of Type-C includes two passageway configuration signal pins, and the data line includes the public head of Type-C supporting with the female seat of Type-C, and the public head of Type-C includes one or two passageway configuration signal pins. When the Type-C male connector comprises a channel configuration signal pin, the Type-C female seat comprises two channel configuration signal pins, so that whether the Type-C male connector is in positive connection or reverse connection with the Type-C female seat, the channel configuration signal pin of the Type-C male connector can be electrically connected with one channel configuration signal pin of the Type-C female seat; when the public head of Type-C includes two passageway configuration signal pins, because the female seat of Type-C also includes two passageway configuration signal pins, consequently, no matter the public head of Type-C is just connecing or the transposition with the female seat of Type-C, two passageway configuration signal pins that can both guarantee the public head of Type-C are connected with two passageway configuration signal pin one-to-one of the female seat of Type-C respectively.
In the application, the data line further comprises a Type-A male head corresponding to the Type-C male head of the data line, and at least one pull-up resistor is connected in series between a channel configuration signal pin of the Type-C male head and a power signal pin of the Type-A male head.
In application, the principle of calculating the resistance value of at least one pull-up resistor by the power management chip is as follows:
when the data line only comprises one channel configuration signal pin, and the first channel configuration signal pin of the Type-C female socket is electrically connected with the channel configuration signal pin of the data line, the voltage value of the second channel configuration signal pin of the Type-C female socket is 0, and the voltage value of the first channel configuration signal pin is obtained by dividing the voltage according to at least one first pull-down resistor connected with the first channel configuration signal pin in series inside the power management chip and at least one pull-up resistor connected with the channel configuration signal pin of the data line in series, so that the power management chip can calculate the resistance value of at least one pull-up resistor connected with the channel configuration signal pin of the data line in series according to the voltage value of the first channel configuration signal pin and the resistance value of the at least one first pull-down resistor;
when the data line only comprises one channel configuration signal pin, and the second channel configuration signal pin of the Type-C female socket is electrically connected with the channel configuration signal pin of the data line, the voltage value of the first channel configuration signal pin of the Type-C female socket is 0, and the voltage value of the second channel configuration signal pin is obtained by dividing the voltage according to at least one second pull-down resistor connected with the second channel configuration signal pin in series inside the power management chip and at least one pull-up resistor connected with the channel configuration signal pin of the data line in series, so that the power management chip can calculate the resistance value of at least one pull-up resistor connected with the channel configuration signal pin of the data line in series according to the voltage value of the second channel configuration signal pin and the resistance value of the at least one second pull-down resistor;
when the data line comprises two channel configuration signal pins, and the first channel configuration signal pin of the Type-C female socket is electrically connected with the first channel configuration signal pin of the data line, and the second channel configuration signal pin of the Type-C female socket is electrically connected with the second channel configuration signal pin of the data line, the voltage value of the first channel configuration signal pin of the Type-C female socket is obtained by dividing the voltage according to at least one first pull-down resistor connected in series with the first channel configuration signal pin of the Type-C female socket inside the power management chip and at least one first pull-up resistor connected in series with the first channel configuration signal pin of the data line, and the voltage value of the second channel configuration signal pin of the Type-C female socket is obtained by dividing the voltage according to at least one second pull-down resistor connected in series with the second channel configuration signal pin of the Type-C female socket inside the power management chip and at least one second pull-up resistor connected in series with the second channel configuration signal pin of the data line Therefore, the power management chip can calculate the resistance value of at least one first pull-up resistor connected in series with the first channel signal configuration pin of the data line according to the voltage value of the first channel configuration signal pin of the Type-C female socket and the resistance value of the at least one first pull-down resistor; and calculating the resistance value of at least one second pull-up resistor connected with the second channel configuration signal pin of the data line in series according to the voltage value of the second channel configuration signal pin of the Type-C female socket and the resistance value of at least one second pull-down resistor.
In application, the preset resistance value can be set according to actual needs, and when the data line comprises a channel configuration signal pin, the preset resistance value is equal to the sum of the resistance values of at least one pull-up resistor; when the data line comprises a first channel configuration signal pin and a second channel configuration signal pin, the preset resistance value comprises a first preset resistance value and a second preset resistance value, the first preset resistance value is equal to the sum of the at least one first pull-up resistor, and the second preset resistance value is equal to the sum of the at least one second pull-up resistor. When the data line comprises a first channel configuration signal pin and a second channel configuration signal pin, the power management chip triggers the application processor to enter the forced download circuit when the first preset resistance value is equal to the sum of the at least one first pull-up resistor and the second preset resistance value is equal to the sum of the at least one second pull-up resistor.
In an application, the preset resistance value should be set to be different from the sum of the resistance values of all pull-up resistors connected in series with each channel configuration signal pin in the conventional Type-C data line, so as to avoid that the power management chip mistakenly identifies the conventional Type-C data line as a data line which can trigger the application processor to enter a download mode.
In an embodiment, the power management chip is configured to output a high level signal to the application processor when the resistance value of the at least one pull-up resistor is equal to a preset resistance value, and trigger the application processor to enter a forced download mode.
In application, when the data line comprises a channel signal configuration pin, the power management chip outputs a high level signal to the application processor when the sum of the resistance values of at least one pull-up resistor is equal to a preset resistance value; when the data line comprises two channel signal configuration pins, the power management chip outputs a high level signal to the application processor when the sum of the resistance values of at least one first pull-up resistor is equal to a first preset resistance value and the sum of the resistance values of at least one second pull-up resistor is equal to a second preset resistance value.
As shown in fig. 2, in an embodiment, the preset GPIO (General-purpose input/output) interface GPIO of the power management chip 30 is electrically connected to the forced USB enable pin Force _ USB _ BOOT of the application processor 20;
the power management chip 30 is configured to generate a high level signal when the resistance value of the at least one pull-up resistor is equal to a preset resistance value, output the high level signal to the forced USB start pin Force _ USB _ BOOT through the preset GPIO interface GPIO, and trigger the application processor 20 to enter a forced download mode.
In application, the preset GPIO interface may be any one of all GPIO interfaces of the power management chip that is available for being electrically connected to the forced USB start pin of the application processor.
As shown in FIG. 3, in one embodiment, the Type-C female socket 10 includes a data line positive signal pin D + and a data line negative signal pin D-, and the application processor 20 is electrically connected to the data line positive signal pin D + and the data line negative signal pin D-;
the application processor 20 is configured to input a data signal through the data line positive signal pin D + and the data line negative signal pin D-after entering the forced download mode, and start downloading data.
In application, the data line positive signal pin and the data line negative signal pin may be a pair of differential signal pins D + and D-based on USB2.0 standard, or may be a pair of differential signal transmission pins RX + and RX-based on USB3.1 standard. The data line positive signal pin and the data line negative signal pin are illustratively shown in fig. 3 as a pair of differential signal pins D + and D-based on the USB2.0 standard.
As shown in fig. 4, an embodiment of the present application further provides a data line 200 applied to the forced download circuit 100 or a terminal device including the forced download circuit 100, where the data line 200 includes a Type-C male header 201 and a Type-a male header 202 that are matched with the Type-C female socket 10;
the Type-C male header 201 comprises a data line positive signal pin D +, a data line negative signal pin D-, one or two channel configuration signal pins (the Type-C male header 201 is exemplarily shown to comprise a first channel configuration signal pin CC1 and a second channel configuration signal pin CC2 in fig. 4), and at least one pull-up resistor is connected in series between each channel configuration signal pin of the Type-C male header 201 and a power signal pin VBUS of the Type-a male header 202 (the first channel configuration signal pin CC1 is exemplarily shown to be connected in series between the power signal pin VBUS and a first pull-up resistor R1 in fig. 4, and the second channel configuration signal pin CC2 is connected in series between the power signal pin VBUS and a second pull-up resistor R2 in fig. 4).
In an application, the data line positive signal pin D +, the data line negative signal pin D-may be equivalently replaced with a pair of differential signaling pins RX + and RX-based on the USB3.1 standard. The number of pull-up resistors connected in series between each channel configuration signal pin of the Type-C male connector and the power signal pin of the Type-A male connector can be set according to actual needs.
In application, the Type-C male header and the Type-A male header further comprise a ground pin for grounding.
As shown in fig. 5, an embodiment of the present application further provides a forced download method, which is implemented by the forced download circuit 100 or a terminal device including the forced download circuit 100, and may be specifically executed by the power management chip 30. The forced downloading method may be a software program method, and is implemented by the power management chip 30 when running the computer program, and the forced downloading method includes:
s501, when a Type-C female socket is connected with a data line, detecting voltage values of a first channel configuration signal pin and a second channel configuration signal pin of the Type-C female socket;
step S502, calculating the resistance value of at least one pull-up resistor electrically connected with the first channel configuration signal pin and/or the second channel configuration signal pin in the data line according to the voltage values of the first channel configuration signal pin and the second channel configuration signal pin;
step S503, when the resistance value of the at least one pull-up resistor is equal to the preset resistance value, triggering the application processor to enter a forced download mode.
In one embodiment, step S503 includes:
and when the resistance value of the at least one pull-up resistor is equal to a preset resistance value, outputting a high level signal to the application processor, and triggering the application processor to enter a forced downloading mode.
In one embodiment, step S503 includes:
generating a high level signal when the resistance value of the at least one pull-up resistor is equal to a preset resistance value;
and outputting the high-level signal to a forced USB starting pin of an application processor through a preset GPIO interface, and triggering the application processor to enter a forced downloading mode.
In an application, the forced download circuit or the terminal device may further include a memory and a computer program, such as a forced download program, stored in the memory and operable on the power management chip. The power management chip implements the steps in the above forced download method embodiment when executing the computer program, for example, steps S501 to S503 shown in fig. 5. The memory may be an internal memory space of the power management chip or an external memory unit, such as a memory.
According to the embodiment of the application, when the Type-C female socket is connected with a data line, voltage values of a first channel configuration signal pin and a second channel configuration signal pin are detected; calculating the resistance value of at least one pull-up resistor electrically connected with the first channel configuration signal pin and/or the second channel configuration signal pin in the data line according to the voltage values of the first channel configuration signal pin and the second channel configuration signal pin; when the resistance value of at least one pull-up resistor is equal to the preset resistance value, the application processor is triggered to enter a forced downloading mode, the data line of the pull-up resistor with the preset resistance value is connected through the Type-C female socket, the forced downloading mode can be entered, the short circuit test point does not need to be dismounted, and the operation is simple.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/wireless communication device and method may be implemented in other ways. For example, the above-described apparatus/wireless communication device embodiments are merely illustrative, and for example, the division of the modules or units is merely a logical division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow in the method of the embodiments described above can be realized by a computer program, which can be stored in a computer-readable storage medium and can realize the steps of the embodiments of the methods described above when the computer program is executed by a processor. . Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media which may not include electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A forced download circuit, comprising:
a Type-C female seat;
an application processor;
the power management chip is electrically connected with the first channel configuration signal pin, the second channel configuration signal pin and the application processor of the Type-C female socket and is used for detecting the voltage values of the first channel configuration signal pin and the second channel configuration signal pin when the Type-C female socket is connected with a data line; calculating the resistance value of at least one pull-up resistor electrically connected with the first channel configuration signal pin and/or the second channel configuration signal pin in the data line according to the voltage values of the first channel configuration signal pin and the second channel configuration signal pin; and when the resistance value of the at least one pull-up resistor is equal to a preset resistance value, triggering the application processor to enter a forced downloading mode.
2. The forced download circuit of claim 1, wherein the power management chip is configured to output a high level signal to the application processor when the resistance of the at least one pull-up resistor is equal to a predetermined resistance, and trigger the application processor to enter a forced download mode.
3. The forced download circuit of claim 2, wherein the preset GPIO interface of the power management chip is electrically connected to a forced USB enable pin of the application processor;
the power management chip is used for generating a high level signal when the resistance value of the at least one pull-up resistor is equal to a preset resistance value, outputting the high level signal to the forced USB starting pin through the preset GPIO interface, and triggering the application processor to enter a forced downloading mode.
4. The forced download circuit as claimed in any one of claims 1 to 3, wherein the Type-C female socket comprises a data line positive signal pin and a data line negative signal pin, and the application processor is electrically connected with the data line positive signal pin and the data line negative signal pin;
and the application processor is used for inputting data signals through the data line positive signal pin and the data line negative signal pin after entering a forced downloading mode and starting to download data.
5. The forced download circuit of claim 4, wherein the data line positive signal pin and the data line negative signal pin are a pair of differential signaling pins based on USB2.0 or USB3.1 standards.
6. A terminal device, characterized in that it comprises a forced download circuit according to any of claims 1 to 5.
7. A data line applied to the forced download circuit according to any one of claims 1 to 5 or the terminal device according to claim 6, wherein the data line comprises a Type-a male header and a Type-C male header matched with the Type-C female socket;
the Type-C male connector comprises a data line positive signal pin, a data line negative signal pin and one or two channel configuration signal pins, and at least one pull-up resistor is connected in series between each channel configuration signal pin of the Type-C male connector and the power supply signal pin of the Type-A male connector.
8. A forced download method, comprising:
when the Type-C female socket is connected with a data line, detecting voltage values of a first channel configuration signal pin and a second channel configuration signal pin of the Type-C female socket;
calculating the resistance value of at least one pull-up resistor electrically connected with the first channel configuration signal pin and/or the second channel configuration signal pin in the data line according to the voltage values of the first channel configuration signal pin and the second channel configuration signal pin;
and when the resistance value of the at least one pull-up resistor is equal to the preset resistance value, triggering the application processor to enter a forced downloading mode.
9. The forced download method of claim 8, wherein triggering the application processor to enter the forced download mode when the resistance of the at least one pull-up resistor is equal to a predetermined resistance comprises:
and when the resistance value of the at least one pull-up resistor is equal to a preset resistance value, outputting a high level signal to the application processor, and triggering the application processor to enter a forced downloading mode.
10. The forced downloading method of claim 9, wherein outputting a high signal to the application processor to trigger the application processor to enter the forced downloading mode when the resistance value of the at least one pull-up resistor is equal to a preset resistance value comprises:
generating a high level signal when the resistance value of the at least one pull-up resistor is equal to a preset resistance value;
and outputting the high-level signal to a forced USB starting pin of an application processor through a preset GPIO interface, and triggering the application processor to enter a forced downloading mode.
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| CN201910955625.6A CN110716891B (en) | 2019-10-09 | 2019-10-09 | Forced downloading method, circuit, terminal equipment and data line |
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| CN201910955625.6A CN110716891B (en) | 2019-10-09 | 2019-10-09 | Forced downloading method, circuit, terminal equipment and data line |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111509814A (en) * | 2020-05-29 | 2020-08-07 | 维沃移动通信有限公司 | Data line and charging equipment |
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| CN115801064A (en) * | 2022-11-09 | 2023-03-14 | 维沃移动通信有限公司 | Electronic device, download mode triggering method and readable storage medium |
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| CN110716891B (en) | 2021-03-02 |
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