CN114077565A

CN114077565A - Identification circuit, system control circuit, access circuit and interface device

Info

Publication number: CN114077565A
Application number: CN202010839453.9A
Authority: CN
Inventors: 朱绍敬; 刘猛
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-08-19
Filing date: 2020-08-19
Publication date: 2022-02-22

Abstract

The application provides an identification circuit, including: the system comprises a first processor, a pull-up circuit and/or a pull-down circuit and a first interface; wherein: the first processor is connected with a target grounding pin; the first processor is used for identifying whether the first interface is connected with a second interface device and/or the type of the second interface device according to the voltage of the target ground pin; the target ground pin is at least a part of at least one first ground pin; the first ground pin is a ground pin connected with the pull-up circuit or the pull-down circuit in the first interface; the first interface is an interface in the first interface device; when the first interface and the second interface device are switched between a disconnection state and a connection state, the voltage of at least one target grounding pin in the target grounding pins changes. The method and the device reduce the operation power consumption for identifying whether the second interface device is connected and/or the type of the second interface device.

Description

Identification circuit, system control circuit, access circuit and interface device

Technical Field

The application relates to the technical field of circuits, in particular to an identification circuit, a system control circuit, an access circuit and an interface device.

Background

The USB Type-C interface is more and more widely applied to consumer electronics products and becomes a standard configuration of devices such as smart phones, tablets, notebooks and Bluetooth headsets.

In the USB Type-C standard protocol, the USB Type-C interface device continuously sends a pulse signal to a Configuration Channel (CC) pin on the USB Type-C interface to identify whether another USB Type-C interface device accesses the USB Type-C interface and the Type of another USB Type-C interface device.

Obviously, the power consumption of the USB Type-C interface device is large due to the need to continuously transmit the pulse signal. In addition, some USB Type-C interface devices cannot recognize whether another USB Type-C interface device is accessed and the Type of another USB Type-C interface device that is accessed.

Disclosure of Invention

The application provides an identification circuit, a system control circuit, an access circuit and an interface device, which are used for solving the problems that the operation power consumption is high and some interface devices cannot identify the access of another interface device and/or the type of another interface device in the process of identifying the access of another interface device.

In a first aspect, the present application provides an identification circuit for use with a first interface device, the identification circuit comprising: the system comprises a first processor, a pull-up circuit and/or a pull-down circuit and a first interface; wherein: the first processor is connected with a target grounding pin; the first processor is used for identifying whether the first interface is connected with a second interface device and/or the type of the second interface device according to the voltage of the target ground pin; the target ground pin is at least a part of at least one first ground pin; the first ground pin is a ground pin connected with the pull-up circuit or the pull-down circuit in the first interface; the first interface is an interface in the first interface device; when the first interface and the second interface device are switched between a disconnection state and a connection state, the voltage of at least one target grounding pin in the target grounding pins changes.

When the first interface and the second interface device are switched between the disconnection state and the connection state, the voltage of at least one target grounding pin in the target grounding pins changes, that is, it can be understood that the voltage on the target grounding pin when the first interface is connected with the second interface device is different from the voltage on the target grounding pin when the first interface is disconnected with the second interface device, and therefore, whether the first interface is connected with the second interface device and/or the type of the second interface device can be identified according to the voltage of the target grounding pin. In addition, whether the first interface is connected with the second interface device and/or the type of the second interface device is identified according to the voltage of the target grounding pin, compared with the prior art, continuous pulse signal transmission is not needed, the operation power consumption is reduced, the operation power consumption of the first interface device comprising the identification circuit is further reduced, and meanwhile, a novel mode for identifying whether the second interface device is connected and/or the type of the second interface device is provided. Furthermore, the identification circuit may be applied to a first interface device having no function for identifying whether the second interface device is accessed and/or the type of the second interface device, so that the first interface device can identify whether the second interface device is accessed and/or the type of the second interface device.

In one possible implementation, when the first interface is in a state of not connecting the second interface device, the voltage of the target ground pin is related to the pull-up circuit or the pull-down circuit to which the target ground pin is connected; when the first interface is in a state of being connected with the second interface device, voltages of the target grounding pins corresponding to different types of the second interface devices are different.

In one possible implementation manner, the voltage of the target ground pin is a digital signal and the number of the target ground pins is multiple; the first processor identifying whether the first interface is connected with a second interface device and/or the type of the second interface device comprises: the first processor identifies whether the first interface is connected with a second interface device and/or the type of the second interface device according to the combination of high and low levels of the voltages of a plurality of target ground pins.

In a possible implementation manner, when the first interface is in a state of being connected to the second interface device, one type of the second interface device corresponds to one combination of high and low levels of voltages of a plurality of target ground pins, and combinations of high and low levels of voltages of a plurality of target ground pins corresponding to different types of the second interface device are different.

In one possible implementation manner, the voltage of the target ground pin is a digital signal and the number of the target ground pins is 1; the first processor identifying whether the first interface is connected with a second interface device and/or the type of the second interface device comprises: the first processor identifies whether the first interface is connected with a second interface device and/or the type of the second interface device according to the high-low level of the voltage of the target grounding pin.

In one possible implementation manner, the voltage of the target ground pin is an analog signal and the number of the target ground pins is multiple; the first processor identifying whether the first interface is connected with a second interface device and/or the type of the second interface device comprises: the first processor identifies whether the first interface is connected with a second interface device and/or the type of the second interface device according to the combination of the voltage values of the voltages of the plurality of target ground pins.

In a possible implementation manner, when the first interface is in a state of being connected to the second interface device, each type of the second interface device corresponds to one combination of voltage values of voltages of a plurality of target ground pins, and the combinations of voltage values of voltages of the plurality of target ground pins corresponding to the second interface devices of different types are different.

In one possible implementation manner, the voltage of the target ground pin is an analog signal and the number of the target ground pins is 1; the first processor identifying whether the first interface is connected with a second interface device and/or the type of the second interface device comprises: the first processor identifies whether the first interface is connected with a second interface device and/or the type of the second interface device according to the voltage value of the voltage of the target grounding pin.

In one possible implementation, the circuit further includes: a control circuit, wherein: the control circuit is connected with the first interface and the second processor in the first interface device; the first processor is also used for generating a control signal according to the identification result; the control circuit is used for responding to the control signal to control the on-off state of a path between the second processor and the first interface.

The control circuit is used for responding to the control signal to control the on-off state of the access between the second processor and the first interface, and the identification result is used for indicating whether the second interface equipment is accessed and the type of the accessed second interface equipment, namely, the control circuit can be understood as conducting the corresponding access and switching off other accesses according to whether the first interface is connected with the second interface equipment and the type of the connected second interface equipment, so that even if different pins are short-circuited, the control circuit can control the on-off state of the access according to the identification result, and therefore, the damage to the second processor caused by the short circuit between different pins can be avoided.

In one possible implementation, the first interface device is a left ear component of a wireless headset, the second interface device is a right ear component of the wireless headset, and a path between the second processor and the first interface includes an audio path; or the first interface device is a right ear component of the wireless headset, the second interface device is a left ear component of the wireless headset, and a path between the second processor and the first interface comprises an audio path.

In a possible implementation manner, the number of the first ground pins is two, wherein one of the first ground pins is connected with a pull-up circuit, and the other one of the first ground pins is connected with a pull-down circuit; the target grounding pin is a first grounding pin connected with the pull-down circuit; the control circuit controlling the on-off state of the path between the second processor and the first interface comprises: the control circuit turns on or off the audio path in response to the control signal.

In a second aspect, the present application provides a system control circuit for use with a first interface device, the system control circuit comprising: the control circuit, the pull-up circuit and/or the pull-down circuit and the first interface; wherein: the control circuit is connected with the target grounding pin; the control circuit is used for responding to the voltage of the target grounding pin to control the on-off state of a path between the second processor and the first interface; the target ground pin is at least a part of at least one first ground pin; the first ground pin is a ground pin connected with the pull-up circuit or the pull-down circuit in the first interface; the first interface is an interface in the first interface device, and the second processor is a processor in the first interface device; when the first interface and the second interface equipment are switched between a disconnection state and a connection state, the voltage of at least one target grounding pin in the target grounding pins changes.

The control circuit is used for responding to the voltage on the target grounding pin to control the on-off state of the path between the second processor and the first interface, and the voltage on the target grounding pin is used for indicating whether the second interface equipment is connected and the type of the connected second interface equipment, namely, the control circuit can be understood as conducting the corresponding path and switching off other paths according to whether the first interface is connected with the second interface equipment and the type of the connected second interface equipment, so that even if different pins are short-circuited, the control circuit can control the on-off state of the path according to whether the first interface is connected with the second interface equipment and the type of the connected second interface equipment, and therefore, the processor can be prevented from being damaged due to short circuit between the second different pins.

In one possible implementation, when the first interface is in a state of not connecting the second interface device, the voltage of the target ground pin is related to the pull-up circuit or the pull-down circuit to which the target ground pin is connected;

when the first interface is in a state of being connected with the second interface device, voltages of the target grounding pins corresponding to different types of the second interface devices are different.

In a possible implementation manner, the voltage of the target ground pin is a digital signal, and the number of the target ground pins is multiple; the control circuit controlling the on-off state of the path between the second processor and the first interface comprises: the control circuit controls the on-off state of a path between the second processor and the first interface in response to a combination of high and low levels of voltages of a plurality of target ground pins.

In a possible implementation manner, when the first interface is in a state of being connected to the second interface device, each type of the second interface device corresponds to one combination of high and low levels of voltages of a plurality of target ground pins, and the combinations of high and low levels of voltages of a plurality of target ground pins corresponding to different types of the second interface device are different.

In a possible implementation manner, the voltage of the target ground pin is a digital signal, and the number of the target ground pins is 1; the control circuit controlling the on-off state of the path between the second processor and the first interface comprises: the control circuit controls the on-off state of a path between the second processor and the first interface in response to the high-low level of the voltage of the target grounding pin.

In one possible implementation manner, the voltage of the target grounding pin is an analog signal and the number of the target grounding pins is multiple; the control circuit controlling the on-off state of the path between the second processor and the first interface comprises: the control circuit controls an on-off state of a path between the second processor and the first interface in response to a combination of voltage values of voltages of a plurality of target ground pins.

In a possible implementation manner, when the first interface is in a state of being connected to the second interface device, each type of the second interface device corresponds to one combination of voltage values of voltages of the plurality of target ground pins, and combinations of voltage values of voltages of the plurality of target ground pins corresponding to different types of the second interface device are different.

In one possible implementation manner, the voltage of the target ground pin is an analog signal and the number of the target ground pins is 1; the control circuit controlling the on-off state of the path between the second processor and the first interface comprises: the control circuit controls the on-off state of a path between the second processor and the first interface in response to a voltage value of a voltage of the target ground pin.

In a possible implementation manner, the number of the first ground pins is two, wherein one of the first ground pins is connected with a pull-up circuit, and the other one of the first ground pins is connected with a pull-down circuit; the target grounding pin is a first grounding pin connected with the pull-down circuit; the control circuit controlling the on-off state of the path between the second processor and the first interface comprises: the control circuit turns on the charging path or the audio path in response to a voltage of the target ground pin.

In a third aspect, the present application provides an access circuit, where the access circuit is applied to a second interface device, and the access circuit includes: a second interface, wherein: the second interface is used for connecting with a first interface in a first interface device, and the first interface device comprises the identification circuit in any one of the first aspects or the system control circuit in any one of the second aspects; the second interface comprises at least one second ground pin; the at least one second grounding pin corresponds to the at least one first grounding pin in the first interface one by one; the second interface is an interface in the second interface device; the connection mode of the second grounding pin is related to the voltage of a corresponding target grounding pin when the second interface is connected with the first interface; the target ground pin is at least a portion of the at least one first ground pin.

In a possible implementation manner, the connection manner of the second ground pin is one of the following five connection manners:

the second ground pin is grounded, the second ground pin is connected with a pull-down circuit, the second ground pin is connected with a pull-up circuit, the second ground pin is connected with another second ground pin, and the second ground pin is open-circuited.

In one possible implementation manner, the first interface device is a left ear component of the wireless headset, and the second interface device is a right ear component of the wireless headset; or the first interface device is a right ear component of the wireless earphone, and the second interface device is a left ear component of the wireless earphone.

In a possible implementation manner, if the number of the first ground pins is two, one of the first ground pins is connected to a pull-up circuit, the other of the first ground pins is connected to a pull-down circuit, and the target ground pin is the first ground pin connected to the pull-down circuit, the number of the second ground pins is two, and the two second ground pins are connected.

In a fourth aspect, the present application provides an electronic device comprising the identification circuit of any one of the first aspect, the system control circuit of any one of the second aspect, or the access circuit of any one of the third aspect.

Drawings

Fig. 1 is a schematic diagram showing a structure of a bluetooth headset in the related art;

fig. 2 is a schematic view showing a state in which a left ear assembly is separated from a right ear assembly in the related art;

FIG. 3 is a schematic diagram illustrating the connection of a left ear assembly to a right ear assembly in a related art;

FIG. 4 is a schematic diagram illustrating the connection of a left ear assembly to a computer according to the related art;

FIG. 5 shows a pin schematic in a USB TYPE-C interface;

fig. 6 is a first schematic diagram of an identification circuit and an access circuit provided in an embodiment of the present application;

fig. 7 is a second schematic diagram of an identification circuit and an access circuit provided in an embodiment of the present application;

fig. 8 is a third schematic diagram of an identification circuit and an access circuit provided in an embodiment of the present application;

fig. 9 is a fourth schematic diagram of an identification circuit and an access circuit provided in an embodiment of the present application;

fig. 10 is a fifth schematic diagram of an identification circuit and an access circuit provided in an embodiment of the present application;

fig. 11 is a sixth schematic diagram of an identification circuit and an access circuit provided in an embodiment of the present application;

FIG. 12 is a schematic diagram of the identification circuit with the addition of a control circuit to that of FIG. 9;

FIG. 13 is a first schematic structural diagram of a left ear assembly and a right ear assembly provided by an embodiment of the present application;

FIG. 14 shows a schematic diagram of a system control circuit and an access circuit;

fig. 15 is a schematic structural diagram ii of a left ear assembly and a right ear assembly provided in the embodiment of the present application.

Detailed Description

The technical solution in the present application will be described below with reference to the accompanying drawings.

To make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," and the like in the description examples and claims of this application and in the drawings are used for descriptive purposes only and are not to be construed as indicating or implying relative importance, nor order. Furthermore, the terms "comprises" and "comprising," as well as any variations thereof, are intended to cover a non-exclusive inclusion, such as a list of steps or elements. A method, system, article, or apparatus is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, system, article, or apparatus.

It should be understood that in the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" for describing an association relationship of associated objects, indicating that there may be three relationships, e.g., "a and/or B" may indicate: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.

First, a left ear module and a right ear module of a computer or a bluetooth headset are taken as an example to describe related technologies.

Fig. 1 shows a schematic structural diagram of a bluetooth headset in the related art. As shown in fig. 1, the bluetooth headset includes a left ear module 110 and a right ear module 120, and the left ear module 110 and the right ear module 120 are designed to be separable. The left ear component 110 and the right ear component 120 include USB Type-C interfaces. The dashed lines in fig. 1 indicate the connection location of the left ear assembly 110 and the right ear assembly 120.

The left ear component 110 and the right ear component 120 are connected by plugging the USB Type-C interface in the right ear component 120 into the USB Type-C interface in the left ear component 110 (as shown in fig. 1).

By pulling the USB Type-C interface in the right ear assembly 120 out of the USB Type-C interface in the left ear assembly 110, the left ear assembly 110 is separated from the right ear assembly 120 (as shown in FIG. 2), such that the USB Type-C interface of the left ear assembly 110 can be plugged into the USB Type-C interface of a computer to charge the left ear assembly 110 via the computer.

It should be noted that only a portion of the left and

right ear assemblies

110 and 120 are shown in fig. 2. The Type of USB Type-C interface includes public head and female head. If two USBType-C equipment are through the USBType-C interface lug connection wherein, then the USBType-C interface in one of them USBType-C equipment is public head, and the USBType-C interface in another USBType-C equipment is female head. For example: the USB Type-C interface that can set up left ear subassembly 110 is public head, and the USB Type-C interface of right ear subassembly 120 is female head. In addition, if the types of the USB Type-C interfaces in the two USB Type-C devices are the same and the two USB Type-C devices are to be connected, the two USB Type-C devices need to be connected through a converter.

Fig. 3 shows a schematic connection diagram of a left ear assembly and a right ear assembly in the related art. As shown in FIG. 3, the left ear assembly 110 includes a processor 111, a charging chip 112, a battery 113, and a USB Type-C interface 114. It should be noted that the left ear assembly 110 may also include more components, such as a speaker, a microphone, etc., other components not shown.

In the left ear assembly 110, the charging chip 112 is connected to any one of the pins a4, a9, B4, and B9 on the processor 111, the battery 113, and the USB Type-C interface 114, respectively, forming a charging path in the left ear assembly 110.

The processor 111 is connected to two of the pins a2, A3, B2, B3, a10, a11, B10, and B11 on the USB Type-C interface 114 (specifically, determined according to the positive and negative insertion modes of the interface), so as to form audio channels (SPK _ RP, SPK _ RN) in the left ear assembly 110.

The processor 111 is connected to two or four of the pins A6, A7, B6, B7 on the USB Type-C interface 114 to form a USB communication path (USB _ D +, USB _ D-) in the left ear assembly 110. It should be noted that the connection rule between the processor 111 and the pins a6, a7, B6, B7 on the USB Type-C interface 114 conforms to the USB communication protocol.

The four ground pins GND1.2.3.4 on the USB Type-C interface 114 are grounded, and the four ground pins GND1.2.3.4 are pins A1, A12, B1 and B12 on the USB Type-C interface 114. The shell of the USB Type-C interface 114 is grounded. The two CC pins A5 and B5 on the USB Type-C interface 114 are connected to ground through a resistor R.

As shown in fig. 3, the right ear assembly 120 includes a USB Type-C interface 121 and a speaker 122.

In the right ear assembly 120, the speaker 122 is connected to two of the pins a2, A3, B2, B3, a10, a11, B10, B11 on the USB Type-C interface 121 (specifically, determined by the way the interfaces are plugged in and unplugged), forming an audio path in the right ear assembly 120. It should be noted that, here, the pins of the speaker 122 connected to the USB Type-C interface 121 correspond to the pins of the processor 111 connected to the USB Type-C interface 114. The shell of the USB Type-C interface 121 is grounded.

As can be seen from fig. 3, after the left ear assembly 110 and the right ear assembly 120 communicate via the USB Type-C interface, the audio path in the left ear assembly 110 communicates with the audio path in the right ear assembly 120, so that the processor 111 can send audio information to the speaker 122.

Because the left ear assembly 110 is not provided with a circuit for identifying whether another USB Type-C interface device is connected and another connected USB Type-C interface device, after the left ear assembly 110 is connected to the right ear assembly 120, corresponding operations are directly performed through a path conducted between the left ear assembly 110 and the right ear assembly 12, but the left ear assembly 110 cannot identify the connection of the right ear assembly 120, so that it is less likely to identify the Type of the connected right ear assembly.

Fig. 4 is a schematic diagram illustrating the connection between the left ear assembly and the computer in the related art. As shown in fig. 4, the computer 130 includes a USB Type-C interface 131, a USB communication module 132, a CC detection module 133, and a reverse charging module 134.

Any one of the pins a4, a9, B4 and B9 on the USB Type-C interface 131 is connected to the reverse charging module 134 to form a reverse charging path in the computer 130.

Any two of the pins a6, a7, B6, and B7 of the USB Type-C interface 131 are connected to the USB communication module 132 to form a USB communication path in the computer 130.

The CC pins A5 and B5 on the USB Type-C interface 131 are connected with the CC detection module 133 to form a detection path in the computer 130.

In fig. 4, the CC detection module 133 continuously sends a pulse signal to the CC pin on the USB Type-C interface 131, after the USB Type-C interface 114 is connected to the USB Type-C interface 131, the charging path in the left ear component 110 and the reverse charging path in the computer 130 are directly connected, so that the computer 130 charges the battery 113 in the left ear component 110, the USB communication path in the computer 130 and the USB communication path in the left ear component 110 are directly connected, so that the processor 111 reports the acquired electric quantity of the battery 113 to the computer 130 through the charging paths, and the CC detection module 133 determines whether the USB Type-C interface 131 is connected to the left ear component 110 and the Type of the connected left ear component 110 through the continuously sent pulse signal. It should be noted that the processor is also used for processing other instructions in the bluetooth headset.

As can be seen from the above, since the computer 130 continuously sends the pulse signal through the CC detection module 133 to identify whether there is the USB Type-C interface device connected and the Type of the connected USB Type-C interface device, the operation power consumption of the computer is improved, and in addition, when the left ear assembly 110 and the right ear assembly 120 are in the separated state, if sweat or foreign matter short-circuits the pin on the USB Type-C interface 114 in the left ear assembly 110, as shown in fig. 4, when the left ear assembly 110 is charged, the charging voltage also applies a voltage to the short-circuited pin, thereby damaging the processor 111 in the left ear assembly 110. In addition, the left ear component 110 cannot identify whether the computer 130 is attached, and thus the type of computer 130 that the root may be attached to.

In conclusion, the mode that whether USB Type-C interface equipment is accessed or not and the Type of the USB Type-C interface equipment are identified by the computer can improve the running power consumption of the computer, and whether USB Type-C interface equipment (a computer and a right ear component) is accessed or not and the Type of the accessed USB Type-C interface equipment cannot be identified by the left ear component.

The same problem is also present for other interface devices.

Therefore, to solve the above technical problem, embodiments of the present application provide an identification circuit, a system control circuit, an access circuit and an interface device.

In the following, the basic concept related to the present application is explained. It should be noted that these explanations are intended to make the present application more understandable, and should not be construed as limiting the scope of protection claimed in the present application.

One, interface

The interface comprises a plurality of grounding pins which have the functions of charging, data transmission, display output and the like. For example, the interface includes, but is not limited to, a USB TYPE-C interface. FIG. 5 shows a pin diagram of a USB TYPE-C interface, which includes pins A1-A12 and pins B1-B12, as shown in FIG. 5. The definition of pins A1-A12 is indicated below pins A1-A12. The definition of pins B1-B12 is indicated above for pins B1-B12.

Second, the processor

In the embodiment of the present application, the type of the processor may be various, that is, the processor includes, but is not limited to, a Central Processing Unit (CPU), an ARM processor, a Field Programmable Gate Array (FPGA), a Micro Control Unit (MCU), a special processor, and other devices having a computing processing capability. In an optional implementation manner, the processor in this embodiment may also be an SOC chip. An SOC chip may also be referred to as a system-on-chip or system-on-chip, meaning that a complete system is integrated on a single chip. A complete system generally includes a central processing unit, a memory, and peripheral circuits.

The SOC chip technology is generally applied to small-sized terminal devices. For example, the SOC chip of the sound detection apparatus integrates an audio receiving terminal, an analog-to-digital converter, a microprocessor, a memory, an input-output interface, and the like on a single chip. Due to the efficient integration performance of SOC chips, SOC chips have become an inevitable trend in the development of microelectronic chips.

Third, control circuit

In an embodiment of the present application, the control circuit may be configured to control an on/off state of a path between a processor in the interface device and an interface therein. The control circuitry includes, but is not limited to, switching circuitry, interface controller, Vbus power control circuitry.

In order to make the objects, technical solutions and advantages of the present application more clear, the circuits and devices provided by the present application will be explained below.

First, the present application provides three circuits, respectively: the identification circuit, the system control circuit and the access circuit. The identification circuit and the system control circuit are both applied to the first interface device, and the access circuit is applied to the second interface device.

The first interface device includes, but is not limited to, a notebook computer, a mobile phone, a left ear component in a wireless headset, a right ear component in a wireless headset, a tablet computer, and other devices with interfaces.

The second interface device includes, but is not limited to, a smart phone, a smart watch, a tablet, a headset, a hard disk, a magnetic disk, a Solid State Disk (SSD), a flash disk, a VR device, an AR device, a personal computer, a handheld computer, a personal digital assistant, a left ear component in a wireless headset, a right ear component in a wireless headset, and the like.

The wireless headset refers to a headset that communicates with a terminal device such as a mobile phone or a tablet computer through a wireless communication technology (e.g., bluetooth technology).

The identification circuit is used for identifying whether the second interface device is connected and/or the type of the second interface device according to the voltage of the target grounding pin on the first interface in the first interface device, and in a possible implementation manner, the identification circuit is further used for transmitting the identification result to the control circuit so that the control circuit controls the on-off state of a path between the second processor in the first interface device and the first interface. It should be noted that, when the first interface is connected to the second interface device, the voltage on the target ground pin changes, and the change is related to the type of the second interface device, that is, when the first interface is connected to the second interface device, the voltage on the target ground pin indicates that the second interface device has been connected to the second interface device and the type of the second interface device.

The system control circuit is used for controlling the on-off state of a path between the second processor in the first interface device and the first interface according to the voltage of the target grounding pin on the first interface in the first interface device. It should be noted that, when the first interface is connected to the second interface device, the voltage on the target ground pin changes, and the change is related to the type of the second interface device, that is, when the first interface is connected to the second interface device, the voltage on the target ground pin indicates that the second interface device has been connected to the second interface device and the type of the second interface device.

Obviously, the identification circuit and the access circuit both perform a responsive operation according to the voltage of the target ground pin on the first interface, and when the first interface is connected to the second interface device, the voltage of the target ground pin changes, and the change is related to the type of the second interface device, so that for different types of second interface devices, the second interface device needs to be modified accordingly.

Based on this, the application also provides an access circuit, which is applied to the second interface device, so that when the first interface is accessed, the voltage of the target ground pin on the first interface is changed correspondingly.

In summary, the system control circuit and the access circuit are used in cooperation, and the identification circuit and the access circuit are also used in cooperation.

It should be noted that, in a possible implementation manner, an interface device may play different roles in different application scenarios, that is, in some application scenarios, the interface device is a first interface device, and in other application scenarios, the interface device is a second interface device. Therefore, for such an interface device, a circuit having the same principle as the identification circuit and a circuit having the same principle as the access circuit may be provided in the same interface in the interface device, or a circuit having the same principle as the system control circuit and a circuit having the same principle as the access circuit may be provided in the same interface in the interface device.

Since the system control circuit and the access circuit need to be used in cooperation, and the identification circuit and the access circuit need to be used in cooperation, hereinafter, the circuit, the first interface device, and the second interface device of the present application will be described with the cooperation between the circuits as a starting point.

Hereinafter, the three circuits will be described by taking the USB Type-C interface as an example.

First, the identification circuit and the access circuit will be explained.

The identification circuit comprises a first processor, a pull-up circuit and/or a pull-down circuit and a first USB Type-C interface. The first USB Type-C interface is an interface in the first interface device that includes the identification circuit.

The first processor is connected with the target grounding pin, and the first processor is used for identifying whether the first USB Type-C interface is connected with the second interface device and/or the Type of the second interface device according to the voltage of the target grounding pin. The target ground pin is at least a portion of the at least one first ground pin. The first ground pin is a ground pin connected with a pull-up circuit or a pull-down circuit in the first USB Type-C interface. When the first USB Type-C interface and the second interface equipment are switched between the disconnection state and the connection state, the voltage of at least one target grounding pin in the target grounding pins changes. When the first USB Type-C interface is in a state of being connected to the second interface device (i.e. the first USB Type-C interface is connected to the second USB Type-C interface in the second interface device), the voltage on the target ground pin is used to indicate the Type of the first USB Type-C interface connected to the second interface device and the second interface device. And under the condition that the first USB Type-C interface is not connected with the second interface equipment, the voltage of the target grounding pin is used for indicating that the first USB Type-C interface is not connected with the second interface equipment.

The identification circuit is applied to the first interface device, and the first interface device comprises a second processor which is used for executing various instructions and the like when the first interface device and the second interface device interact. The identification circuit includes a first processor, and the first processor and the second processor may be the same processor, that is, the identification circuit multiplexes the second processor in the first interface device, and the first processor and the second processor may be the same processor or may not be the same processor, which is not limited in this application.

From the above, the target ground pin is an interface in the first USB Type-C interface, which is used to identify whether the first USB Type-C interface is connected to the second interface device and/or the Type of the second interface device.

The first grounding pin is a pin which is connected with a pull-up circuit or a pull-down circuit in the first USB Type-C interface. The number of the first grounding pins is at least one, and the target grounding pin is at least one part of the at least one first grounding pin. If all the first grounding pins are target grounding pins, the number of the first grounding pins and the number of the target grounding pins are related to the number of the types of the second interface equipment needing to be identified. If a part of the first grounding pins are target grounding pins, the number of the target grounding pins is related to the Type number of the second interface equipment needing to be identified, and the number of the first grounding pins which are not used as the target grounding pins in the first grounding pins is related to the voltage change principle of the target grounding pins when the first USB Type-C interface is connected to the second interface equipment. For example, in fig. 8 below, the voltage of the target ground pin GND2 is pulled high through the first ground pin GND1.

Since the USB Type-C interface includes four ground pins, the number of the first ground pins may be, for example, 1, 2, 3, or 4.

It should be noted that, in a possible implementation manner, in order to ensure that the first USB Type-C interface and the second interface device form the same ground plane loop after being connected, at least one ground pin needs to be reserved in the first USB Type-C interface, and the reserved ground pin needs to be grounded. Thus, the number of first ground pins is at most 3.

The number of the target ground pins with the changed voltage can be determined according to design requirements, and is not particularly limited herein.

When the first USB Type-C interface is in a state of not connecting the second interface device, the voltage of the target grounding pin is related to the pull-up circuit or the pull-down circuit connected with the target grounding pin. In other words, the voltage of the target ground pin when the first USB Type-C interface is in a state where the second interface device is not connected is determined according to the pull-up circuit or the pull-down circuit to which the target ground pin is connected.

When the first USB Type-C interface and the second interface device are switched between the disconnection state and the connection state, the voltage of at least one target grounding pin in the target grounding pins changes. Therefore, the voltage of the target ground pin in the state that the first USBType-C interface is not connected with the second interface device is different from the voltage of the target ground pin in the state that the first USBType-C interface is connected with the second interface device, thus, the voltage of the target ground pin when the first USB Type-C interface is in a state of not connecting with the second interface device indicates that the second interface device is not connected with the first USB Type-C interface, the voltage of the target ground pin when the first USB Type-C interface is in a state of connecting with the second interface device indicates that the second interface device is connected with the first USB Type-C interface and the second interface device, thereby indicating whether the second interface device is connected to the first USB Type-C interface and/or the Type of the connected second interface device according to the voltage of the target ground pin.

The type of the second interface device may be defined according to design requirements, for example, the type of the second interface device may refer to a specific name of the device, i.e., a mobile phone, a computer, a headset, a microphone, and the like. For another example, the types of the second interface device include an audio communication device, a data interaction device, a charging device, and the like, and it should be noted that the principle of this Type of the second interface device is that after the second interface device is connected to the first USB Type-C interface, the interaction function between the two devices is divided. For example, if the second interface device performs audio communication after being connected to the first USB Type-C interface, the Type of the second interface device is an audio communication Type device, and if the second interface device performs charging after being connected to the first USB Type-C interface, the Type of the second interface device is an audio charging Type device.

In order to distinguish different types of second interface devices, when the first USB Type-C interface is in a state of being connected to the second interface device, voltages of target ground pins corresponding to the different types of second interface devices are different. The voltage of the target grounding pin corresponding to the second interface device is the voltage on the target grounding pin when the second interface device is connected with the first USB Type-C interface.

Since the number of the target ground pins is at least one, the voltage difference of the target ground pins corresponding to the different types of second interface devices can be understood as: if the voltages of at least one of the target ground pins corresponding to the two types of second interface devices are different, the voltages of the target ground pins corresponding to the two types of second interface devices are different.

When the first USB Type-C interface is in a state of being connected to the second interface device, the first ground pin is connected to a corresponding second ground pin on the second USB Type-C interface of the second interface device, so that the voltage of the first ground pin is affected by the connection mode of the corresponding second ground pin (which will be described below). Therefore, the voltage of the target ground pin in the case that the first USB Type-C interface is connected to the second interface device may be determined according to the connection manner of the pull-up circuit or the pull-down circuit to which the first ground pin is connected and the corresponding second ground pin.

Based on the above, if the voltage of the target ground pin is the voltage of the target ground pin when the first USB Type-C interface is in the state of not being connected with the second interface device, it is determined that the second interface device is not connected with the first USB Type-C interface, and if the voltage of the target ground pin is the voltage of the target ground pin when the first USB Type-C interface is in the state of being connected with the second interface device, it is determined that the second interface device is connected with the first USB Type-C interface, and the Type of the second interface device is determined according to the voltage of the target ground pin when the first USB Type-C interface is in the state of being connected with the second interface device.

Next, the voltage of the target ground pin will be described.

If the voltage of the target ground pin is a digital signal, the voltage of the target ground pin is a high level or a low level. Specifically, the method comprises the following steps:

when the first USB Type-C interface is not connected with the second interface equipment, if the target grounding pin is connected with the pull-up circuit, the voltage of the target grounding pin is at a high level, and if the target grounding pin is connected with the pull-down circuit, the voltage of the target grounding pin is at a low level. That is, the pull-up circuit is used to maintain the voltage of the target ground pin at a high level, and the pull-down circuit is used to maintain the voltage of the target ground pin at a low level.

When the first USB Type-C interface and the second interface equipment are switched from a disconnection state to a connection state, if the voltage of the target grounding pin changes and the target grounding pin is connected with the pull-up circuit, the voltage of the target grounding pin changes from a high level to a low level, and if the voltage of the target grounding pin changes and the target grounding pin is connected with the pull-down circuit, the voltage of the target grounding pin changes from a low level to a high level. I.e. the voltage of the target ground pin where the voltage changes is switched between high and low levels.

When the first USB Type-C interface is in a state of being connected with second interface equipment, aiming at a target grounding pin with voltage change, if the target grounding pin is connected with a pull-up circuit, the voltage of the target grounding pin is at a low level, and if the target grounding pin is connected with a pull-down circuit, the voltage of the target grounding pin is at a high level. For a target ground pin with unchanged voltage, if the target ground pin is connected with a pull-up circuit, the voltage of the target ground pin is at a high level, and if the target ground pin is connected with a pull-down circuit, the voltage of the target ground pin is at a low level.

Based on this, if the type of the second interface device is one, a target ground pin is set. Since the voltage of the target ground pin is a digital signal, the voltage of the target ground pin has two values, namely, a high level and a low level. In this way, it may be indicated by either one of the high level and the low level that the second interface device is not connected to the first USB Type-C interface, and by the other one of the high level and the low level that the second interface device is connected to the first USB Type-C interface and the Type of the connected second interface device. And determining the number of the first grounding pins, the connection mode of the second grounding pins in the second USB Type-C interface in the second interface equipment and the target grounding pins in the first grounding pins according to the voltages of the target grounding pins with different connection states.

In this way, the first processor identifies whether the first USB Type-C interface is connected to the second interface device and/or the Type of the second interface device according to the high-low level of the voltage of the target ground pin.

And if the types of the second interface equipment are multiple, setting the number of the target grounding pins according to the type number of the second interface equipment. Since the types of the second interface device are various, the number of the target ground pins is at least two. Specifically, since the voltage of the target ground pin is a digital signal, the combination of the high and low levels of the voltages of the N target ground pins is N²The first USB Type-C interface is not connected with the second interface equipment due to the fact that a combination is needed, and therefore the N target grounding pins can indicate N at most²-1 type of second interface device. Based on the above principle, the number of the first target ground pins can be deduced reversely according to the number of the types of the second interface devices.

After the number of the target ground pins is determined, a combination when the first USB Type-C interface is not connected to the second interface device and a combination when the first USB Type-C interface is connected to each of the second interface devices are respectively determined among combinations of high and low levels of voltages of the plurality of target ground pins. And determining the number of the first grounding pins, the connection mode of the second grounding pins in the second USB Type-C interface in each Type of second interface equipment and the target grounding pins in the first grounding pins according to the determined combination.

In this way, the first processor identifies whether the first USB Type-C interface is connected to the second interface device and/or the Type of the second interface device according to the combination of the high and low levels of the voltages of the plurality of target ground pins. When the first USB Type-C interface is in a state of being connected with second interface equipment, the second interface equipment of one Type corresponds to one combination of high and low levels of the voltages of the target grounding pins, and the second interface equipment of different types corresponds to different combinations of high and low levels of the voltages of the target grounding pins.

The determination principle of the information such as the connection manner of the first ground pin, the connection manner of the second ground pin, the number of the target ground pins, and the number of the first ground pins is only exemplary and is not intended to limit the present application.

If the voltage of the target ground pin is an analog signal, the voltage of the target ground pin is one of a first preset voltage value or at least one second preset voltage value, and each second preset voltage value of the at least one second preset voltage value is different. Specifically, the method comprises the following steps:

when the first USB Type-C interface is not connected to the second interface device, the voltage of the target ground pin is a first preset voltage value, that is, the pull-up circuit or the pull-down circuit is configured to maintain the voltage of the target ground pin at the first preset voltage value.

When the first USB Type-C interface and the second interface equipment are switched from the disconnection state to the connection state, if the voltage of the target grounding pin changes, the voltage of the target grounding pin is one of at least one second preset voltage value. I.e. the voltage of the target ground pin, whose voltage varies, switches between different voltage values.

The number of the second preset voltage values is related to the number of types of the second interface devices and the number of the target ground pins.

When the first USB Type-C interface is in a state of being connected with second interface equipment, aiming at a target grounding pin with changed voltage, the voltage of the target grounding pin is one of at least one second preset voltage value, and aiming at a target grounding pin with unchanged voltage, the voltage of the target grounding pin is a first preset voltage value.

Based on this, if the number of the target ground pins is one. The voltage of the target grounding pin is an analog signal, so that the number of second preset voltage values of the target grounding pin can be determined according to the Type number of the second interface equipment, namely the number of the second preset voltage values is the same as the Type number of the second interface equipment, the second preset voltage values correspond to the types of the second interface equipment one to one, and the second interface equipment, which is used for indicating the corresponding Type of the second preset voltage values, is connected to the first USB Type-C interface.

After the number of the second preset voltage values is determined, the size of each second preset voltage value and the size of the first preset voltage value are set, and then the number of the first grounding pins, the connection mode of the second grounding pins in the second interface in each type of second interface equipment and the target grounding pins in the first grounding pins are determined according to the set sizes.

In this way, the first processor identifies whether the first USB Type-C interface is connected to the second interface device and/or the Type of the second interface device according to the voltage value of the voltage of the target ground pin.

If the number of the target ground pins is multiple. Since the voltage of the target ground pin is an analog signal, the number of the second preset voltage values of each target ground pin can be determined according to the number of the types of the second interface devices, so as to ensure that the number of the combinations of the voltage values of the voltages of the plurality of target ground pins is greater than or equal to the sum of the number of the types of the second interface devices and 1.

After the number of the second preset voltage values of each target grounding pin is determined, the size of the first preset voltage value of each target grounding pin and the size of the second preset voltage value of each target grounding pin are determined, and the combination of the voltage values of the plurality of target grounding pins when the first USB Type-C interface is not connected with the second interface device and the combination of the voltage values of the plurality of target grounding pins when the first USB Type-C interface is connected with the second interface device are determined according to the first preset voltage value and the second preset voltage value of each target grounding pin. And finally, determining the number of the first grounding pins, the connection mode of the second grounding pins in the second interface in each type of second interface equipment and the target grounding pins in the first grounding pins according to the determined combination.

In this way, the first processor identifies whether the first USB Type-C interface is connected to the second interface device and/or the Type of the second interface device according to a combination of voltage values of voltages of the plurality of target ground pins. When the first USB Type-C interface is in a state of being connected with second interface equipment, each Type of second interface equipment corresponds to one combination of voltage values of voltages of a plurality of target grounding pins, and the combinations of the voltage values of the voltages of the plurality of target grounding pins corresponding to the second interface equipment of different types are different.

The pull-up circuit may include, for example, a resistor and a power supply connected to one end of the resistor, and the other end of the resistor is connected to the first ground pin. The pull-down circuit may include, for example, a resistor having one end connected to ground and the other end connected to the first ground pin. It should be noted that the structures of the pull-up circuit and the pull-down circuit are merely exemplary, and are not used to limit the present application.

In summary, when the first USB Type-C interface and the second interface device are switched between the disconnected state and the connected state, the voltage of at least one target ground pin in the target ground pin changes, that is, it can be understood that the voltage on the target ground pin when the first USB Type-C interface is connected to the second interface device is different from the voltage on the target ground pin when the first USB Type-C interface is disconnected from the second interface device, and therefore, whether the first USB Type-C interface is connected to the second interface device and/or the Type of the second interface device can be identified according to the voltage of the target ground pin. In addition, whether the first USB Type-C interface is connected with the second interface device and/or the Type of the second interface device is identified according to the voltage of the target grounding pin, compared with the prior art, continuous pulse signal sending is not needed, the operation power consumption is reduced, the operation power consumption of the first interface device comprising the identification circuit is further reduced, and meanwhile, a novel mode for identifying whether the second interface device is connected and/or the Type of the second interface device is provided. Furthermore, the identification circuit may be applied to a first interface device having no function for identifying whether the second interface device is accessed and/or the type of the second interface device, so that the first interface device can identify whether the second interface device is accessed and/or the type of the second interface device.

The access circuit comprises a second USB Type-C interface. Wherein: the second USB Type-C interface is used for being connected with the first USB Type-C interface in the first interface equipment. The first interface device comprises the above-mentioned identification circuit.

The second USB Type-C interface comprises at least one second grounding pin, the at least one second grounding pin corresponds to at least one first grounding pin in the first USB Type-C one to one, the connection mode of the second grounding pin is related to the voltage of a corresponding target grounding pin when the second USB Type-C interface is connected with the first USB Type-C interface, and the target grounding pin is at least one part of the at least one first grounding pin.

The quantity of second ground pin is the same with the quantity of first ground pin, and when second USBType-C interface and first USBType-C interface connection, first ground pin is connected with the second ground pin that corresponds. Because the USB Type-C interface includes four ground pins, the number of second ground pins is at most 4.

It should be noted that, in a possible implementation manner, in order to ensure that the first USB Type-C interface and the second USB Type-C interface form the same ground plane when connected, at least one ground pin needs to be reserved in the second USB Type-C interface and grounded. Thus, the number of the second ground pins is at most 3.

Therefore, when the first USB Type-C interface and the second USB Type-C interface are switched between the disconnected state and the connected state, the voltage on at least one target ground pin in the target ground pins changes, that is, when the first USB Type-C interface is connected to the second USB Type-C interface, the voltage on the target ground pin is affected by the connection mode of the second ground pin connected to the target ground pin. Therefore, the connection mode of the second ground pin is related to the voltage of the target ground pin connected with the second USB Type-C interface when the second USB Type-C interface is connected with the first USB Type-C interface.

The connection mode of the second ground pin includes, but is not limited to, the following five types: the second grounding pin is grounded, the second grounding pin is connected with the pull-down circuit, the second grounding pin is connected with the pull-up circuit, the second grounding pin is connected with the other second grounding pin, and the second grounding pin is open-circuited.

The identification circuit and the access circuit are explained below by way of example.

Fig. 6 is a first schematic diagram of an identification circuit and an access circuit provided in an embodiment of the present application. The identification circuit is applied to the first interface device. As shown in fig. 6, the identification circuit includes a first processor, a first USB Type-C interface Type C1, and a pull-up circuit. The TypeC1 includes four ground pins GND1.2.3.4, where the first ground pin and the target ground pin are GND1 in TypeC1, and GND1 in TypeC1 is connected to a pull-up circuit, which includes a resistor R1 and a power supply VDD1 connected to the resistor R1, and GND2.3.4 in TypeC1 is grounded. The voltage of the target ground pin is a digital signal.

The access circuit is applied to the second interface device. Since the kind of the access circuit is one, the type of the second interface device is one. The access circuit comprises a second USB Type-C interface Type C2a, the Type C2a comprising four ground pins GND1.2.3.4, wherein the second ground pin is GND1 in Type C2a, and GND1 in Type C2a is grounded, and GND2, 3, 4 in Type C2a is grounded.

Since the voltage of the target ground pin is a digital signal. Therefore, in the case where the second interface device is not connected to the TypeC1 (i.e., in the case where the TypeC2a is not connected to the TypeC 1), the voltage of the GND1 in the TypeC1 is maintained at a high level by the pull-up circuit. When the TypeC2a is connected to the TypeC1, GND1.2.3.4 of the TypeC1 is communicated with GND1.2.3.4 of the TypeC2a in sequence, and since GND1 of the TypeC2a is grounded, the voltage of GND1 of the TypeC1 is low.

Based on this, the type c1 is not accessed by the high level on GND1 in type c1, and the type of the second interface device is accessed by the second interface device into type c1 and the type of the second interface device is indicated by the low level on GND1 in type c 1.

In other words, if the voltage of GND1 in TypeC1 is high level, the first processor determines that the second interface device is not accessed to TypeC1, and if the voltage of GND1 in TypeC1 is low level, the first processor determines that the second interface device is accessed to TypeC1 and determines the type of the second interface device according to the low level of GND1 in TypeC 1.

As can be seen from the above, since the voltage of GND1 in TypeC1 when TypeC1 is in a state of not connecting the second interface device is different from the voltage of GND1 in TypeC1 when TypeC1 is in a state of connecting the second interface device, and since the voltage of GND1 is a digital signal, whether TypeC1 is connected to the second interface device and/or the second interface device is identified according to the high-low level of the voltage of GND1 in TypeC 1. In addition, because the type of the TypeC1 and whether the second interface device and/or the second interface device is connected is identified according to the high-low level of the voltage of the GND1 in the TypeC1, compared with the prior art, the pulse signal does not need to be continuously sent, the operation power consumption is reduced, the operation power consumption of the first interface device comprising the identification circuit is further reduced, and a new identification mode is provided. Furthermore, the identification circuit may be applied to a first interface device without an identification function, so that the first interface device can identify whether to access a second interface device and/or a type of the second interface device.

Fig. 7 is a second schematic diagram of an identification circuit and an access circuit provided in the embodiment of the present application. The identification circuit is applied to the first interface device and the access circuit is applied to the second interface device.

As shown in fig. 7, the identification circuit differs from the identification circuit in fig. 6 in that the voltage of the target ground pin is an analog signal.

Since the kinds of the access circuits are 2, the kinds of the second interface devices are two. The second USB Type-C interface in the first Type of access circuit is Type C2a, and the second USB Type-C interface in the second Type of access circuit is Type C2 b. The first access circuit is the same as the one in fig. 6. The first access circuit is applied to the first type of second interface equipment, and the second access circuit is applied to the second type of second interface equipment.

The second access circuit comprises a second USB Type-C interface Type C2b, and the Type C2b comprises four ground pins GND1.2.3.4, wherein the second ground pin is GND1 in the Type C2b, and GND1 in the Type C2b is connected to a pull-down circuit, and the pull-down circuit comprises a grounded resistor R2, and GND2.3.4 in the Type C2b is grounded.

Since the voltage of the target ground pin is an analog signal. Therefore, in the case where the second interface device is not connected to TypeC1 (i.e., in the case where neither TypeC2a nor TypeC2b is connected to TypeC 1), the voltage of GND1 in TypeC1 is maintained at 5V (calculated from the voltage of power supply VDD 1) by the pull-up circuit. When the TypeC2a is connected to the TypeC1, GND1.2.3.4 of the TypeC1 is sequentially communicated with GND1.2.3.4 of the TypeC2a, and since GND1 of the TypeC2a is grounded, the voltage of GND1 of the TypeC1 is 0V. When the TypeC2b is connected to the TypeC1, GND1.2.3.4 of the TypeC1 is sequentially communicated with GND1.2.3.4 of the TypeC2b, and since GND1 of the TypeC2b is grounded through the resistor R2, the voltage of the GND1 of the TypeC1 is 3V (calculated according to the resistors R1 and R2 and the voltage of the power supply VDD 1).

Based on this, the type c1 is not connected to the second interface device is indicated by the voltage value 5V of GND1 in the type c1, the second interface device is connected to the type c1 is indicated by the voltage value 0V of GND1 in the type c1, and the type of the second interface device is the second type. The second interface device is switched into the TypeC1 and the type of the second interface device is the second type, which is indicated by the voltage value of 3V of GND1 in the TypeC 1.

In other words, if the voltage value of GND1 in TypeC1 is 5V, the first processor determines that the second interface device is not accessed to TypeC1, and if the voltage value of GND1 in TypeC1 is 0V, the first processor determines that the second interface device is accessed to TypeC1 and the type of the second interface device is the first type. If the voltage value of GND1 in the TypeC1 is 3V, the first processor determines that the second interface device is accessed into the TypeC1 and the type of the second interface device is the second type.

As can be seen from the above, since the voltage of the GND1 in TypeC1 when TypeC1 is in a state of not connecting the second interface device is different from the voltage of the GND1 in TypeC1 when TypeC1 is in a state of connecting the second interface device, and since the voltage of the GND1 in TypeC1 is an analog signal, whether TypeC1 connects the second interface device and/or the type of the second interface device is indicated according to the different voltage values of the voltage of the GND1 in TypeC 1. In addition, because the TypeC1 and whether the second interface device and/or the type of the second interface device are/is connected are identified according to the voltage value of GND1 in the TypeC1, compared with the prior art, continuous pulse signal transmission is not needed, the operation power consumption is reduced, the operation power consumption of the first interface device comprising the identification circuit is further reduced, and a novel identification mode is provided. Furthermore, the identification circuit may be applied to a first interface device without an identification function, so that the first interface device can identify whether to access a second interface device and/or a type of the second interface device.

Fig. 8 is a third schematic diagram of an identification circuit and an access circuit provided in the embodiment of the present application. The identification circuit is applied to the first interface device, and as shown in fig. 8, the identification circuit includes a first processor, a first USB Type-C interface Type C1, and a pull-up circuit and a pull-down circuit. The TypeC1 includes four ground pins GND1.2.3.4, where the first ground pin is GND1.2 in TypeC1, and GND1 in TypeC1 is connected to a pull-up circuit including resistor R1 and power supply VDD1 connected to resistor R1. GND2 in TypeC1 is connected to a pull-down circuit, which includes a resistor R3, and the resistor R3 is connected to ground. The target ground pin is GND2 in TypeC1, GND3.4 in TypeC1 is grounded, and the voltage of the target ground pin is a digital signal.

The access circuit is applied to the second interface device. Since the kind of the access circuit is one, the type of the second interface device is one. The access circuit comprises a second USB Type-C interface Type C2a, the Type C2a comprising four ground pins GND1.2.3.4, wherein the second ground pin is GND1.2 in Type C2a, and GND1 and GND2 in Type C2a are connected. GND3.4 in TypeC2a is grounded.

The voltage of the grounding pin is a digital signal. Therefore, in the case where the second interface device is not connected to the TypeC1, the voltage of GND2 in the TypeC1 is maintained at a low level by the pull-down circuit. With the type c2a accessing the type c1, GND1.2.3.4 in the type c1 in turn communicates with gnd1.2.3.4 in the type c2 a. Thus, as shown, GND2 in TypeC1 communicates with GND1 in TypeC 1. Since GND1 and GND2 in TypeC1 are connected, the voltage of GND2 in TypeC1 is pulled up to a high level by VDD1 and R1.

Based on this, the low level of GND2 in TypeC1 indicates that TypeC1 does not access the second interface device, and the high level of GND2 in TypeC1 indicates that the second interface device accesses TypeC1 and the type of the second interface device.

In other words, if the voltage of GND2 in TypeC1 is low, the first processor determines that the second interface device does not access TypeC1, and if the voltage of GND2 in TypeC1 is high, the first processor determines that the second interface device accesses TypeC1 and the type of the second interface device.

As can be seen from the above, since the voltage of the GND2 in TypeC1 when TypeC1 is in a state of not connecting the second interface device is different from the voltage of the GND2 in TypeC1 when TypeC1 is in a state of connecting the second interface device, and since the voltage of the GND2 in TypeC1 is a digital signal, whether TypeC1 is connected to the second interface device and/or the second interface device is identified according to the high-low level of the voltage of the GND2 in TypeC 1. In addition, because the type of the TypeC1 and whether the second interface device and/or the second interface device is connected is identified according to the high-low level of the voltage of the GND2 in the TypeC1, compared with the prior art, the pulse signal does not need to be continuously sent, the operation power consumption is reduced, the operation power consumption of the first interface device comprising the identification circuit is further reduced, and a new identification mode is provided. Furthermore, the identification circuit may be applied to a first interface device without an identification function, so that the first interface device can identify whether to access a second interface device and/or a type of the second interface device.

Fig. 9 is a fourth schematic diagram of an identification circuit and an access circuit provided in the embodiment of the present application. The identification circuit is applied to the first interface device and the access circuit is applied to the second interface device.

As shown in fig. 9, the identification circuit includes a first processor, a first USB Type-C interface Type C1, and a pull-up circuit and a pull-down circuit. The TypeC1 includes four ground pins GND1.2.3.4, where the first ground pin and the target ground pin are GND1.2 in TypeC1, and GND1 in TypeC1 is connected to a pull-up circuit including resistor R1 and power supply VDD1 connected to resistor R1. GND2 in TypeC1 is connected to a pull-down circuit, which includes a resistor R3, and the resistor R3 is connected to ground. GND3.4 in TypeC1 is grounded, and the voltage of the target ground pin is an analog signal.

Since the kinds of the access circuits are 3, the kinds of the second interface devices are three. The second USB Type-C interface in the first Type of access circuit is Type C2a, the second USB Type-C interface in the second Type of access circuit is Type C2b, and the second USB Type-C interface in the third Type of access circuit is Type C2C. The first access circuit is the same as the first access circuit in fig. 7. The second access circuit is the same as the second access circuit in fig. 7. The third access circuit comprises a second USB Type-C interface Type C2C, the Type C2C comprises four ground pins GND1.2.3.4, wherein the second ground pin is GND1.2 in Type C2C, and GND1 and GND2 in Type C2C are connected. GND3.4 in TypeC2c is grounded.

The first access circuit is applied to the first type of second interface equipment, the second access circuit is applied to the second type of second interface equipment, and the third access circuit is applied to the third type of second interface equipment.

Since the voltage of the target ground pin is an analog signal. Therefore, in the case where the second interface device is not connected to the TypeC1, the voltage of GND1 in the TypeC1 is maintained at 5V by the pull-up circuit, and the voltage of GND2 in the TypeC1 is maintained at 0V by the pull-down circuit.

When the TypeC2a is connected to the TypeC1, GND1.2.3.4 of the TypeC1 is communicated with GND1.2.3.4 of the TypeC2a in turn, and since GND1.2 of the TypeC2a is grounded, the voltage value of GND1.2 of the TypeC1 is 0V.

With the type c2b accessing the type c1, GND1.2.3.4 in the type c1 in turn communicates with GND1.2.3.4 in the type c2 b. Since GND2 in TypeC2b is grounded, the voltage value of GND2 in TypeC1 is 0V, and since GND1 in TypeC2b is grounded through resistor R2, the voltage value of GND1 in TypeC1 is 3V (calculated by resistors R1, R2 and power supply VDD 1).

When the TypeC2c is connected to the TypeC1, GND1.2.3.4 of the TypeC1 is sequentially communicated with GND1.2.3.4 of the TypeC2c, and GND2 and GND1 of the TypeC2c are connected, so that the voltage of GND1 and 2 of the TypeC1 is 2V (calculated by resistors R1 and R3 and a power supply VDD 1).

Based on this, the type c1 is indicated by a voltage value (5V,0V) on GND1.2 in the type c1 that is not connected to the second interface device, the second interface device is indicated by a voltage value (0V,0V) on GND1.2 in the type c1 that is connected to the type c1 and the type of the second interface device is the first type. The second interface device is switched into the TypeC1 and the type of the second interface device is indicated as the second type by a voltage value (3V,0V) on GND1.2 in the TypeC 1. The second interface device is indicated to be switched into the TypeC1 by a voltage value (2V,2V) on GND1.2 in the TypeC1 and the type of the second interface device is the third.

Thus, if the voltage of GND1.2 in TypeC1 is (5V,0V), the first processor determines that the second interface device is not accessed to TypeC1, and if the voltage of GND1.2 in TypeC1 is (0V,0V), the first processor determines that the second interface device is accessed to TypeC1 and the type of the second interface device is the first type. If the voltage GND1.2 in the TypeC1 is (3V,0V), the first processor determines that the second interface device is connected to the TypeC1 and the type of the second interface device is the second type. If the voltage GND1.2 in the TypeC1 is (2V,2V), the first processor determines that the second interface device is connected to the TypeC1 and the type of the second interface device is the third type.

As can be seen from the above, since the voltage of GND1.2 in TypeC1 when TypeC1 is in a state of not connecting the second interface device is different from the voltage of GND1.2 in TypeC1 when TypeC1 is in a state of connecting the second interface device, and since the voltage of GND1.2 is a digital signal, whether TypeC1 connects the second interface device and/or the second interface device is identified according to a combination of voltage values of the voltages of GND1.2. In addition, because the type of identifying the TypeC1 and whether to connect the second interface device and/or the second interface device is identified according to the combination of the voltage values of the voltages of the GND1.2, compared with the prior art, the continuous transmission of the pulse signal is not needed, the operation power consumption is reduced, and further, the operation power consumption of the first interface device including the identification circuit is reduced, and a new mode is provided. Furthermore, the identification circuit may be applied to a first interface device without an identification function, so that the first interface device can identify whether to access a second interface device and/or a type of the second interface device.

Fig. 10 is a fifth schematic diagram of an identification circuit and an access circuit provided in an embodiment of the present application. The identification circuit is applied to the first interface device and the access circuit is applied to the second interface device.

As shown in fig. 10, the identification circuit includes a first processor, a first USB Type-C interface Type C1, and a pull-up circuit and a pull-down circuit. The TypeC1 includes four ground pins GND1.2.3.4, where the first and target ground pins are GND1.2.3 in TypeC1, and GND1 in TypeC1 connects to a pull-up circuit that includes resistor R1 and power supply VDD1 connected to resistor R1. GND2 in TypeC1 is connected to a pull-up circuit comprising resistor R2 and power supply VDD2 connected to resistor R2. GND3 in TypeC1 is connected to a pull-down circuit, which includes a resistor R3, and the resistor R3 is connected to ground. GND4 in TypeC1 is grounded. The voltage of the target ground pin is an analog signal.

Since the kinds of the access circuits are 4, the kinds of the second interface devices are four. The second USB Type-C interface in the first Type of access circuit is Type C2a, the second USB Type-C interface in the second Type of access circuit is Type C2b, the second USB Type-C interface in the third Type of access circuit is Type C2C, and the second USB Type-C interface in the fourth Type of access circuit is Type C2 d.

The first access circuit comprises a second USB Type-C interface Type C2a, the Type C2a comprises four ground pins GND1.2.3.4, wherein the second ground pin is GND1.2.3 of the Type C2a, GND1.2.4 of the Type C2a is grounded, and GND3 of the Type C2a is connected with a pull-up circuit, the pull-up circuit comprises a resistor R4 and a power supply VDD3 connected with the resistor R4.

The second access circuit comprises a second USB Type-C interface Type C2b, the Type C2b comprises four ground pins GND1.2.3.4, wherein the second ground pin is GND1.2.3 of the Type C2b, GND2.3.4 of the Type C2b is grounded, GND1 of the Type C2b is connected to a pull-down circuit, the pull-up circuit comprises a resistor R5, and the resistor R5 is grounded.

The third access circuit comprises a second USB Type-C interface Type C2C, the Type C2C comprises four ground pins GND1.2.3.4, wherein the second ground pin is GND1.2.3 of the Type C2C, GND2.3.4 of the Type C2C is grounded, GND1 of the Type C2C is connected to a pull-down circuit, the pull-up circuit comprises a resistor R6, and the resistor R6 is grounded.

The fourth access circuit comprises a second USB Type-C interface Type C2d, the Type C2d comprising four ground pins GND1.2.3.4, wherein the second ground pin is GND1.2.3 of Type C2d, wherein GND1.2. connection of Type C2d, GND3.4 ground of Type C2 d.

The first access circuit is applied to the first second interface device, the second access circuit is applied to the second interface device, the third access circuit is applied to the third second interface device, and the fourth access circuit is applied to the fourth second interface device.

The voltage of the grounding pin is an analog signal. Therefore, in the case that the second interface device is not connected to the TypeC1, the voltage of GND1.2 in the TypeC1 is maintained at 5V by the pull-up circuit, and the voltage of GND3 in the TypeC1 is maintained at 0V by the pull-down circuit.

When the TypeC2a is connected to the TypeC1, GND1.2.3.4 in the TypeC1 is sequentially communicated with GND1.2.3.4 in the TypeC2a, and since GND1.2 in the TypeC2a is grounded, the voltage of GND1.2 in the TypeC1 is 0V. The voltage of GND3 in TypeC1 is 5V (calculated from resistor R3, resistor R4, and power supply VDD 3).

When the TypeC2b is connected to the TypeC1, GND1.2.3.4 in the TypeC1 is sequentially communicated with GND1.2.3.4 in the TypeC2b, and since GND2.3 in the TypeC2b is grounded, the voltage of GND2.3 in the TypeC1 is 0V. The voltage of GND1 in TypeC1 is 3V (calculated from resistor R1, resistor R5, and power supply VDD 1).

When the TypeC2c is connected to the TypeC1, GND1.2.3.4 in the TypeC1 is sequentially communicated with GND1.2.3.4 in the TypeC2c, and since GND2.3 in the TypeC2c is grounded, the voltage of GND2.3 in the TypeC1 is 0V. The voltage of GND1 in TypeC1 is 2V (calculated from resistor R1, resistor R6, and power supply VDD 1).

When the TypeC2d is connected to the TypeC1, GND1.2.3.4 in the TypeC1 is sequentially communicated with GND1.2.3.4 in the TypeC2d, and since GND3 in the TypeC2d is grounded, the voltage of GND3 in the TypeC1 is 0V. Since the GND1 and 2 in the TypeC2d are communicated, the voltage of GND1.2 in the TypeC1 is 3V (calculated according to the resistor R1, the resistor R2, the power supplies VDD1 and VDD 2).

Based on this, the TypeC1 is indicated by a voltage value (5V,0V) of GND1.2.3 in the TypeC1 not to be connected to the second interface device, the second interface device is indicated by a voltage value (0V, 5V) on GND1.2.3 in the TypeC1 to be connected to the TypeC1 and the type of the second interface device is the first type. The second interface device is indicated to be accessed to TypeC1 and the type of the second interface device is the second type by a voltage value (3V,0V) on GND1.2.3 in TypeC 1. The second interface device is indicated to be accessed to TypeC1 by the voltage value (2V, 0V) on GND1.2.3 in TypeC1 and the type of the second interface device is the third. The second interface device is indicated to be accessed to TypeC1 by the voltage value (3V,0V) on GND1.2.3 in TypeC1 and the type of the second interface device is fourth.

Thus, if the voltage of GND1.2.3 in the TypeC1 is (5V,0V), the first processor determines that the second interface device does not access the TypeC1, and if the voltage of GND1.2.3 in the TypeC1 is (0V, 5V), the first processor determines that the second interface device accesses the TypeC1 and the type of the second interface device is the first type. If the voltage of GND1.2.3 in the TypeC1 is (3V,0V), the first processor determines that the second interface device is accessed into the TypeC1 and the type of the second interface device is the second type. If the voltage of GND1.2.3 in the TypeC1 is (2V, 0V), the first processor determines that the second interface device is accessed to the TypeC1 and the type of the second interface device is the third type. If the voltage of GND1.2.3 in the TypeC1 is (3V,0V), the first processor determines that the second interface device is accessed into the TypeC1 and the type of the second interface device is a fourth type.

As can be seen from the above, the voltage of GND1.2.3 in TypeC1 when TypeC1 is in a state of not connecting the second interface device is different from the voltage of GND1.2.3 in TypeC1 when TypeC1 is in a state of connecting the second interface device, and the combination of the voltage values of GND1.2.3 when TypeC1 connects a second interface device of a different kind, so it is possible to identify whether TypeC1 connects the second interface device and/or the type of the second interface device according to the combination of the voltage values of voltage of GND1.2.3. In addition, since the type of the TypeC1 and whether the second interface device and/or the second interface device is connected is identified according to the combination of the voltage values of the voltage of GND1.2.3, compared with the prior art, continuous transmission of a pulse signal is not required, the operation power consumption is reduced, the operation power consumption of the first interface device including the identification circuit is further reduced, and a new identification mode is provided. Furthermore, the identification circuit can be used in the first interface device of the identification function, so that the first interface device can identify whether the second interface device is connected and/or the type of the second interface device.

Fig. 11 is a sixth schematic diagram of an identification circuit and an access circuit provided in an embodiment of the present application. The identification circuit is applied to the first interface device and the access circuit is applied to the second interface device.

As shown in fig. 11, the identification circuit includes a first processor, a first USB Type-C interface Type C1, and a pull-up circuit. The TypeC1 includes four ground pins GND1.2.3.4, where the first and target ground pins are GND1.2.3 in TypeC1, and GND1 in TypeC1 connects to a pull-up circuit that includes resistor R1 and power supply VDD1 connected to resistor R1. GND2 in TypeC1 is connected to a pull-up circuit comprising resistor R2 and power supply VDD2 connected to resistor R2. GND3 in TypeC1 is connected to a pull-up circuit comprising resistor R3 and power supply VDD3 connected to resistor R3. The voltage of the ground pin is a digital signal.

The first access circuit includes a second USB Type-C interface Type C2a, the Type C2a including four ground pins GND1.2.3.4, wherein the second ground pin is GND1.2.3 of Type C2a, wherein GND1.2.3.4 of Type C2a is grounded.

The second access circuit comprises a second USB Type-C interface Type C2b, the Type C2b comprises four ground pins GND1.2.3.4, wherein the second ground pin is GND1.2.3 of the Type C2b, GND2.3.4 of the Type C2b is grounded, and GND1 of the Type C2a is open-circuited.

The third access circuit comprises a second USB Type-C interface Type C2C, the Type C2C comprises four ground pins GND1.2.3.4, wherein the second ground pin is GND1.2.3 of the Type C2C, GND3.4 of the Type C2C is grounded, and GND1.2 of the Type C2C is open.

The fourth access circuit comprises a second USB Type-C interface Type C2d, the Type C2d comprises four ground pins GND1.2.3.4, wherein the second ground pin is GND1.2.3 of the Type C2d, GND1.3 of the Type C2d is open, and GND2.4 of the Type C2C is grounded.

Since the voltage on the ground pin is a digital signal. Therefore, in the case where the second interface device is not connected to TypeC1, the voltages of GND1.2.3 in TypeC1 are all high levels.

When the TypeC2a is connected to the TypeC1, GND1.2.3.4 in the TypeC1 is sequentially communicated with GND1.2.3.4 in the TypeC2a, and the voltage of GND1.2.3 in the TypeC1 is low.

When the TypeC2b is connected to the TypeC1, GND1.2.3.4 in the TypeC1 is communicated with GND 11.2.3.4 in the TypeC2b in turn, and the voltage of GND2.3 in the TypeC1 is low. The voltage of GND1 in TypeC1 is high.

When the TypeC2c is connected to the TypeC1, GND1.2.3.4 in the TypeC1 is sequentially communicated with GND1.2.3.4 in the TypeC2c, and the voltage of GND3 in the TypeC1 is low. The voltage of GND1.2 in TypeC1 is high.

When the TypeC2d is connected into the TypeC1, GND1.2.3.4 in the TypeC1 is sequentially communicated with GND1.2.3.4 in the TypeC2d, and the voltage of GND1.3 in the TypeC1 is high level. The voltage of GND2 in TypeC1 is high.

Based on this, the TypeC1 is indicated by a voltage (high level ) of GND1.2.3 in the TypeC1 not to be connected to the second interface device, the second interface device is indicated by a voltage (low level ) of GND1.2.3 in the TypeC1 to be connected to the TypeC1 and the type of the second interface device is the first type. By the voltage value GND1.2.3 (high level, low level) in the TypeC1, it is indicated that the second interface device is accessed to the TypeC1 and the type of the second interface device is the second type. The second interface device is indicated by the voltage (high, low) on GND1.2.3 in TypeC1 to access TypeC1 and the type of the second interface device is the third. The second interface device is indicated by the voltage GND1.2.3 (high, low, high) in TypeC1 to access TypeC1 and the type of the second interface device is fourth.

Thus, if the voltage of GND1.2.3 in the TypeC1 is (high level ), the first processor determines that the second interface device does not access the TypeC1, and if the voltage of GND1.2.3 in the TypeC1 is (low level ), the first processor determines that the second interface device accesses the TypeC1 and the type of the second interface device is the first type. If the voltage of GND1.2.3 in the TypeC1 is (high, low), the first processor determines that the second interface device is accessed into the TypeC1 and the type of the second interface device is the second type. If the voltage GND1.2.3 of the TypeC1 is (high level, low level), the first processor determines that the second interface device is accessed to the TypeC1 and the type of the second interface device is the third type. If the voltage of GND1.2.3 in the TypeC1 is (high, low, high), the first processor determines that the second interface device is accessed to the TypeC1 and the type of the second interface device is a fourth type.

As can be seen from the above, the combination of the high point level of the voltage at GND1.2.3 in TypeC1 when TypeC1 is in a state of not connecting the second interface device is different from the combination of the high and low levels of the voltage at GND1.2.3 in TypeC1 when TypeC1 is in a state of connecting the second interface device, and the combination of the high and low levels of the voltage at GND1.2.3 when TypeC1 is connecting a second interface device of a different kind, and therefore it is possible to identify whether TypeC1 connects the second interface device and/or the second interface device according to the combination of the high and low levels of the voltage at GND1.2.3 in TypeC 1. In addition, since the type of the TypeC1 and whether to connect the second interface device and/or the second interface device is identified according to the combination of the high and low levels of the voltage GND1.2.3 in the TypeC1, compared with the prior art, a pulse signal does not need to be continuously transmitted, the operation power consumption is reduced, and further, the operation power consumption of the first interface device including the identification circuit is reduced, and a new identification mode is provided. Furthermore, the identification circuit may be applied to a first interface device without an identification function, so that the first interface device can identify whether to access a second interface device and/or a type of the second interface device. In addition, since the number of the target ground pins is plural and the voltage of the target ground pin is a digital signal, more types of second interface devices may be indicated by a combination of high point levels of the voltage of the target ground pin.

In the above examples, the combination of high and low levels and the combination of voltage values are exemplary, and are not intended to limit the present application.

On this basis, the identification circuit also comprises a control circuit. The control circuit is connected with the first processor, the second processor and the first USB Type-C interface, the first processor is further used for generating a control signal according to the identification result, and the control circuit is used for responding to the control signal to control the on-off state of a channel between the second processor and the first USB Type-C interface.

The second processor has already been described above and will therefore not be described in further detail here. In the first interface device, a plurality of paths exist between the second processor and the first USB Type-C interface, and the plurality of paths include a path for interacting with the second interface device, that is, at least one path corresponds to each Type of second interface device.

In a possible implementation manner, when the first USB Type-C interface is not connected to the second interface device, the path corresponding to the second interface device is in an off state, and when the first USB Type-C interface is connected to the second interface device, the path corresponding to the second interface device is in an on state.

For example, the first interface device is a left ear component of a wireless headset, the second interface device is a right ear component of the wireless headset, and the path between the second processor in the left ear component and the first USB Type-C interface therein includes an audio path.

And if the left ear component is not connected with the second interface equipment, the audio channel is cut off, and if the left ear component is connected with the right ear component, the audio channel is connected. Or

For another example, the first interface device is a right ear component of the wireless headset, the second interface device is a left ear component of the wireless headset, and the path between the second processor in the right ear component and the first USB Type-C interface therein includes an audio path.

And if the right ear component is not connected with the second interface equipment, the audio channel is switched off, and if the right ear component is connected with the left ear component, the audio channel is switched on.

Because the control circuit is used for responding to the control signal and controlling the on-off state of the access between the second processor and the first USB Type-C interface, and the identification result is used for indicating whether the second interface equipment is accessed and the Type of the accessed second interface equipment, namely, the corresponding access can be switched on and other accesses can be switched off according to whether the first USB Type-C interface is connected with the second interface equipment and the Type of the connected second interface equipment, even if the pins are short-circuited, the control circuit can control the on-off state of the access according to the identification result, and therefore, the damage to the second processor caused by the short-circuit between different pins can be avoided.

Next, a control circuit will be described by taking an example in which a control circuit is added to the identification circuit in fig. 9, and fig. 12 is a schematic diagram of an identification circuit in which a control circuit is added to fig. 9. In fig. 12 the first processor and the second processor are identical. FIG. 12 differs from FIG. 9 in that the identification circuit further includes a control circuit that is coupled to the first processor and the first USB Type-C interface. As shown in fig. 12, two paths exist between the first processor and the first USB Type-C interface, which are a first path and a second path, respectively, where the first path is turned on when the Type C1 is connected to the second interface device, and the second path is turned on when the Type C1 is not connected to the second interface device.

It should be noted that the identification circuit added with the control circuit is only exemplary and not intended to limit the present application, and for example, for each of the identification circuits shown above, a control circuit may be added to the identification circuit according to the above principle.

Based on the above principle, the identification circuit including the control circuit is introduced into the left ear module of the wireless headset, the access circuit is introduced into the right ear module, and the wireless headset is a bluetooth headset as an example, and the left ear module and the right ear module after being improved are described as an example.

Fig. 13 is a first schematic structural diagram of a left ear assembly and a right ear assembly provided in an embodiment of the present application. The left ear assembly 1310 includes a second processor 1311 (where the first and second processors are the same), a first USB Type-C interface USB Type-C11314, a charging chip 1312, a battery 1313, and a control circuit 1315. The USB Type-C comprises GND1.2.3.4, wherein a first USB Type-C interface pin is GND3.4, a target grounding pin is GND4, the GND3.4 is grounded, the GND4 is connected with a pull-down circuit, the pull-down circuit comprises a resistor R5, and a resistor R5 is grounded. GND3 is connected to a pull-up circuit that includes resistor R3 and power supply VDD1 connected to R3.

The paths between the second processor 1311 and the USB Type-C11314 include a charging path, a USB communication path (USB _ D +, USB _ D-) and audio paths (SPK _ RP, SPK _ RN). Wherein. The USB communication path and the charging path are in a conducting state. The charging path is composed of a charging chip 1312, a battery 1313, a second processor 1311, and a USB Type-C11314. The control circuit 1315 controls the audio path to be turned on or off in response to a control signal, and the control circuit 1315 is a switch circuit, which is configured as shown in the figure.

The right ear assembly includes a second USB Type-C interface USB Type-C21321 and a speaker 1322. Wherein the USB Type-C21321 and the speaker 1322 are connected to form audio paths (SPK _ RP, SPK _ RN) in the right ear assembly.

If the voltage on the ground pin is a digital signal, the voltage on GND4 is low when the left ear assembly 1310 is not connected to any second interface device, and the voltage on GND4 is high when the right ear assembly 1320 is connected.

Based on this, the left ear component 1310 is indicated by a low level on GND4 in Type-C11314 as not having the second interface device connected. The left ear assembly 1310 is indicated with a high voltage level on GND4 in Type-C11314 as being connected to a second interface device, and the second interface device is a right ear assembly 1320.

And if the voltage at GND4 in Type-C11314 is high, i.e., it is determined that the second interface device is connected, and the second interface device is a right ear device, then a control signal is generated to control the control circuit 1315 to turn on the audio channel (i.e., two moving parts of the switch are connected to SPK _ RP and SPK _ RN).

If the voltage at GND4 in Type-C11314 is low, a control signal is generated to control the control circuit 1315 to turn off the audio channel (i.e., the two moving parts of the switch are grounded through resistors R2 and R3, respectively).

It should be noted that the left ear assembly can only identify one type of the second interface device, and the type of the second interface device is the right ear assembly.

Obviously, the left ear component can identify whether the second interface device is connected or not and the Type of the connected second interface device (right ear component) according to the voltage on the GND4 in the Type-C11314. In addition, the audio channel can be switched on after the fact that the second interface equipment is connected is recognized and the connected second interface equipment is connected to the right ear assembly, and the audio channel is switched off when the second interface equipment is not connected. Like this, when the circular telegram equipment inserts left ear subassembly, because the charging path switches on always, then can directly charge to left ear subassembly, because the Type of charging equipment is different with the Type of right ear subassembly again, consequently the audio frequency route is turn-offs, like this, even the pin that the charging path corresponds on USB Type-C11314 and the pin short circuit that the audio frequency route corresponds, also can not cause the injury to the second treater.

It should be noted that, although the USB communication path is always in the on state, the withstand voltage of the USB communication path is high, and therefore, even if the pin corresponding to the charging path on the USB Type-C11314 is short-circuited with the pin of the USB communication path, the pin will not pass through and cause damage.

It should be noted that, in the above example, the structure of the control circuit is merely exemplary, and is not used to limit the present application, and in other possible implementations, the control circuit may also be used to control the on/off states of the audio path, the USB communication path, and the charging path.

Next, a system control circuit and an access circuit will be explained.

The system control circuit comprises a control circuit, a pull-up circuit and/or a pull-down circuit and a first USB Type-C interface; wherein: and the control circuit is connected with the target grounding pin and used for responding to the voltage of the target grounding pin to control the on-off state of a path between the second processor and the first USB Type-C interface. The target ground pin is at least a portion of the at least one first ground pin. The first ground pin is a ground pin connected with a pull-up circuit or a pull-down circuit in the first USB Type-C interface. The first USB Type-C interface is an interface in the first interface device, and the second processor is an interface in the first interface device. If the first USB Type-C interface and the second interface equipment are switched from the disconnection state to the connection state, the voltage of at least one target grounding pin in the target grounding pins changes. In the case of a first USB Type-C interface connecting a second interface device (i.e., a second USB Type-C interface in the first USB Type-C interface connecting the second interface device), the voltage on the target ground pin is used to indicate the Type of the first USB Type-C interface connecting the second interface device and the second interface device. Under the condition that the first USB Type-C interface is not connected with the second interface device, the voltage of the target grounding pin is used for indicating that the first USB Type-C interface is not connected with the second interface device.

Since the system control circuit is different from the above-described identification apparatus including the control circuit in that: the system control circuit does not need the first processor to identify whether the second interface device is accessed and/or the type of the second interface device, and the system control circuit controls the control circuit directly according to the voltage on the target ground pin, and since the voltage on the target ground pin indicates whether the second interface device is accessed and/or the type of the second interface device, the system control circuit can be understood as controlling the control circuit directly according to whether the second interface device is accessed and/or the type of the second interface device accessed. Since the identification circuit controls the control circuit according to the identification result, and the identification result is used to indicate whether the second interface device is connected and/or the type of the second interface device, the principle of the control circuit in the identification circuit and the control circuit in the system control circuit is the same, and only the representation form of the signal for controlling the control circuit is different.

Based on this, since the identification circuit has the same principle as the same part in the system control circuit, and the principle of the same part has already been explained in the identification circuit, the detailed description is omitted here.

In addition, since the principle of the same part in the identification circuit and the system control circuit is the same, the design principle of the interface is also the same, and therefore the design principle of the interface is not described herein again.

The control circuit is used for responding to the voltage on the target grounding pin to control the on-off state of the access between the second processor and the first USB Type-C interface, and the voltage on the target grounding pin is used for indicating whether the second interface equipment is connected and the Type of the connected second interface equipment, namely, the corresponding access is conducted and other accesses are turned off according to whether the first USB Type-C interface is connected with the second interface equipment and the Type of the connected second interface equipment, so that even if the different pins are short-circuited, the control circuit can control the on-off state of the access according to the Type of whether the first USB Type-C interface is connected with the second interface equipment and the connected second interface equipment, and therefore, the second processor can be prevented from being damaged.

In the following, a system control circuit and an access circuit are described by way of example,

fig. 14 shows a schematic diagram of the system control circuit and the access circuit.

The system control circuit is applied to the first interface equipment, and the system control circuit comprises a first USB Type-C interface TypeC1, a pull-up circuit, a pull-down circuit and a control circuit. The TypeC1 includes four ground pins GND1.2.3.4, where the first ground pin is GND1.2 in TypeC1, and GND1 in TypeC1 is connected to a pull-up circuit including resistor R1 and power supply VDD1 connected to resistor R1. GND2 in TypeC1 is connected to a pull-down circuit, which includes a resistor R3, and the resistor R3 is connected to ground. The target ground pin is GND2 in TypeC1, GND3.4 in TypeC1 is grounded, and the voltage of the ground pin is a digital signal. The control circuit is connected with the second processor in the first interface device and the TypeC1 and is used for controlling the on-off state of the first path and the second path between the second processor and the TypeC 1.

In other words, if the voltage of GND2 in TypeC1 is low, it indicates that the two interface devices do not access TypeC1, and the control circuit turns on the first path and turns off the second path through the low level. If the voltage of GND2 in TypeC1 is at a high level, it indicates that the second interface device is connected to TypeC1 and the type of the second interface device, and the control circuit turns off the first path and turns on the second path through the low level.

It should be noted that the above examples are merely illustrative and are not intended to limit the present application.

Based on the above principle, the system control circuit is introduced into the left ear module of the wireless headset, the access circuit is introduced into the right ear module, and the wireless headset is a bluetooth headset for example, and the left ear module and the right ear module after improvement are described for example.

Fig. 15 is a schematic structural diagram ii of a left ear assembly and a right ear assembly provided in the embodiment of the present application. FIG. 15 differs from FIG. 13 in that GND4 in Type-C11314 in FIG. 15 is not tied into the second processor, but is tied directly into control circuit 1315, which control circuit 1315 controls the audio path to turn on or off in response to GND4 in Type-C11314.

If the voltage on the ground pin is a digital signal, the voltage on the GND4 in Type-C11314 is low when the left ear assembly 1310 is not connected to any second interface device, and the voltage on the GND4 in Type-C11314 is high after the right ear assembly 1320 is connected.

Based on this, the left ear component 1310 is indicated by a low level on GND4 in Type-C11314 as not having the second interface device connected. The left ear component 1310 is indicated with a high level on GND4 in Type-C11314 as being connected to a second interface device, and the second interface device is a right ear component 1320.

And if the voltage at GND4 in Type-C11314 is high, the control circuit 1315 turns on the audio channel (i.e., the two moving parts of the switch are connected to SPK _ RP and SPK _ RN).

If the voltage at GND4 in Type-C11314 is low, the control circuit 1315 turns off the audio channel (i.e., the two moving parts of the switch are grounded through resistors R2 and R3, respectively).

Obviously, the left ear component can turn on or off the audio channel according to the voltage on the GND4 in the Type-C11314, specifically, after the voltage on the GND4 in the Type-C11314 indicates that the second interface device is connected and the connected second interface device is connected for the right ear component, the audio component is turned on, and when the voltage on the GND4 in the Type-C11314 indicates that the second interface device is not connected, the audio channel is turned off. Like this, when through inserting the circular telegram equipment left ear subassembly, because the charging path switches on always, then can directly charge to the left ear subassembly, because the Type of charging equipment is different with the Type of right ear subassembly again, consequently the audio frequency route is turn-offs, like this, even the pin that the charging path corresponds on USB Type-C11314 and the pin short circuit that the audio frequency route corresponds, also can not cause the injury to the second treater.

Although the USB communication path is always in the on state, the withstand voltage of the USB communication path is high, and therefore, even if the pin corresponding to the charging path on the USB Type-C11314 is short-circuited with the pin of the USB communication path, the pin will not pass through and cause damage.

In an embodiment of the present application, an electronic device is further provided, where the electronic device includes the above identification circuit, or a system control circuit or an access circuit.

By introducing the circuits into the electronic equipment, the electronic equipment realizes the corresponding function of each circuit. It should be noted that, when the electronic device executes the corresponding process through the introduced circuit, the technical effect generated by the electronic device is similar to that of the corresponding circuit, and therefore, the details are not repeated here.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. An identification circuit for use with a first interface device, the identification circuit comprising: the system comprises a first processor, a pull-up circuit and/or a pull-down circuit and a first interface; wherein:

the first processor is connected with a target grounding pin;

the first processor is used for identifying whether the first interface is connected with a second interface device and/or the type of the second interface device according to the voltage of the target ground pin;

the target ground pin is at least a part of at least one first ground pin;

the first ground pin is a ground pin connected with the pull-up circuit or the pull-down circuit in the first interface;

the first interface is an interface in the first interface device;

when the first interface and the second interface device are switched between a disconnection state and a connection state, the voltage of at least one target grounding pin in the target grounding pins changes.

2. The circuit of claim 1, wherein when the first interface is in a state of no connection to the second interface device, the voltage of the target ground pin is related to the pull-up circuit or the pull-down circuit to which it is connected;

3. The circuit according to claim 1 or 2, wherein the voltage of the target ground pin is a digital signal and the number of the target ground pins is plural;

the first processor identifying whether the first interface is connected with a second interface device and/or the type of the second interface device comprises:

the first processor identifies whether the first interface is connected with a second interface device and/or the type of the second interface device according to the combination of high and low levels of the voltages of a plurality of target ground pins.

4. The circuit of claim 4, wherein when the first interface is in a state of connecting the second interface device, one type of the second interface device corresponds to one combination of high and low levels of voltages of a plurality of target ground pins, and different types of the second interface device correspond to different combinations of high and low levels of voltages of a plurality of target ground pins.

5. The circuit of claim 1 or 2, wherein the voltage of the target ground pin is a digital signal and the number of the target ground pins is 1;

the first processor identifies whether the first interface is connected with a second interface device and/or the type of the second interface device according to the high-low level of the voltage of the target grounding pin.

6. The circuit according to claim 1 or 2, wherein the voltage of the target ground pin is an analog signal and the number of the target ground pins is plural;

the first processor identifies whether the first interface is connected with a second interface device and/or the type of the second interface device according to the combination of the voltage values of the voltages of the plurality of target ground pins.

7. The circuit of claim 6, wherein each type of the second interface device corresponds to a different combination of voltage values of voltages of a plurality of target ground pins when the first interface device is in a state of connecting the second interface device, and wherein the different types of the second interface device correspond to different combinations of voltage values of voltages of a plurality of target ground pins.

8. The circuit of claim 1 or 2, wherein the voltage of the target ground pin is an analog signal and the number of the target ground pins is 1;

the first processor identifies whether the first interface is connected with a second interface device and/or the type of the second interface device according to the voltage value of the voltage of the target grounding pin.

9. The circuit of any one of claims 1-8, further comprising: a control circuit, wherein:

the control circuit is connected with the first interface and the second processor in the first interface device;

the first processor is also used for generating a control signal according to the identification result;

the control circuit is used for responding to the control signal to control the on-off state of a path between the second processor and the first interface.

10. The circuit of claim 9, wherein the first interface device is a left ear component of a wireless headset, wherein the second interface device is a right ear component of a wireless headset, and wherein the path between the second processor and the first interface comprises an audio path; or

The first interface device is a right ear assembly of the wireless headset, the second interface device is a left ear assembly of the wireless headset, and a path between the second processor and the first interface comprises an audio path.

11. The circuit of claim 10, wherein the number of the first ground pins is two, one of the first ground pins is connected to a pull-up circuit, and the other of the first ground pins is connected to a pull-down circuit;

the target grounding pin is a first grounding pin connected with the pull-down circuit;

the control circuit controlling the on-off state of the path between the second processor and the first interface comprises:

the control circuit turns on or off the audio path in response to the control signal.

12. A system control circuit for use with a first interface device, the system control circuit comprising: the control circuit, the pull-up circuit and/or the pull-down circuit and the first interface; wherein:

the control circuit is connected with the target grounding pin;

the control circuit is used for responding to the voltage of the target grounding pin to control the on-off state of a path between the second processor and the first interface;

the target ground pin is at least a part of at least one first ground pin;

the first interface is an interface in the first interface device, and the second processor is a processor in the first interface device;

when the first interface and the second interface equipment are switched between a disconnection state and a connection state, the voltage of at least one target grounding pin in the target grounding pins changes.

13. The circuit of claim 12, wherein the voltage of the target ground pin is related to the pull-up circuit or the pull-down circuit to which it is connected when the first interface is in a state in which the second interface device is not connected;

14. The circuit according to claim 12 or 13, wherein the voltage of the target ground pin is a digital signal, and the number of the target ground pins is plural;

the control circuit controls the on-off state of a path between the second processor and the first interface in response to a combination of high and low levels of voltages of a plurality of target ground pins.

15. The circuit of claim 14, wherein each type of the second interface device corresponds to a combination of high and low levels of voltages of a plurality of target ground pins when the first interface device is in a state of connecting the second interface device, and wherein the combination of high and low levels of voltages of the plurality of target ground pins corresponding to different types of the second interface device is different.

16. The circuit according to claim 12 or 13, wherein the voltage of the target ground pin is a digital signal, and the number of the target ground pins is 1;

the control circuit controls the on-off state of a path between the second processor and the first interface in response to the high-low level of the voltage of the target grounding pin.

17. The circuit according to claim 12 or 13, wherein the voltage of a target ground pin is an analog signal and the number of the target ground pins is plural;

the control circuit controls an on-off state of a path between the second processor and the first interface in response to a combination of voltage values of voltages of a plurality of target ground pins.

18. The circuit of claim 17, wherein each type of the second interface device corresponds to a different combination of voltage values of voltages of a plurality of the target ground pins when the first interface device is in a state of connecting the second interface device, and wherein the different types of the second interface device correspond to different combinations of voltage values of voltages of a plurality of the target ground pins.

19. The circuit of claim 12 or 13, wherein the voltage of a target ground pin is an analog signal and the number of the target ground pins is 1;

the control circuit controls the on-off state of a path between the second processor and the first interface in response to a voltage value of a voltage of the target ground pin.

20. The circuit of any of claims 12-19, wherein the first interface device is a left ear component of a wireless headset, the second interface device is a right ear component of the wireless headset, and the path between the second processor and the first interface comprises an audio path; or

21. The circuit of claim 20, wherein the number of the first ground pins is two, one of the first ground pins is connected to a pull-up circuit, and the other of the first ground pins is connected to a pull-down circuit;

the control circuit turns on the charging path or the audio path in response to a voltage of the target ground pin.

22. An access circuit for use with a second interface device, the access circuit comprising: a second interface, wherein:

the second interface is used for connecting with a first interface in a first interface device, wherein the first interface device comprises the identification circuit of any one of claims 1-11 or the system control circuit of any one of claims 12-21;

the second interface comprises at least one second ground pin;

the at least one second grounding pin corresponds to the at least one first grounding pin in the first interface one by one;

the second interface is an interface in the second interface device;

the connection mode of the second grounding pin is related to the voltage of a corresponding target grounding pin when the second interface is connected with the first interface;

the target ground pin is at least a portion of the at least one first ground pin.

23. The circuit of claim 22, wherein the second ground pin is connected in one of five ways:

24. The circuit of claim 22 or 23, wherein the first interface device is a left ear component of a wireless headset and the second interface device is a right ear component of a wireless headset; or

The first interface device is a right ear assembly of the wireless headset, and the second interface device is a left ear assembly of the wireless headset.

25. The circuit of claim 24, wherein if the number of the first ground pins is two, one of the first ground pins is connected to a pull-up circuit, the other of the first ground pins is connected to a pull-down circuit, the target ground pin is the first ground pin connected to the pull-down circuit, the number of the second ground pins is two, and the two second ground pins are connected.

26. An electronic device comprising an identification circuit as claimed in any one of claims 1 to 11 or a system control circuit as claimed in any one of claims 12 to 21 or an access circuit as claimed in any one of claims 22 to 25.