CN110710112A - Turbo编码方法、Turbo编码器及无人机 - Google Patents

Turbo编码方法、Turbo编码器及无人机 Download PDF

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Publication number
CN110710112A
CN110710112A CN201880031265.4A CN201880031265A CN110710112A CN 110710112 A CN110710112 A CN 110710112A CN 201880031265 A CN201880031265 A CN 201880031265A CN 110710112 A CN110710112 A CN 110710112A
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China
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data
bit data
parallel
turbo
caches
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Pending
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CN201880031265.4A
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English (en)
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刘瑛
翟春华
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SZ DJI Technology Co Ltd
Shenzhen Dajiang Innovations Technology Co Ltd
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Shenzhen Dajiang Innovations Technology Co Ltd
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Publication of CN110710112A publication Critical patent/CN110710112A/zh
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2771—Internal interleaver for turbo codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2739—Permutation polynomial interleaver, e.g. quadratic permutation polynomial [QPP] interleaver and quadratic congruence interleaver
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/082—Associative directories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0884—Parallel mode, e.g. in parallel with main memory or CPU
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6563—Implementations using multi-port memories

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Error Detection And Correction (AREA)

Abstract

一种Turbo编码方法、Turbo编码器及无人机，该方法通过获取用于Turbo编码的码块，将码块中的数据分块存储在多个并行的缓存中(101)，从多个并行的缓存中获取并行数据进行Turbo编码(103)。从而实现了Turbo编码时数据的并行存储和并行读取，从而提高了Turbo编码的效率，并且与传统串行的方式相比，能够减少Turbo编码时，内交织产生的中间变量的数量，因而，能够降低Turbo编码器中特定用途集成电路(ASIC)的成本。

Description

PCT国内申请，说明书已公开。

Claims (22)

  1. PCT国内申请，权利要求书已公开。
CN201880031265.4A 2018-05-15 2018-05-15 Turbo编码方法、Turbo编码器及无人机 Pending CN110710112A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/086799 WO2019218130A1 (zh) 2018-05-15 2018-05-15 Turbo编码方法、Turbo编码器及无人机

Publications (1)

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CN110710112A true CN110710112A (zh) 2020-01-17

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US (1) US20210083691A1 (zh)
CN (1) CN110710112A (zh)
WO (1) WO2019218130A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113259992B (zh) * 2021-06-11 2021-10-01 苏州华兴源创科技股份有限公司 码块分割方法、计算机设备及存储介质

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6298463B1 (en) * 1998-07-31 2001-10-02 Nortel Networks Limited Parallel concatenated convolutional coding
US20020015425A1 (en) * 2000-06-29 2002-02-07 Fujitsu Limited Transceiver apparatus
CN101674161A (zh) * 2009-10-15 2010-03-17 华为技术有限公司 解速率匹配方法及装置
CN101777924A (zh) * 2010-01-11 2010-07-14 新邮通信设备有限公司 一种Turbo码译码方法和装置
US20110022801A1 (en) * 2007-12-06 2011-01-27 David Flynn Apparatus, system, and method for redundant write caching
CN102098061A (zh) * 2009-12-15 2011-06-15 上海贝尔股份有限公司 并行Turbo编码器
CN102111163A (zh) * 2009-12-25 2011-06-29 中兴通讯股份有限公司 Turbo编码器及编码方法
US20150014482A1 (en) * 2013-07-15 2015-01-15 Design Intelligence Incorporated, LLC Unmanned aerial vehicle (uav) with inter-connecting wing sections
US20160028513A1 (en) * 2013-12-10 2016-01-28 Telefonaktiebolaget L M Ericsson (Publ) Group-Based Resource Element Mapping for Radio Transmission of Data
US20160204865A1 (en) * 2015-01-09 2016-07-14 Don M. Boroson Link architecture and spacecraft terminal for high rate direct to earth optical communications

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6298463B1 (en) * 1998-07-31 2001-10-02 Nortel Networks Limited Parallel concatenated convolutional coding
US20020015425A1 (en) * 2000-06-29 2002-02-07 Fujitsu Limited Transceiver apparatus
US20110022801A1 (en) * 2007-12-06 2011-01-27 David Flynn Apparatus, system, and method for redundant write caching
CN101674161A (zh) * 2009-10-15 2010-03-17 华为技术有限公司 解速率匹配方法及装置
CN102098061A (zh) * 2009-12-15 2011-06-15 上海贝尔股份有限公司 并行Turbo编码器
CN102111163A (zh) * 2009-12-25 2011-06-29 中兴通讯股份有限公司 Turbo编码器及编码方法
CN101777924A (zh) * 2010-01-11 2010-07-14 新邮通信设备有限公司 一种Turbo码译码方法和装置
US20150014482A1 (en) * 2013-07-15 2015-01-15 Design Intelligence Incorporated, LLC Unmanned aerial vehicle (uav) with inter-connecting wing sections
US20160028513A1 (en) * 2013-12-10 2016-01-28 Telefonaktiebolaget L M Ericsson (Publ) Group-Based Resource Element Mapping for Radio Transmission of Data
US20160204865A1 (en) * 2015-01-09 2016-07-14 Don M. Boroson Link architecture and spacecraft terminal for high rate direct to earth optical communications

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US20210083691A1 (en) 2021-03-18
WO2019218130A1 (zh) 2019-11-21

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