CN110706674B

CN110706674B - Clock recovery device and source driver

Info

Publication number: CN110706674B
Application number: CN201910615738.1A
Authority: CN
Inventors: 金炳局; 全炫奎
Original assignee: Silicon Works Co Ltd
Current assignee: LX Semicon Co Ltd
Priority date: 2018-07-09
Filing date: 2019-07-09
Publication date: 2024-04-19
Anticipated expiration: 2039-07-09
Also published as: KR20200005971A; US10943560B2; KR102507862B1; US20200013370A1; CN110706674A

Abstract

In the clock recovery apparatus of the embodiment, when generating the mask signal to be used in recovering the clock signal embedded in the interface signal, when the mask rising signal for generating the mask signal is located in the data signal interval and the data signal indicates a high level, the mask signal may be generated according to a falling edge of the data signal different from the mask rising signal. A source driver is also provided.

Description

Clock recovery device and source driver

Cross Reference to Related Applications

The present application claims priority from korean patent application No. 10-2018-0079041, filed on 7/9/2018, which is hereby incorporated by reference for all purposes as if fully set forth herein.

Technical Field

Embodiments relate to a technique for recovering an embedded clock from an interface signal, and more particularly, to a clock recovery device and a source driver.

Background

At least two devices may exchange information via an interface signal.

The interface signal is divided into a plurality of unit times, and the value of the field may be recorded for each unit time. Such fields are also referred to as bits. When the interface signal is identified by dividing the interface signal into each unit time, the receiving device may read the value of each bit received through the interface signal.

In order to divide the interface signal into each unit time, a clock signal indicating each unit time is required. The clock signal may be transmitted from the transmitting device to the receiving device together with the interface signal.

The interface signal containing the value of each field may be transmitted and received via separate lines from the clock signal. The receiving device may receive the interface signal through the first line, receive the clock signal through the second line, and use the clock signal to identify the interface signal by dividing the interface signal into portions per unit time, thereby obtaining data from the interface signal.

However, if the interface signal and the clock signal are composed of separate lines, an electromagnetic interference (electromagnetic interference; EMI) problem in which the clock signal and the interface signal interfere with each other may occur, a data sampling error problem may occur due to a difference in transmission delay of each line, and a space allocation problem may occur due to an increase in the number of lines.

In order to solve the above-mentioned problems, the transmission/reception device may transmit/receive a clock signal embedded in an interface signal. This may alleviate EMI problems, data sampling errors problems, and space allocation problems.

In an embedded clock scheme in which a clock signal is embedded in an interface signal, the clock signal may be inserted into some time intervals of the interface signal and transmitted and received. The receiving device may extract the clock signal from the interface signal by using a mask signal indicating the time interval into which the clock signal is inserted.

The mask signal generation circuit may generate a mask signal to indicate a time interval containing a portion of the clock signal inserted therein. However, when the mask signal generation circuit generates the mask signal, there may occur a problem that the time interval of the portion into which the clock signal is inserted cannot be accurately indicated due to the processing delay time of the logic circuit. For example, the clock signal may not be included in the time interval indicated by the mask signal in the interface signal, or the data signal or glitch may be included in the corresponding time interval. In this case, the receiving device cannot recover the clock signal from the interface signal, or the transmitting device may generate the clock signal having characteristics different from those of the intended clock signal.

Disclosure of Invention

In this context, it is an aspect of the present disclosure to provide a technique for accurately recovering a clock signal from an interface signal.

According to an aspect of the present disclosure, a clock recovery apparatus includes: a mask signal generating unit configured to form a rising edge of the mask signal according to the mask rising signal when the interface signal indicates a first level at a point of time when the signal level of the mask rising signal is shifted, and configured to form a rising edge of the mask signal according to a section in which the interface signal is shifted from the second level to the first level when the interface signal indicates a second level different from the first level at the point of time when the signal level of the mask rising signal is shifted; a clock extraction unit configured to generate an extraction clock from an interface signal in a time interval in which the mask signal is activated, the interface signal having the clock signal embedded therein; and a time delay control unit configured to generate a plurality of data clock signals and mask rising signals in a next cycle by time-delaying the extraction clock.

One period of the interface signal may be divided into a plurality of unit times, each unit time including the divided information, and the phase of the mask rising signal may be advanced by K unit times (K is a positive number and a multiple of 0.5) from the phase of the extraction clock.

The interface signal may include a glitch interval and a clock signal interval, and the interface signal may indicate a first level in the glitch interval and a second level in the clock signal interval. The phase of the mask up signal may lead the phase of the glitch interval.

The mask signal generating unit may generate a falling edge of the mask signal according to the extraction clock or a signal obtained by delaying the extraction clock by a predetermined time.

The time delay control unit may include: a delay circuit configured to generate a plurality of data clock signals each having a different phase by time-delaying the extraction clock via a plurality of delay members connected in series, and configured to adjust a time delay degree of each delay member according to the voltage control signal; and a phase difference feedback unit configured to generate a voltage control signal corresponding to a phase difference between one data clock signal and another data clock signal obtained by passing the one data clock signal through a predetermined number of delay members to output the generated voltage control signal to each of the delay members. One period of the interface signal may be divided into a plurality of unit times, each unit time including the divided information, and the delay means may delay the time by 0.5 unit time.

According to another aspect of the present disclosure, a clock recovery apparatus includes: a clock extraction unit configured to generate an extraction clock from an interface signal in a time interval in which the mask signal is activated, the interface signal having the clock signal embedded therein; a mask signal generating unit configured to form a rising edge of the mask signal according to the mask rising signal and configured to form a falling edge of the mask signal according to the extraction clock or a signal obtained by delaying the extraction clock by a predetermined time; and a time delay control unit configured to generate a plurality of data clock signals and mask rising signals in a next cycle by time-delaying the extraction clock.

A time delay may occur between the mask rising signal and the rising edge of the mask signal and between the extraction clock and the falling edge of the mask signal.

According to another aspect of the present disclosure, a source driver includes: a signal receiving unit configured to receive a display signal having a clock signal embedded therein; a clock recovery unit configured to generate a plurality of data clock signals by recovering a clock signal from the display signal; and a data driving unit configured to extract image data from the display signals according to the plurality of data clock signals and configured to drive pixels disposed on the panel according to the image data. The clock recovery unit may generate an extraction clock from the display signal in a time interval in which the mask signal is activated and generate a plurality of data clock signals and the mask signal using the extraction clock, and may control a phase of the mask signal according to a level of a last data bit in a signal interval of the display signal.

As described above, according to an embodiment, a clock signal can be accurately recovered from an interface signal. As an example, according to an embodiment, it is possible to accurately recover a clock signal from an interface signal having a clock signal embedded therein by allowing the mask signal to accurately indicate a portion of the clock signal that is inserted into the interface signal. As another example, according to the embodiment, it is possible to generate a mask signal by compensating for a processing delay time generated in a mask signal generating circuit, thereby reducing inaccuracy of the mask signal due to the processing delay time. As another example, according to the embodiment, it is possible to solve the problem of erroneously recovering the clock signal due to the data signal occurring in the time interval indicated by the mask signal. As another example, according to an embodiment, it is possible to solve the problem that the clock signal is not recovered because the clock signal is not included in the time interval indicated by the mask signal.

Drawings

The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:

Fig. 1 is a configuration diagram showing a general data receiving apparatus.

Fig. 2 is a timing diagram illustrating a main signal in the data receiving apparatus illustrated in fig. 1.

Fig. 3 is a graph showing a time difference between each of the mask up signal and the mask down signal and the mask signal.

Fig. 4 is a configuration diagram showing a display device according to an embodiment.

Fig. 5 is a configuration diagram showing a data transmission apparatus and a data reception apparatus according to an embodiment.

Fig. 6 is a first exemplary configuration diagram showing a clock recovery unit according to an embodiment.

Fig. 7 is a configuration diagram showing a time delay control unit according to an embodiment.

Fig. 8 is a first exemplary timing diagram illustrating a main signal in a clock recovery unit according to an embodiment.

Fig. 9 is a first exemplary timing diagram illustrating a main signal when a mask signal is formed in a data signal interval.

Fig. 10 is a second exemplary timing diagram illustrating a main signal when a mask signal is formed in a data signal interval.

Fig. 11 is a second exemplary timing diagram illustrating a master signal in a clock recovery unit according to an embodiment.

Fig. 12 is a second exemplary configuration diagram showing a clock recovery unit according to an embodiment.

Fig. 13 is a third exemplary timing diagram illustrating a main signal when a mask signal is formed in a data signal interval.

Fig. 14 is a third exemplary timing diagram illustrating a master signal in a clock recovery unit according to an embodiment.

Fig. 15 is a configuration diagram showing a data driving apparatus according to an embodiment.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. When reference numerals are added to elements in each figure, the same elements will be designated by the same reference numerals as much as possible although the same elements are depicted in different figures. Further, in the following description of the present disclosure, when it is determined that a detailed description of known functions and configurations incorporated herein may render the subject matter of the present disclosure rather unclear, this description will be omitted.

In addition, in describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), or the like may be used herein. These terms are only used to distinguish one structural element from other structural elements and the nature, order, sequence, or the like of the corresponding structural elements is not limited by the terms. When one component is described in the specification as being "connected," "coupled," or "joined" to another component, it is understood that the first component may be directly connected, coupled, or joined to the second component, and that the third component may also be "connected," "coupled," and "joined" between the first and second components.

Fig. 1 is a configuration diagram showing a general data receiving apparatus.

Referring to fig. 1, the data receiving apparatus may include a clock recovery unit 10 and a data extraction unit 20.

The clock recovery unit 10 may include a clock extraction unit CKEX, a voltage controlled delay line unit VCDL, a phase feedback unit PDCP, a mask signal generation unit MASKG, and the like.

The clock extraction unit CKEX may generate the extraction clock ECK by a signal in the time interval indicated by the MASK signal MASK in the interface signal IS (in the time interval in which the MASK signal IS activated, for example, where the signal level IS high).

The voltage controlled delay line unit VCDL may generate a plurality of data clock signals DCK by time-delaying the extraction clock ECK. The voltage controlled delay line unit VCDL may control the time delay on the extraction clock ECK such that the phase of one data clock signal of the plurality of data clock signals DCK is synchronized with the phase of the other data clock signal.

For example, the voltage control delay line unit VCDL may transmit one data clock signal obtained by delaying the extraction clock ECK by one unit time as the feedback clock signal feb_ck to the phase feedback unit PDCP, and another data clock signal obtained by delaying the extraction clock ECK by (n+1) unit time as the reference clock signal ref_ck to the phase feedback unit PDCP.

The phase feedback unit PDCP may transmit the voltage control signal VCTR corresponding to the phase difference between the above-mentioned one data clock signal and the other data clock signal to the voltage control delay line unit VCDL. The voltage control delay line unit VCDL may adjust the time delay time of the extraction clock ECK according to the voltage control signal VCTR so that the phase of one data clock signal mentioned above may be synchronized with the phase of the other data clock signal. According to this synchronization, the phase difference between the respective data clock signals may be equal to a unit time in which information is divided.

The voltage control delay line unit VCDL may generate MASK rising signals mask_r and MASK falling signals mask_f and a plurality of data clock signals DCK, and may transmit the generated signals to the MASK signal generating unit MASKG. Herein, the MASK up signal mask_r may be a signal delayed in time from the extraction clock ECK by R (R is a value corresponding to an integer multiple of 0.5) unit time, and the MASK down signal mask_f may be a signal delayed in time from the extraction clock ECK by Q (Q is a value corresponding to an integer multiple of 0.5 and greater than R) unit time.

The MASK signal generating unit MASKG may generate a rising edge of the MASK signal MASK according to the MASK rising signal mask_r and may generate a falling edge of the MASK signal MASK according to the MASK falling signal mask_f, thereby generating the MASK signal MASK.

Meanwhile, when the data clock signal DCK IS generated in the clock recovery unit 10, the data extraction unit 20 may use the latch circuit F/F to latch the interface signal IS according to each data clock signal DCK, thereby generating the data signal DT.

Referring to fig. 2, a data signal DT, a dummy signal DM, and a clock signal CK may be inserted into the interface signal IS. The corresponding bits of the data signal DT may be divided into unit times, and one bit of the data signal DT may be inserted in one unit time. The clock signal CK is a part into which a clock is inserted and may have a size of one unit time or two unit times. The dummy signal DM is a part different from the data signal DT or the clock signal CK, and may be inserted to maintain the interval between the data signal DT and the clock signal CK, or may be inserted as a preliminary section for expansion of the data signal DT.

The MASK signal MASK IS a signal indicating a time interval in which the clock signal CK IS inserted in the interface signal IS, and the clock recovery device may extract the clock signal CK embedded in the interface signal IS from the time interval between the rising edge and the falling edge of the MASK signal MASK. Meanwhile, the clock signal is a signal that repeats with a predetermined period. As depicted in fig. 2, the entire portion CK repeated at predetermined time intervals may be regarded as a clock signal. However, from another perspective, the rising edge of this portion CK may be considered a clock signal.

The clock extraction unit may detect a level change of the interface signal IS in a time interval in which the MASK signal MASK IS maintained at a high level, and may generate the extraction clock ECK when a rising or falling edge occurs in the interface signal IS.

The voltage controlled delay line unit may generate a plurality of data clocks (DCK [ M:1], where M is 2 or a natural number greater than 2) by time-delaying the extraction clock ECK.

The data extraction unit may generate a data signal (DT [ M:1 ]) by locking the interface signal IS at the rising edge of each data clock DCK.

Meanwhile, the master signal generating unit may generate the MASK signal MASK at a time delayed from the extraction clock ECK by a predetermined multiple of a unit time. When one period of the interface signal IS divided into N unit times (N IS a natural number equal to or greater than 2), the main signal generating unit may generate the MASK signal MASK such that a rising edge may be formed at a time point delayed from the extraction clock ECK by (N-0.5) unit times and a falling edge may be formed at a time point delayed from the extraction clock ECK by (n+0.5) unit times. This enables the clock extraction unit to detect the clock signal CK of the interface signal IS at an intermediate point in time of the time interval during which the MASK signal MASK IS maintained at a high level.

The rising and falling edges of the MASK signal MASK are generated by a voltage controlled delay line unit that time delays the extraction clock ECK. The voltage controlled delay line unit may generate the mask rising signal at a time point delayed (N-0.5) from the extraction clock ECK, and may generate the mask falling signal at a time point delayed (n+0.5) unit times.

The MASK signal generating unit may generate the MASK signal MASK using the MASK up signal and the MASK down signal transmitted from the voltage control delay line unit.

Meanwhile, the MASK signal generating unit may form a rising edge of the MASK signal MASK according to the MASK rising signal via the internal circuit, and may form a falling edge of the MASK signal MASK according to the MASK falling signal. However, since a processing delay time occurs in the internal circuit, the rising edge of the MASK signal MASK and the MASK rising signal are not synchronized with each other with a predetermined time difference therebetween, and the falling edge of the MASK signal MASK and the MASK falling signal are not synchronized with each other with a predetermined time difference therebetween.

Referring to fig. 3, a processing delay time Tmask between a rising edge of the MASK signal MASK and the MASK rising signal mask_r may occur, and a processing delay time Tmask between a falling edge of the MASK signal MASK and the MASK falling signal mask_f may occur. Although such a processing delay time Tmask may occur due to the processing delay time of the mask signal generating unit, the processing delay time Tmask may be affected by other factors.

Meanwhile, the MASK signal generating unit may generate the MASK rising signal mask_r and the MASK falling signal mask_f in consideration of the above-described processing delay time Tmask so as to detect the clock signal CK near the center of the high-level interval of the MASK signal MASK.

For example, the MASK signal generating unit may generate the MASK rising signal mask_r at a time point (a time point delayed by a smaller time point) earlier than the processing delay time Tmask by (N-0.5) unit time than the extraction clock ECK, and may generate the MASK falling signal mask_f at a time point (a time point delayed by a smaller time point) earlier than the processing delay time Tmask by (n+0.5) unit time. The processing delay time Tmask may be set to generally 0.5 to 1 unit time.

Meanwhile, as the data transfer rate has recently increased, the unit time has been shortened. Therefore, the processing delay time Tmask becomes gradually longer on a unit time basis. For example, at a conventional data transfer rate, the processing delay time Tmask may correspond to one unit time. If such a data transfer rate is doubled, the processing delay time Tmask may correspond to two unit times.

To reflect the tendency of the data transfer rate to increase, the phase difference between the MASK rising signal mask_r and the extraction clock ECK can be better controlled. For example, if MASK up signal mask_r has conventionally been formed one unit time earlier than the fetch clock ECK, then in recent products with higher data transfer rates MASK up signal mask_r may be formed 2 to 3 unit times earlier than fetch clock ECK.

However, if the phase of the MASK up signal mask_r is formed earlier in this way, the MASK signal MASK is formed much earlier, so that the MASK signal MASK cannot indicate the time interval of the clock signal CK or may indicate the interval of the data signal.

If the time interval indicated by the MASK signal MASK indicates an interval of the data signal, a problem may occur in that the clock extraction unit erroneously recognizes the data signal as the clock signal CK to erroneously generate a clock. When the MASK signal MASK cannot indicate the time interval of the clock signal CK, for example, when the falling edge of the MASK signal MASK leads the rising edge of the clock signal CK, the clock extraction unit may not recognize the clock signal CK.

To solve these problems, embodiments of the present disclosure provide a technique for preventing a clock extraction unit from erroneously interpreting a data signal as a clock signal and a technique for preventing a mask signal from failing to indicate a time interval of the clock signal.

Some of the configurations of this embodiment may be the same as those described with reference to fig. 1 to 3, and configurations in which functions and details are omitted may be understood with reference to the above description.

Referring to fig. 4, the display apparatus 400 may include a plurality of panel driving devices 410, 420, 430, 440, and a display panel 450.

The plurality of data lines DL and the plurality of gate lines GL may be disposed on the display panel 450, and the plurality of pixels may be disposed on the display panel. The pixel may be constituted by a plurality of sub-pixels SP. The subpixels may include red (R), green (G), blue (B), white (W), and the like. One pixel may be constituted of the sub-pixels SP of RGB, the sub-pixels SP of RGBG, the sub-pixels SP of RGBW, and the like. Hereinafter, for convenience of description, one pixel is described as being composed of sub-pixels of RGB.

The panel driving device 410, the panel driving device 420, the panel driving device 430, and the panel driving device 440 are devices that generate signals for displaying images on the display panel 450, and may correspond to the image processing device 410, the data driving device 420, the gate driving device 430, and the data processing device 440.

The gate driving device 430 may supply a gate driving signal of an on voltage or an off voltage to the gate line GL. When a gate driving signal of an on voltage is supplied to the sub-pixel SP, the sub-pixel SP is connected to the data line DL. When the gate driving signal of the off-voltage is supplied to the sub-pixel SP, the connection between the sub-pixel SP and the data line DL is released. The gate driving device 430 may be referred to as a gate driver.

The data driving device 420 may supply the data voltage Vp to the sub-pixel SP through the data line DL. The data voltage Vp supplied to the data line DL may be supplied to the subpixel SP according to a gate driving signal. The data driving device 420 may be referred to as a source driver.

The data processing device 440 may supply control signals to the gate driving device 430 and the data driving device 420. For example, the data processing device 440 may transmit the gate control signal GCS to the gate driving device 430 so that the scan starts. The data processing device 440 may output the image data IMG to the data driving device 420. The data processing device 440 may transmit a data control signal DCS that controls the data driving device 420 to supply the data voltage Vp to each subpixel SP. The data processing device 440 may be referred to as a timing controller.

The image processing device 410 may generate image data IMG and may transmit the image data IMG to the data processing device 440. The image processing apparatus 410 may be referred to as a host (host).

Meanwhile, a communication interface is formed between the data processing apparatus 440 and the data driving device 420, and the data processing apparatus 440 may transmit the data control signal DCS and/or the image data IMG to the data driving device 420.

The data transmission device 510 depicted in fig. 5 may be included in one panel driving device described with reference to fig. 4, and the data reception device 520 may be included in another panel driving device described with reference to fig. 4.

As an example, the data transmission device 510 may be included in a data processing device (see data processing device 440 in fig. 4) and the data receiving device 520 may be included in a data driving device (see data driving device 420 in fig. 4). At this time, the data transmission device 510 may transmit image data or a data control signal as data DT to be transmitted.

As another example, the data transmission device 510 may be included in a data driving device (see data driving device 420 in fig. 4), and the data receiving device 520 may be included in a data processing device (see data processing device 440 in fig. 4). At this time, the data transmission device 510 may transmit the sensing data as the pixels of the data DT to be transmitted.

The data transmission device 510 may include a parallel/serial (P2S) conversion unit 512, a clock insertion unit 514, a transmission unit 516, and the like.

The P2S conversion unit 512 may convert the data DT processed by the parallel communication into data processed by the serial communication. The clock insertion unit 514 may generate the interface signal IS by combining the data DT converted into the serial and the clock CK. The transmission unit 516 may transmit the interface signal IS to the data receiving device 520 through a signal line.

The data receiving device 520 may include an S2P conversion unit 522, a clock recovery unit 524, a receiving unit 526, and the like.

The receiving unit 526 may receive the interface signal IS through a signal line. The clock recovery unit 524 may recover the clock CK from the interface signal IS, may generate the data clock signal DCK, and may transmit the data clock signal DCK to the S2P conversion unit 522. The S2P conversion unit 522 (serial/parallel conversion unit 522) may convert a portion of the data signal inserted in the interface signal IS into parallel data by the data clock signal DCK, thereby restoring the data DT.

When the data transmission device 510 is included in the data processing device described with reference to fig. 4 and the data reception device 520 is included in the data driving device described with reference to fig. 4, the data DT may include image data or a data control signal.

When the data transmission 510 is included in the data driving apparatus described with reference to fig. 4 and the data receiving apparatus 520 is included in the data processing apparatus described with reference to fig. 4, the data DT may be sensing data of pixels.

Referring to fig. 6, the clock recovery unit 524a may include a clock extraction unit CKEX, a mask signal generation unit MASKG, and a time delay control unit 620.

The MASK signal generating unit MASKG may generate the MASK signal MASK according to the MASK rising signal mask_r. The MASK signal generating unit MASKG may form a rising edge of the MASK signal MASK according to the MASK rising signal mask_r.

The MASK signal generating unit MASKG may generate the MASK signal MASK according to the MASK down signal mask_f. The MASK signal generating unit MASKG may form a falling edge of the MASK signal MASK according to the MASK falling signal mask_f.

The MASK signal generating unit MASKG may include an internal circuit (including at least one logic circuit), and may form a rising edge of the MASK signal MASK according to the MASK rising signal mask_r through the internal circuit. At this time, a processing delay time of the internal circuit may occur. Depending on the processing delay time, a predetermined time difference may occur between the rising edges of the MASK rising signal mask_r and the MASK signal MASK.

At the same time, the MASK signal MASK may be transmitted to the clock extraction unit CKEX. The clock extraction unit CKEX may generate the extraction clock ECK by a signal at a time interval indicated by a MASK signal MASK in the interface signal IS in which the clock signal IS embedded.

The time delay control unit 620 may generate the plurality of data clock signals DCK, the MASK rising signal mask_r, and the MASK falling signal mask_f by time-delaying the extraction clock ECK.

The time delay control unit 620 may include a voltage control delay line unit VCDL and a phase difference feedback unit PDCP.

The voltage control delay line unit VCDL may include a delay circuit composed of a plurality of delay members connected in series. Such a delay means may generate a plurality of data clock signals DCK having different phases by time-delaying the extraction clock ECK. Such a delay circuit may adjust the time delay degree of each delay member according to the voltage control signal VCTR.

The phase difference feedback unit PDCP may generate a signal corresponding to a phase difference between the feedback clock feb_ck and the reference clock ref_ck as the voltage control signal VCTR. The phase difference feedback unit PDCP may output the voltage control signal VCTR to a corresponding delay means included in the delay circuit.

The feedback clock feb_ck may be a data clock signal generated by the voltage-controlled delay line unit VCDL. The reference clock ref_ck may be another data clock signal that passes through a predetermined number of delay members with this data clock signal.

For example, one period of the interface signal IS may be divided into N unit times (N IS a natural number equal to or greater than 2) in which information IS divided. The reference clock ref_ck may be a data clock signal generated by delaying the feedback clock feb_ck by N unit times. At this time, if phases of the reference clock ref_ck and the feedback clock feb_ck coincide with each other, the unit time determined by the data receiving apparatus matches the unit time expected by the data transmitting apparatus.

Referring to fig. 7, the time delay control unit 620 may include a voltage control delay line unit VCDL and a phase difference feedback unit PDCP.

The voltage controlled delay line unit VCDL may include a plurality of delay members DS. Each delay means DS may be an inverter accompanied by a time delay, and two delay means DS may be responsible for a time delay of one unit time.

The voltage control delay line unit VCDL may generate a plurality of data clock signals (data clock signals DCK [ N:1 ]) using a plurality of delay means DS.

The voltage control delay line unit VCDL may output one data clock signal among a plurality of data clock signals (data clock signals DCK [ N:1 ]) as a feedback clock feb_ck, and may output another data clock signal as a reference clock ref_ck. When one period of the interface signal is divided into N unit times, the reference clock ref_ck may be a clock obtained by delaying the feedback clock feb_ck by N unit times.

The phase difference feedback unit PDCP may include a phase detector PD, a charge pump CP, and a loop filter LF.

The phase detector PD may selectively output the UP signal UP and the down signal DN to correspond to a phase difference between the feedback clock feb_ck and the reference clock ref_ck. The charge pump CP may generate an output voltage to correspond to the UP signal UP and the down signal DN, and the loop filter LF may generate the voltage control signal VCTR according to the output voltage of the charge pump CP.

The voltage control signal VCTR may be a driving voltage of the delay member DS. At this time, when the voltage of the voltage control signal VCTR is high, the current of the delay member DS may be increased to reduce the time delay of the delay member DS. Conversely, when the voltage of the voltage control signal VCTR is low, the current of the delay member DS may be reduced to increase the time delay of the delay member DS.

The VCDL may output MASK up signal mask_r and MASK down signal mask_f and a data clock signal DCK.

The MASK rising signal mask_r may be a signal whose phase is formed one to two unit times earlier than the conventional MASK rising signal mask_r'. The MASK down signal mask_f may be a signal whose phase is formed one to two unit times earlier than the conventional MASK down signal mask_f'.

Referring to fig. 8, one period of the interface signal IS divided into a plurality of unit times UI in which information IS divided. Each unit time UI may indicate each bit of data of the data signal DT. A data signal DT having M bits (M IS 2 or a natural number greater than 2) may be included in each period of the interface signal IS. The dummy DM interval may be disposed after the data signal DT and the clock signal CK interval may be disposed after the dummy DM interval.

The dummy signal DM is a part different from the data signal DT or the clock signal CK, and may be inserted to maintain a space between the data signal DT and the clock signal CK, or may be inserted as a preliminary section for expansion of the data signal DT. The dummy DM interval may correspond to one unit time or two unit times as depicted in fig. 8.

Preferably, a rising edge of the MASK signal MASK is formed in the dummy signal DM interval and a falling edge of the MASK signal MASK is formed in the clock signal CK interval. The MASK signal generating unit may generate the MASK rising signal mask_r in consideration of the processing delay time Tmask.

To reflect the increase in the processing delay time Tmask based on the unit time UI, the phase of the MASK rising signal mask_r may be advanced by the unit time UI by the phase L (L is a positive number and is a multiple of 0.5) of the conventional MASK rising signal mask_r'. The phase of MASK up signal mask_r may be advanced by a unit time relative to the extraction clock ECK by a phase K (K is a positive number and a multiple of 0.5) of the extraction clock ECK.

Meanwhile, since the phase of the MASK rising signal mask_r is formed earlier, a point of time indicated by the MASK rising signal mask_r (e.g., when the signal level of the MASK rising signal mask_r shifts) may correspond to the data signal DT interval. For example, the point in time indicated by mask_R may correspond to the last data signal (DT [ M ]) interval. At this time, if the processing delay time Tmask is equal to or longer than a predetermined time, a rising edge of the MASK signal MASK generated according to the MASK rising signal mask_r may correspond to the dummy signal DM interval. However, if the processing delay time Tmask becomes shorter than expected due to a deviation in a product or the like, a problem may occur in that the rising edge of the MASK signal MASK may be formed in a data signal DT interval different from the dummy signal DM interval.

Referring to fig. 9, the MASK rising signal mask_r may be formed in the data signal DT interval. In particular, the MASK up signal mask_r may be formed in the last data signal (last data signal DT [ M ]) interval. When the processing delay time Tmask is short, some intervals (a part of intervals having a high level) of the MASK signal MASK generated according to the MASK rising signal mask_r may overlap with the data signal DT intervals (particularly with the last data signal (DT [ M ]) intervals).

The clock extraction unit may generate the extraction clock ECK at a point of time when the interface signal IS has a high level in a time interval indicated by the MASK signal MASK. In the dummy signal DM interval, the interface signal IS may indicate a first level (e.g., a low level), and in the clock signal CK interval, the interface signal IS may indicate a second level (e.g., a high level). If the time interval indicated by MASK signal MASK extends over the dummy signal DM interval and the clock signal CK interval, the clock extraction unit may generate the extraction clock ECK to correspond to a point in time when the interface signal IS shifted from the dummy signal DM interval to the clock signal CK interval.

Meanwhile, in the case where a part of the interval of the MASK signal MASK overlaps the data signal DT, when the data signal DT indicates a first level (e.g., a low level in the overlapping interval), the clock extraction unit may normally generate the extraction clock ECK in the clock signal CK interval in which the second level occurs. For example, if a portion of the interval of the MASK signal MASK overlaps with the last data signal (DT [ M ]) interval and the last data signal (DT [ M ]) indicates a first level (e.g., the value of the last data bit is 0), the clock extraction unit may normally generate the extraction clock ECK in the clock signal CK interval occurring at the second level.

In comparison with fig. 9, in the timing chart of fig. 10, the last data signal (DT [ M ]) overlapped with the MASK signal MASK indicates a second level (e.g., a high level).

The clock extraction unit may generate the extraction clock ECK at a point in time when the interface signal IS has the second level in a time interval indicated by the MASK signal MASK. However, since the last data signal (DT [ M ]) indicates the second level (e.g., the value of the last data bit is 1) in the time interval indicated by the MASK signal MASK, the clock extraction unit may generate the extraction clock ECK in synchronization with the data signal DT according to the value.

In order to solve these problems, the MASK signal generating unit may monitor the interface signal IS at a point of time indicated by the MASK rising signal mask_r, may form a rising edge of the MASK signal MASK according to the MASK rising signal mask_r when the interface signal IS indicates the first level, and may form a rising edge of the MASK signal MASK according to a signal for shifting the interface signal IS from the second level to the first level when the interface signal IS indicates the second level different from the first level at the point of time indicated by the MASK rising signal mask_r.

Referring to fig. 11, the MASK signal generating unit may form a rising edge of the MASK signal MASK according to the MASK rising signal mask_r when the interface signal IS indicates a first level in a time point indicated by the MASK rising signal mask_r, and may form a rising edge of the MASK signal MASK according to a signal for shifting the interface signal IS from the second level to the first level when the interface signal IS indicates a second level different from the first level at the time point indicated by the MASK rising signal mask_r.

The interface signal IS may include a dummy signal DM interval and a clock signal CK interval that are sequentially arranged, and the phase of the MASK rising signal mask_r may be advanced from the dummy signal DM interval. The data signal DT interval may lead the dummy signal DM interval. Thus, the MASK up signal mask_r may correspond to the dummy DT interval. In particular, the MASK up signal mask_r may be formed to correspond to a last data signal (DT [ M ]) interval.

The time during which the MASK signal generation unit generates the rising edge of the MASK signal MASK (that is, the processing delay time Tmask) may be shorter than 0.5 unit time.

When the dummy signal DM interval corresponds to two unit times, the phase of the MASK rising signal mask_r may be formed to advance the phase of the extraction clock ECK by 2.5 unit times. At this time, when the processing delay time Tmask of the MASK signal generating unit is less than 0.5 unit time, rising edges of the MASK signal MASK may be arranged at intervals of the data signal DT.

When the dummy signal DM interval corresponds to one unit time, the phase of the MASK rising signal mask_r may be formed to advance the phase of the extraction clock ECK by 1.5 unit times. At this time, the processing delay time Tmask of the MASK signal generating unit is less than 0.5 unit time, and rising edges of the MASK signal MASK may be arranged at intervals of the data signal DT.

Meanwhile, when the data signal DT indicates a first level (e.g., a low level and 0 as a bit value) at a point of time indicated by the MASK rising signal mask_r while monitoring the interface signal IS and the MASK rising signal mask_r, the MASK signal generating unit may generate the MASK signal MASK according to the MASK rising signal mask_r. When the data signal DT indicates a second level (e.g., a high level and 1 as a bit value) at a point of time indicated by the MASK rising signal mask_r, the MASK signal generating unit may generate the MASK signal MASK according to a signal (e.g., the data signal DT) shifted from the second level to the first level in a falling edge of the data signal DT.

According to this control, there is no problem in that the MASK signal MASK overlaps the data signal DT of the second level (e.g., high level).

Meanwhile, a mask down signal may be generated together with a mask up signal. However, if the mask down signal is formed much earlier together with the mask up signal, a problem arises in that the mask down signal is located in the glitch interval and even the falling edge of the mask signal according to the mask down signal is also located in the glitch interval.

The second example described with reference to fig. 12 can solve the above-described problem by generating the falling edge of the mask signal according to the extraction clock different from the mask falling signal alone.

Referring to fig. 12, the clock recovery unit 524b may include a clock extraction unit CKEX, a mask signal generation unit MASKG, and a time delay control unit 620.

The MASK signal generating unit MASKG may generate the MASK signal MASK according to the extraction clock ECK. The MASK signal generating unit MASKG may form a falling edge of the MASK signal MASK according to the extraction clock ECK. Alternatively, the MASK signal generating unit MASKG may generate the MASK signal MASK according to a signal obtained by delaying the extraction clock ECK by a predetermined time. The MASK signal generating unit MASKG may form a falling edge of the MASK signal MASK according to a signal obtained by delaying the extraction clock ECK by a predetermined time.

The MASK signal generating unit MASKG may form a rising edge of the MASK signal MASK according to the MASK rising signal mask_r through the first internal circuit while including the first internal circuit (including at least one logic circuit). At this time, a processing delay time of the first internal circuit may occur. According to such a processing delay time, a predetermined time difference may occur between the MASK rising signal mask_r and the rising edge of the MASK signal MASK.

The MASK signal generating unit MASKG may form a falling edge of the MASK signal MASK according to the extraction clock ECK through the second internal circuit while including the second internal circuit (including at least one logic circuit). At this time, a processing delay time of the second internal circuit may occur. According to such a processing delay time, a predetermined time difference may occur between the falling edges of the extraction clock ECK and the MASK signal MASK.

The processing delay time between the rising edges of the MASK rising signal mask_r and the MASK signal MASK may be within 0.5 unit time, and the processing delay time between the falling edges of the extraction clock ECK and the MASK signal MASK may be within 0.5 unit time.

When the MASK down signal IS located in the dummy signal interval and the processing delay time required to generate the falling edge of the MASK signal MASK using the MASK down signal IS within 0.5 unit time, the time interval indicated by the MASK signal MASK may be included in the dummy signal interval, whereby the clock extraction unit may not extract the clock signal from the interface signal IS.

On the other hand, when the MASK signal generating means generates the falling edge of the MASK signal MASK according to the extraction clock ECK, the MASK signal MASK overlaps with the clock signal by at least the above-described processing delay time.

Referring to fig. 13, the MASK rising signal mask_r may be formed in the data signal DT interval. In particular, the MASK up signal mask_r may be formed in the last data signal (DT [ M ]). When the processing delay time Tmask is short, a part of the interval of the MASK signal MASK (e.g., a part of the interval having a high level) generated according to the MASK rising signal mask_r may overlap with the interval of the data signal DT (particularly, with the interval of the last data signal (DT [ M ])).

The MASK signal MASK may have the same high level interval as that of the dummy signal interval. In this condition, when the rising edge of the MASK signal MASK is located in the data signal DT interval, the falling edge of the MASK signal MASK is located in the dummy signal DM interval.

Since the clock extraction unit receiving such MASK signal MASK does not recognize that the interface signal IS indicates the second level (e.g., high level) in the time interval indicated by the MASK signal MASK, the clock extraction unit may not generate the extraction clock ECK.

Referring to fig. 14, the MASK signal generating unit may form a rising edge of the MASK signal MASK according to the MASK rising signal mask_r. At this time, the MASK rising signal mask_r may be located in the data signal DT interval, and even the rising edge of the MASK signal MASK may be located in the data signal DT interval because the processing delay time Tmask is short.

The MASK signal generating unit may form a falling edge of the MASK signal MASK according to the extraction clock ECK or a signal obtained by delaying the extraction clock ECK by a predetermined time. When the MASK signal generating unit generates the falling edge of the MASK signal MASK according to the extraction clock ECK, the phase of the falling edge of the MASK signal MASK may occur to be delayed by the processing delay time Tmask with respect to the phase of the extraction clock ECK.

Referring to fig. 15, the data driving apparatus 420 may include a signal receiving unit 1510, a clock recovery unit 1520, and a data driving unit 1530.

The signal receiving unit 1510 may receive a display signal DPS having a clock signal embedded therein from a data processing device. The display signal DPS is an interface signal and includes a data control signal, image data, etc. as data, and a clock signal may be embedded in the display signal DPS.

The clock recovery unit 1520 may recover a clock signal from the display signal DPS to generate a plurality of data clock signals DCK.

The data driving unit 1530 may extract image data from the display signal DPS according to a plurality of data clock signals DCK, and may generate a data voltage Vdata according to the image data to drive pixels disposed on the panel.

The clock recovery unit 1520 may generate the extraction clock by a time interval indicated by a mask signal in the display signal DPS, and may generate a plurality of data clock signals and the mask signal using the extraction clock. The phase of the mask signal may be changed according to the level of the last data bit in the signal interval of the display signal. For example, the phase of the mask signal may lead the phase of the mask signal when the last data bit is 0.

The clock recovery unit may generate a mask up signal for forming a rising edge of the mask signal, and the mask up signal may be generated in a signal interval of the last data bit.

The clock recovery unit may form a rising edge of the mask signal according to the mask rising signal when the last data bit is at a first level, and may form a rising edge of the mask signal according to a time when a signal interval of the last data bit is terminated when the last data bit is at a second level different from the first level.

In the display signal, a glitch interval may occur after the last data bit.

The clock recovery unit may generate a falling edge of the mask signal according to the extraction clock or may generate a falling edge of the mask signal according to a signal obtained by delaying the extraction clock by a predetermined time.

The display signal may be a serial signal, and the data driving unit may include a serial/parallel converting unit converting a portion of image data in the display signal into parallel data.

Because terms such as "comprising," "including," and "having" mean that the corresponding elements may be present unless specifically stated to the contrary, it is to be understood that other elements may be additionally included, rather than omitting such elements. All technical, scientific or other terms are used in accordance with the meanings as understood by those skilled in the art unless defined to the contrary. Common terms as seen in dictionaries should be interpreted in the context of the relevant art and should not be interpreted too ideally or deviate from reality unless the present disclosure explicitly defines them.

Although the preferred embodiments of the present disclosure have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the embodiments as disclosed in the accompanying claims. Accordingly, the embodiments disclosed in the present disclosure are intended to illustrate the scope of the technical idea of the present disclosure, and the scope of the present disclosure is not limited by the embodiments. The scope of the present disclosure should be construed based on the appended claims in such a manner that all technical ideas included in the scope equivalent to the claims belong to the present disclosure.

Claims

1. A clock recovery apparatus comprising:

A mask signal generating unit configured to form a rising edge of a mask signal according to a mask rising signal when a last data bit in a period of an interface signal is a first level, and configured to form the rising edge of the mask signal according to a time when a signal interval of the last data bit ends when the last data bit is a second level different from the first level;

A clock extraction unit configured to generate an extraction clock from the interface signal in a time interval in which the mask signal is activated, the interface signal having a clock signal embedded therein; and

A time delay control unit configured to generate a plurality of data clock signals and the mask rising signal in a next cycle by time-delaying the extraction clock,

Wherein the mask up signal is generated within the signal interval of the last data bit.

2. The clock recovery device of claim 1, wherein one period of the interface signal is divided into a plurality of unit times, each unit time including the divided information, and a phase of the mask rising signal leads a phase of the extraction clock by K unit times, where K is a positive number and is a multiple of 0.5.

3. The clock recovery device of claim 1, wherein the interface signal includes a glitch interval and a clock signal interval, and the interface signal indicates the first level in the glitch interval and indicates the second level in the clock signal interval.

4. A clock recovery apparatus as claimed in claim 3, wherein the phase of the mask up signal leads the phase of the glitch interval.

5. The clock recovery apparatus according to claim 1, wherein the mask signal generation unit generates the falling edge of the mask signal according to the extraction clock or a signal obtained by delaying the extraction clock by a predetermined time.

6. The clock recovery apparatus of claim 1, wherein the time delay control unit comprises

A delay circuit configured to generate a plurality of data clock signals each having a different phase by time-delaying the extraction clock via a plurality of delay members connected in series, and configured to adjust a time delay degree of each delay member according to a voltage control signal, an

And a phase difference feedback unit configured to generate the voltage control signal corresponding to a phase difference between one data clock signal and another data clock signal obtained by the one data clock signal passing through a predetermined number of delay members to output the generated voltage control signal to each delay member.

7. The clock recovery device of claim 6, wherein one period of the interface signal is divided into a plurality of unit times, each unit time includes the divided information, and each delay means delays a time by 0.5 unit time.

8. A source driver, comprising:

a signal receiving unit configured to receive a display signal having a clock signal embedded therein;

A clock recovery unit configured to generate a plurality of data clock signals by recovering the clock signal from the display signal; and

A data driving unit configured to extract image data from the display signals according to the plurality of data clock signals and configured to drive pixels disposed on a panel according to the image data,

Wherein the clock recovery unit generates an extraction clock from the display signal and generates the plurality of data clock signals and the mask signal using the extraction clock in a time interval in which the mask signal is activated, and controls a phase of the mask signal according to a level of a last data bit in a period of the display signal,

Wherein the clock recovery unit generates a mask up signal for forming a rising edge of the mask signal, and the mask up signal is generated in a signal interval of the last data bit, and

Wherein the clock recovery unit

Forming the rising edge of the mask signal according to the mask rising signal when the last data bit is a first level, and

The rising edge of the mask signal is formed according to a time when the signal interval of the last data bit ends when the last data bit is a second level different from the first level.

9. The source driver of claim 8, wherein a glitch interval occurs after the last data bit in the display signal.

10. The source driver according to claim 8, wherein the clock recovery unit generates a falling edge of the mask signal according to the extraction clock or a signal obtained by delaying the extraction clock by a predetermined time.

11. The source driver of claim 8, wherein the display signal is a serial signal and the data driving unit comprises a serial/parallel conversion unit configured to convert a portion of the image data in the display signal into parallel data.