CN110702381A

CN110702381A - Packaging method and monitoring device for integrity monitoring of DOE (data object analysis)

Info

Publication number: CN110702381A
Application number: CN201910926090.XA
Authority: CN
Inventors: 李安; 陈驰; 蒋建华
Original assignee: Shenzhen Ansijiang Technology Co Ltd
Current assignee: Shenzhen Ansijiang Technology Co Ltd
Priority date: 2019-09-27
Filing date: 2019-09-27
Publication date: 2020-01-17

Abstract

The invention discloses a packaging method and a monitoring device for DOE integrity monitoring, which belong to the technical field of photoelectricity and comprise the following steps: 1) manufacturing a plurality of microstructures of DOE units on a substrate wafer; 2) plating a metal layer on the surface of the whole substrate wafer by adopting a metal deposition PVD process; 3) spraying a photoresist layer on the metal layer, covering a mask plate with a preset pattern, and processing through a photoetching process to obtain a metal circuit, a metal bonding pad and a metal mark; 4) covering a cover wafer on the whole substrate wafer; 5) cutting the whole obtained in the step 4) to obtain a plurality of DOE units. Only one photoetching process is needed, and the circuit, the bonding pad and the mark can be completed together. Greatly simplifying the process and reducing the manufacturing cost.

Description

Packaging method and monitoring device for integrity monitoring of DOE (data object analysis)

Technical Field

The invention relates to the field of photoelectric technology, in particular to a packaging method and a monitoring device for DOE integrity monitoring.

Background

Cameras and projectors have been widely used in various electronic products. For example, in various common products such as smart phones, tablets, and personal computers, cameras are already an indispensable device. In recent years, it has become a trend to integrate micro projectors into these electronic products as well.

The functions brought by the projectors can greatly enrich the experience of users and improve the competitiveness of products. For example, the projector can be used in a 3D structured light module to project a specific pattern, and then can be used to realize accurate modeling of a three-dimensional scene in cooperation with a receiver (e.g., a camera) and a specific algorithm, so that the projector can be used for gesture recognition, posture recognition, three-dimensional scene modeling and face recognition. Especially, 3D face recognition is incomparable with 2D face recognition in terms of experience, security, and the like because one-dimensional information is added. Also, the reliability and security of 3D face recognition are significantly better than those of conventional biometric recognition, such as fingerprint recognition.

Diffractive Optical Elements (DOEs) have been widely used in various micro projectors due to their special optical properties, and the DOEs enable the projectors to project the same effect patterns, and at the same time, reduce the size of the projectors and the production cost, which makes it practical to integrate the projectors into widely used portable mobile terminals, such as smart phones.

Generally, a DOE is a relatively complex micro-nano passive optical device, which can normally split a single light beam, that is, a light beam can be split into a plurality of light beams after passing through the DOE, the DOE can be generally divided into two types, one is an amplitude type, and the other is a phase type, because the amplitude type DOE can cause loss of optical energy, and the DOE is not easy to manufacture when the microstructure size requirement of the DOE is very fine, the phase type DOE is widely used at present. The phase-type DOE can be divided into a periodic type and a random type according to the arrangement of the microstructures, wherein the microstructures of the periodic DOE are repeatedly arranged; the arrangement of random DOE microstructures is not regular.

In any DOE, when the microstructure of the DOE is damaged and the integrity of the DOE is lost, the diffraction of the light beam passing through the DOE is damaged, so that the light beam cannot be separated into a plurality of beams according to a preset mode, and the energy of a certain outgoing light beam is enhanced, generally, zero-order diffracted light is enhanced, so that damage may be caused in the application to human beings and other organisms, for example, retina burn may be caused by excessively strong light energy. Therefore, monitoring of the state of the DOE is essential in many products, and a traditional monitoring method indirectly infers the state of the DOE by simply monitoring the reflected light intensity of the DOE, for example, when diffraction is damaged, the reflected light intensity may have a certain change, and the monitoring precision of this method is low, for example, patents CN207096666U, CN10778336A, CN108088656A, etc.; moreover, the DOE state is packaged and monitored by constructing a resistor or capacitor structure through a conductive film such as ITO, and the DOE monitoring process is complex and has high manufacturing cost.

The above background disclosure is only for the purpose of assisting understanding of the concept and technical solution of the present invention and does not necessarily belong to the prior art of the present patent application, and should not be used for evaluating the novelty and inventive step of the present application in the case that there is no clear evidence that the above content is disclosed at the filing date of the present patent application.

Disclosure of Invention

The invention aims to provide a packaging method and a monitoring device for DOE integrity monitoring, which greatly simplify the process and lower the manufacturing cost.

In order to achieve the above object, the present invention provides a packaging method for DOE integrity monitoring, which includes the following steps:

1) manufacturing a plurality of microstructures of DOE units on a substrate wafer;

2) plating a metal layer on the surface of the whole substrate wafer by adopting a metal deposition PVD process;

3) spraying a photoresist layer on the metal layer, covering a mask plate with a preset pattern, and processing through a photoetching process to obtain a metal circuit, a metal bonding pad and a metal mark;

4) covering a cover wafer on the whole substrate wafer;

5) cutting the whole obtained in the step 4) to obtain a plurality of DOE units.

In the technical scheme, only one photoetching process is needed, and the circuit, the bonding pad and the mark can be completed together. Greatly simplifying the process and reducing the manufacturing cost.

Preferably, in step 1), the microstructure is formed by one of a semiconductor photolithography process, a nanoimprint process, and a precision injection molding process. If the semiconductor photoetching process or the nano-imprinting process is used for manufacturing, the corresponding substrate wafer is made of glass; if the precision injection molding process is used, the corresponding substrate wafer is made of plastic material, such as PC, PMMA, etc.

Preferably, in step 2), the metal layer includes a buffer layer, a main layer, and an oxidation preventing layer in this order. The buffer layer is generally made of metal titanium, the main layer is generally made of metal copper, and the anti-oxidation layer is generally made of nickel and gold.

Preferably, in step 2), the thickness of the metal layer is 200nm to 2 um.

Preferably, in step 4), the cover wafer and the base wafer are bonded together using a bonding process.

The invention provides a monitoring device for DOE integrity monitoring, which comprises:

the DOE unit is manufactured by adopting the packaging method for monitoring the integrity of the DOE;

and a peripheral monitoring circuit connected to the DOE unit by a wire.

Preferably, the DOE unit comprises a microstructure Die region and a non-active region surrounding the microstructure Die region, wherein the non-active region is used for structural buffering and packaging process functions.

Preferably, the area of the microstructure Die is square, and the size of the area is 100-500 nm.

Preferably, the non-effective area is provided with:

the metal circuit is used for surrounding the micro-structure Die area and does not interfere with the micro-structure Die area;

the metal pads form external connecting contacts, and comprise two metal pads and are used for connecting the peripheral monitoring circuit;

and the metal mark serves as a para mark of the DOE unit.

Two metal pads are connected with a peripheral monitoring circuit, when the DOE unit is damaged and loses integrity, the metal circuit is damaged, so that breakage occurs, the monitoring circuit detects the damage of the metal circuit and feeds back a signal to a control circuit, and the system judges and generates a preset countermeasure according to a preset program, such as reducing the luminous power of a light source or closing operation.

Compared with the prior art, the invention has the beneficial effects that:

compared with the prior art, the packaging method and the monitoring device for DOE integrity monitoring have the advantages of greatly simplified process and lower manufacturing cost. In the existing DOE conductive film type packaging process, a resistor or capacitor circuit pattern surrounding the DOE is made of a conductive film material, such as a common ITO material, but a bonding pad and a mark are not required to be made of a metal material, so that two photoetching processes are required in the DOE packaging process, one photoetching process is used for making the conductive film circuit pattern, and the other photoetching process is used for making the bonding pad and the mark.

Drawings

FIG. 1 is a schematic view of a substrate wafer with a DOE microstructure according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an unpackaged DOE unit according to an embodiment of the present invention;

FIG. 3 is a schematic view of a DOE unit used to perform a PVD process according to an embodiment of the invention; wherein (a) is a top view and (b) is a cross-sectional view;

FIG. 4 is a schematic diagram of a DOE unit after metal etching is performed according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of the bonding of the cover wafer and the base wafer in the embodiment of the present invention;

fig. 6 is a schematic diagram illustrating connection between the packaged DOE unit and the peripheral monitoring circuit according to the embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described with reference to the following embodiments and accompanying drawings. It should be emphasized that the following description is merely exemplary in nature and is not intended to limit the scope of the invention or its application.

Examples

The packaging method for DOE integrity monitoring in this embodiment includes the following steps:

1) manufacturing a plurality of microstructures of DOE units on a substrate wafer; the microstructure is completed by one of a semiconductor lithography process, a nanoimprint process, and a precision injection molding process.

2) Plating a metal layer on the surface of the whole substrate wafer by adopting a metal deposition PVD process; the thickness of the metal layer is 200 nm-2 um, and the metal layer sequentially comprises a buffer layer, a main layer and an anti-oxidation layer.

3) And spraying a photoresist layer on the metal layer, covering a mask plate with a preset pattern, and processing through a photoetching process to obtain a metal circuit, a metal bonding pad and a metal mark.

4) A cover wafer is placed over the entire base wafer and the cover wafer 20 is bonded to the base wafer using a bonding process.

Referring to fig. 6, the monitoring device for DOE integrity monitoring of the present embodiment includes:

and a peripheral monitoring circuit connected to the DOE unit by a wire.

Referring to fig. 1, there is a base wafer 10 with the basic DOE microstructure formed thereon, typically having dimensions of 3 inches, 6 inches, 8 inches, or even 12 inches. The microstructure of each DOE unit 100 on the substrate wafer 10 is generally completed by one of a semiconductor lithography process, a nanoimprint process, and a precision injection molding process, the dimension of the microstructure is generally within a range of 100-500 nm, and due to the existence of the microstructure, each DOE unit 100 can realize diffraction splitting on a light beam. If the semiconductor photoetching process or the nano-imprinting process is used for manufacturing, the corresponding substrate wafer 10 is made of glass; if a precision injection molding process is used, the corresponding substrate wafer 10 is made of plastic, such as PC, PMMA, etc. Typically, a wafer can be diced to produce 1000-4000 DOE units 100.

As shown in fig. 2, before the DOE packaging process is performed on the base wafer 10, the DOE unit 100 includes a microstructure Die region 101 and an inactive region 102. The microstructure Die area 101 is generally completed by one of a semiconductor photoetching process, a nano-imprinting process and a precision injection molding process, and the dimension of the microstructure is generally within the range of 100-500 nm. The inactive area 102 is a portion of the base wafer 10 itself, which is not subjected to any processing, and is generally smooth and transparent, and functions as a structure buffer area and a packaging process active area.

As shown in fig. 3 (a), a metal layer 103 is first plated on the entire surface of the entire substrate wafer 10 by a metal deposition PVD process, and the metal layer 103 includes multiple layers in practical operation, such as a buffer layer of metal titanium, a main layer of metal copper, and an oxidation-resistant layer of nickel gold, which are common plating requirements of the PVD process in the industry. Fig. 3 (b) is a cross-sectional view, and the thickness of the metal layer 103 is generally between 200nm and 2um, and can be increased or decreased according to the actual product requirement.

Next, a photoresist layer is further sprayed on the metal layer 103, a mask plate with a predetermined pattern is covered, and then the processes of exposure, developing and photoresist removal and metal etching are sequentially performed, these process steps are collectively referred to as a photolithography process, and are mature in the semiconductor industry, and detailed technical description is not provided in this embodiment. The metal wiring 1031, the metal pad 1032 and the metal mark 1033 shown in fig. 4 are obtained, and the shapes of the wiring, the shapes of the metal pad and the shapes of the metal mark are only schematic and can be made into various shapes according to the product requirements. The main role of the metal wiring 1031 is to surround the microstructure Die region 101 without interfering and overlapping with the microstructure Die region 101. The metal pads 1032 function to form external connection contacts, one on each side of the board, to be connected to peripheral inspection lines on subsequent products. The metal pad 1032 is electrically connected to the metal wiring 1031. The metal mark 1033 serves as an alignment mark for the DOE unit 100, and the assembly position of the DOE unit 100 in the optical system product is required to be highly accurate, so that the metal mark 1033 can accurately control the assembly position of the DOE unit 100 in the system.

Compared with the existing DOE conductive film type packaging process, the resistor or capacitor circuit pattern surrounding the DOE is made of a conductive film material, such as a common ITO material, but a bonding pad and a mark can not be made of a metal material, so that two photoetching processes are needed in the DOE packaging process, one photoetching process is used for making the conductive film circuit pattern, and the other photoetching process is used for making the bonding pad and the mark. Meanwhile, the bonding force between the conductive film and the substrate wafer made of plastic material is problematic, so that the DOE element manufactured by using the precision injection molding process cannot be packaged, and the precision injection molding process is being developed in a large scale due to the cost advantage, and will be the mainstream of the DOE manufacturing technology in the future.

Finally, a cover bonding process is performed, and as shown in fig. 5, a cover wafer 20 is covered on the whole substrate wafer 10, and fig. 5 illustrates the case of a single DOE unit 100. The cover wafer 20 may be made of glass or plastic, and the surface thereof is smooth and transparent, and functions to seal and protect the microstructure Die area 101, the metal wiring 1031, the metal pad 1032, and the metal mark 1033 from the influence of external environmental conditions. The cover wafer 20 and the base wafer 10 are bonded together by using a bonding process, and then cutting and testing processes are performed to finally produce a DOE unit 100 subjected to a complete packaging process.

As shown in fig. 6, in an optical system product of the DOE unit 100, such as a 3D structured light micro-projector, two metal pads 1032 of the DOE unit are connected to the peripheral monitoring circuit 30, when the DOE unit 100 is damaged and loses integrity, the metal wire 1031 is damaged and then broken, at this time, the monitoring circuit 30 detects the damage of the metal wire 1031, and feeds back a signal to the control circuit, and the system determines to generate a predetermined countermeasure according to a predetermined formula, such as reducing the light emitting power of the light source or turning off the operation. The specific peripheral circuit connection mode and monitoring process vary with different product requirements, and this embodiment is not detailed, but only illustrated in fig. 6.

The foregoing is a more detailed description of the invention in connection with specific/preferred embodiments and is not intended to limit the practice of the invention to those descriptions. It will be apparent to those skilled in the art that various substitutions and modifications can be made to the described embodiments without departing from the spirit of the invention, and these substitutions and modifications should be considered to fall within the scope of the invention.

Claims

1. A packaging method for DOE integrity monitoring, comprising the steps of:

4) covering a cover wafer on the whole substrate wafer;

2. The packaging method for DOE integrity monitoring as claimed in claim 1, wherein in step 1), the microstructure is formed by one of a semiconductor lithography process, a nanoimprint process and a precision injection molding process.

3. The encapsulation method for DOE integrity monitoring according to claim 1, wherein in step 2), the metal layer sequentially comprises a buffer layer, a main layer and an oxidation prevention layer.

4. The packaging method for DOE integrity monitoring as claimed in claim 1, wherein in step 2), the thickness of the metal layer is 200nm to 2 um.

5. The packaging method for DOE integrity monitoring as claimed in claim 1, wherein in step 4), the cover wafer and the base wafer are bonded together using a bonding process.

6. A monitoring device for DOE integrity monitoring, comprising:

the DOE unit is manufactured by the packaging method for DOE integrity monitoring as claimed in any one of claims 1-5;

and a peripheral monitoring circuit connected to the DOE unit by a wire.

7. The monitoring device for DOE integrity monitoring as claimed in claim 6, wherein the DOE unit includes a microstructure Die region and an inactive region surrounding the microstructure Die region, the inactive region being used for structural buffering and packaging process functions.

8. The monitoring device for DOE integrity monitoring as claimed in claim 7, wherein the microstructure Die area is square with a dimension of 100-500 nm.

9. The monitoring device for DOE integrity monitoring as claimed in claim 7, wherein the inactive region has:

and the metal mark serves as a para mark of the DOE unit.