CN110690869A - Chip packaging method and chip packaging structure - Google Patents
Chip packaging method and chip packaging structure Download PDFInfo
- Publication number
- CN110690869A CN110690869A CN201910967685.XA CN201910967685A CN110690869A CN 110690869 A CN110690869 A CN 110690869A CN 201910967685 A CN201910967685 A CN 201910967685A CN 110690869 A CN110690869 A CN 110690869A
- Authority
- CN
- China
- Prior art keywords
- wafer
- packaging
- chip
- groove
- grooves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 109
- 238000000034 method Methods 0.000 title claims abstract description 80
- 238000005530 etching Methods 0.000 claims abstract description 10
- 235000012431 wafers Nutrition 0.000 claims description 218
- 239000003292 glue Substances 0.000 claims description 28
- 239000011241 protective layer Substances 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 239000010410 layer Substances 0.000 claims description 9
- 238000005520 cutting process Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 238000010897 surface acoustic wave method Methods 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 5
- 238000001746 injection moulding Methods 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 abstract description 3
- 238000012858 packaging process Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
- H03H3/10—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
- H03H3/04—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks for obtaining desired frequency or temperature coefficient
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
- H03H3/04—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks for obtaining desired frequency or temperature coefficient
- H03H2003/0414—Resonance frequency
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Acoustics & Sound (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
According to the chip packaging method and the chip packaging structure, wiring or a connecting terminal does not need to be arranged on the second wafer, wiring complexity is reduced, the second wafer for packaging does not need to adopt a single crystal or a high-impedance wafer, and cost of the chip packaging method is greatly reduced. And the second wafer has good strength and hardness as a packaging wafer, and can adapt to high injection molding pressure, so that the finally obtained chip packaging structure has very high reliability. In addition, the chip packaging method does not need a TSV (through silicon via) process, a complex photoetching and etching process and a complex routing design. Furthermore, the first wafer and the second wafer are bonded through the photoresist, so that the method is suitable for various bonding interfaces and various materials, and is suitable for preparing various surface acoustic wave and bulk acoustic wave filter chips.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and more particularly, to a chip packaging method and a chip packaging structure.
Background
The Filter chip is widely applied to various wireless cellular terminals (such as mobile phones, smart watches, internet of things terminals, smart cars and the like).
The filter chip is designed by using the Surface Acoustic Wave (SAW) or Bulk Acoustic Wave (BAW) principle, so that a cavity without any medium contact is formed on one side of a resonant circuit during packaging, the Acoustic Wave is prevented from being conducted and dissipated, and the Acoustic Wave is ensured to resonate according to a designed mode to obtain the required frequency output.
For the process of packaging the filter chip, a Wafer Level Package (WLP) process is generally adopted, and the WLP process is roughly divided into a wafer bonding packaging process and a thin film packaging process, but in the prior art, both the wafer bonding packaging process and the thin film packaging process have problems such as complex packaging process or high cost.
Disclosure of Invention
In order to solve the above technical problems, the present application provides a chip packaging method and a chip packaging structure, so as to solve the problem of complicated packaging process or high cost in the prior art.
In order to achieve the technical purpose, the embodiment of the application provides the following technical scheme:
a chip packaging method, comprising:
providing a first wafer and a second wafer, wherein the surface of the first wafer is provided with a plurality of chip units, and each chip unit is provided with a packaging area and a preset circuit structure;
forming a plurality of first grooves on the second wafer, wherein the area surrounded by one first groove corresponds to one chip unit;
coating bonding glue in each first groove, wherein the coating area of the bonding glue corresponds to the packaging area;
bonding the surface of one side, provided with the chip units, of the first wafer with the second wafer by using the bonding glue, thinning the second wafer until the first groove is exposed, so that the second wafer becomes a plurality of packaging wafers, and each packaging wafer corresponds to one chip unit;
and performing subsequent processes on the first wafer to form a single chip packaging structure.
Optionally, before forming the plurality of first grooves on the second wafer, the method further includes:
forming a plurality of second grooves on the second wafer, wherein the forming areas of the second grooves correspond to the areas where the preset circuit structures of the chip units are located;
the depth of the second groove is smaller than the depth of the first groove.
Optionally, the cross-sectional shape of the second groove is rectangular or arc.
Optionally, the forming a plurality of second grooves on the second wafer includes:
a plurality of second grooves and at least one support structure located in the second grooves are formed on the second wafer.
Optionally, bonding the surface of the first wafer with the chip unit with the second wafer by using the bonding adhesive, and thinning the second wafer until the first groove is exposed further includes:
and forming a protective layer covering the exposed surface of the second wafer and the exposed surface of the bonding glue.
Optionally, the protective layer is a silicon dioxide layer, a silicon nitride layer, or an amorphous aluminum nitride layer.
Optionally, the cross-sectional shape of the first groove is rectangular or arc.
Optionally, the performing a subsequent process on the first wafer to form a single chip package structure includes:
forming connecting terminals electrically connected with the preset circuit structure on the surface of the first wafer and on two sides of the packaging wafer;
and cutting or etching the first wafer to separate the plurality of chip units from each other so as to obtain a single chip packaging structure.
A chip package structure, comprising:
the wafer packaging structure comprises a first wafer and a packaging wafer which are arranged oppositely, wherein one side of the first wafer, facing the packaging wafer, is provided with a preset circuit structure and a packaging area;
the bonding glue covers the packaging area and is used for bonding the first wafer and the packaging wafer;
and the connecting terminals are positioned on the surface of the first wafer and on two sides of the packaging wafer and are electrically connected with the preset circuit structure.
Optionally, the package wafer further includes a second groove disposed toward the first wafer.
Optionally, the package wafer further includes at least one support structure located in the second groove.
Optionally, when the connection terminal is a solder ball, a side wall of the package wafer facing the solder ball is an arc-shaped side wall.
Optionally, the method further includes:
and the protective layer covers the exposed surface of the second wafer and the exposed surface of the bonding glue.
It can be seen from the foregoing technical solutions that the embodiments of the present application provide a chip packaging method and a chip packaging structure, wherein, the chip packaging method firstly forms a plurality of first grooves on a second wafer, then after the first wafer and the second wafer are bonded, the first grooves are exposed by thinning the second wafer, therefore, the second wafer becomes a packaging wafer of a plurality of chip units, the area for executing subsequent processes on the first wafer is exposed, and finally the subsequent processes are executed in the area of the first wafer which is not covered by the packaging wafer to form a single chip packaging structure. And the second wafer has good strength and hardness as a packaging wafer, and can adapt to high injection molding pressure, so that the finally obtained chip packaging structure has very high reliability.
In addition, the chip packaging method does not need a TSV (through Silicon vias) process, and does not need a complex photoetching and etching process and a complex routing design.
Furthermore, the first wafer and the second wafer are bonded through the photoresist, so that the method is suitable for various bonding interfaces and various materials, and is suitable for preparing various surface acoustic wave and bulk acoustic wave filter chips.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic flowchart of a chip packaging method according to an embodiment of the present application;
fig. 2-9 are schematic diagrams illustrating a manufacturing process of a chip packaging method according to an embodiment of the present application;
fig. 10 is a schematic flow chart illustrating a chip packaging method according to another embodiment of the present application;
fig. 11 is a schematic cross-sectional view of a second wafer having a second groove according to an embodiment of the present disclosure;
fig. 12 is a schematic cross-sectional view illustrating a chip package structure according to an embodiment of the present application;
fig. 13 is a schematic cross-sectional view illustrating a chip package structure according to another embodiment of the present application;
fig. 14 is a schematic cross-sectional view illustrating a chip package structure according to another embodiment of the present application;
fig. 15 is a schematic cross-sectional view illustrating a chip package structure according to still another embodiment of the present application;
fig. 16 is a schematic cross-sectional view illustrating a second wafer having a first groove according to another embodiment of the present disclosure;
fig. 17 is a schematic cross-sectional view illustrating a chip package structure according to an alternative embodiment of the present application;
fig. 18 is a flowchart illustrating a chip packaging method according to another embodiment of the present application;
fig. 19 is a schematic cross-sectional view of a chip package structure according to another alternative embodiment of the present application.
Detailed Description
As described in the background art, in various wafer bonding packaging processes in the prior art, since structures such as traces or connection terminals need to be designed on a sub-wafer for packaging, the sub-wafer must be a single crystal or a high-impedance wafer to meet Radio Frequency (RF) requirements, and the single crystal or the high-impedance wafer has a high cost. And the routing or connection terminal designed on the sub-wafer needs to be electrically connected with the circuit structure in the main wafer through a complicated routing design or a tsv (through Silicon vias) process, so that the preparation process is complicated.
For various thin film bonding packaging processes in the prior art, the packaging structure needs to be designed with structures such as wiring or connecting terminals, and the electrical connection with the circuit structure in the main wafer is realized through complex wiring design or TSV (through silicon via) process, so that the problem of complex preparation process exists, besides, the packaging structure is mostly formed by thin film materials, and the strength and the hardness are poor.
In view of this, an embodiment of the present application provides a chip packaging method, including:
providing a first wafer and a second wafer, wherein the surface of the first wafer is provided with a plurality of chip units, and each chip unit is provided with a packaging area and a preset circuit structure;
forming a plurality of first grooves on the second wafer, wherein the area surrounded by one first groove corresponds to one chip unit;
coating bonding glue in each first groove, wherein the coating area of the bonding glue corresponds to the packaging area;
bonding the surface of one side, provided with the chip units, of the first wafer with the second wafer by using the bonding glue, thinning the second wafer until the first groove is exposed, so that the second wafer becomes a plurality of packaging wafers, and each packaging wafer corresponds to one chip unit;
and performing subsequent processes on the first wafer to form a single chip packaging structure.
According to the chip packaging method, a plurality of first grooves are formed on a second wafer, then the first grooves are exposed in a mode of thinning the second wafer after the first wafer and the second wafer are bonded, so that the second wafer becomes a packaging wafer with a plurality of chip units, an area for executing subsequent processes on the first wafer is exposed, and finally the subsequent processes are executed in the area, not covered by the packaging wafer, of the first wafer to form a single chip packaging structure. And the second wafer has good strength and hardness as a packaging wafer, and can adapt to high injection molding pressure, so that the finally obtained chip packaging structure has very high reliability.
In addition, the chip packaging method does not need a TSV (through Silicon vias) process, and does not need a complex photoetching and etching process and a complex routing design.
Furthermore, the first wafer and the second wafer are bonded through the photoresist, so that the method is suitable for various bonding interfaces and various materials, and is suitable for preparing various surface acoustic wave and bulk acoustic wave filter chips.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
An embodiment of the present application provides a chip packaging method, as shown in fig. 1, including:
s101: providing a first wafer and a second wafer, wherein the surface of the first wafer is provided with a plurality of chip units, and each chip unit is provided with a packaging area and a preset circuit structure;
referring to fig. 2, fig. 3 and fig. 4, fig. 2 is a schematic cross-sectional structure of the first wafer, fig. 3 is a schematic top-view structure of a chip unit in the first wafer, and fig. 4 is a schematic cross-sectional structure of the second wafer. In fig. 2 to 4, reference numeral 10 denotes the first wafer, 11 denotes the predetermined circuit structure, 12 denotes the package region, and 20 denotes the second wafer.
Optionally, for the filter chip, the preset circuit structure is a resonant circuit structure.
S102: forming a plurality of first grooves on the second wafer, wherein the area surrounded by one first groove corresponds to one chip unit;
referring to fig. 5, fig. 5 is a schematic cross-sectional structure diagram of the second wafer after step S102. The first groove is used for cutting the second wafer in the subsequent second wafer thinning process and exposes the area, used for executing the subsequent process, of the first wafer, so that when the bottom surface of the first groove is a plane, the depth of the first groove is the thickness of the thinned packaging wafer; when the bottom surface of the first groove is an arc surface, the cut-off position of the thinning in step S102 may be the maximum diameter of the first groove, but it is ensured that the cut-off position of the thinning process does not expose the second groove. In fig. 5, 21 denotes the first groove.
Optionally, the depth of the first groove is in a range of 30 to 60 μm, the width of the first groove is in a range of 100 and 200 μm, and the specific values and ranges of the depth and the thickness of the first groove are determined according to the type of the finally obtained chip package structure, which is not limited in this application and is determined according to the actual situation.
S103: coating bonding glue in each first groove, wherein the coating area of the bonding glue corresponds to the packaging area;
referring to fig. 6, fig. 6 is a schematic view of the second wafer and its surface structure after step S103. Optionally, the bonding glue is a photosensitive bonding glue. In fig. 6, 22 denotes the bonding paste.
S104: bonding the surface of one side, provided with the chip units, of the first wafer with the second wafer by using the bonding glue, thinning the second wafer until the first groove is exposed, so that the second wafer becomes a plurality of packaging wafers, and each packaging wafer corresponds to one chip unit;
referring to fig. 7 and 8, fig. 7 is a schematic cross-sectional structure diagram of the bonded first wafer and second wafer, and fig. 8 is a schematic structure diagram after thinning. In fig. 8, when the bottom surface of the first groove is a plane, in the process of thinning the second wafer, the bottom of the first groove is used as a limitation, and when the first groove is exposed, the thinning process is stopped, at this time, due to the existence of the first groove, the second wafer is divided into a plurality of packaged wafers, and the thickness of each packaged wafer is the same as that of the first groove. Due to the existence of the first groove, after the thinning process, the corresponding area of the first wafer and the first groove is exposed, and the subsequent process can be executed without routing design or connection terminal arrangement on the packaging wafer. In fig. 8, 30 denotes the package wafer.
Certainly, when the bottom surface of first recess is the arc or the section shape of first recess is the circular arc, it is right in the second wafer carries out the attenuate process, can with the maximum diameter department of first recess is the restriction, stops when the maximum diameter department of attenuate position arrival first recess, nevertheless need guarantee that the attenuate process can not expose the second recess when stopping.
Optionally, before the bonding glue is used to bond the surface of the first wafer having the chip unit with the second wafer, the surfaces of the first wafer and the second wafer may be generally pretreated to ensure the bonding effect, and the pretreatment includes cleaning, micro-etching, cleaning, and processing the bonding interface.
S105: and performing subsequent processes on the first wafer to form a single chip packaging structure.
Optionally, the performing of the subsequent process on the first wafer may include:
s1051: forming connecting terminals electrically connected with the preset circuit structure on the surface of the first wafer and on two sides of the packaging wafer;
optionally, the connection terminal may be a solder ball or a metal bump.
S1052: and cutting or etching the first wafer to separate the plurality of chip units from each other so as to obtain a single chip packaging structure.
In step S1052, when the package region is rectangular, the plurality of chip units on the first wafer may be separated from each other by a dicing process or an etching process; when the packaging area is a complex polygon or has an arc shape, the first wafer is preferably processed by an etching process so as to separate the plurality of chip units from each other.
Referring to fig. 9, fig. 9 is a schematic cross-sectional structure view of a possible single chip package structure according to an embodiment of the present disclosure, in fig. 9, a groove for forming a cavity is not disposed on the second wafer, and the purpose of forming a cavity on the first wafer and the second wafer is achieved by matching the second wafer with the bonding glue. In fig. 9, reference numeral 40 denotes a metal bump.
Of course, referring to fig. 10, before forming the plurality of first grooves on the second wafer, the method further includes:
s106: forming a plurality of second grooves on the second wafer, wherein the forming areas of the second grooves correspond to the areas where the preset circuit structures of the chip units are located;
the depth of the second groove is smaller than the depth of the first groove.
In this embodiment, the depth of the second groove is smaller than the depth of the first groove, so as to ensure that the second groove is not exposed during the thinning process, and ensure that the package wafer and the first wafer can form a cavity.
Referring to fig. 11 and 12, fig. 11 is a schematic cross-sectional structure of the second wafer shown in fig. 4 after step S106, and fig. 12 is a schematic cross-sectional structure of a single chip package structure prepared from the second wafer shown in fig. 11 after steps S102-S105. In fig. 11, reference numeral 23 denotes the second groove.
When the second wafer is formed with the second grooves for forming the cavities, the thickness of the bonding paste applied in step S103 may be greatly reduced, and may be, for example, 10 to 20 μm or the like.
In fig. 11 and 12, the cross-sectional shape of the second groove is rectangular. In some embodiments of the present application, as shown in fig. 13, the cross-sectional shape of the second groove may also be an arc, and after the second groove with the arc cross-sectional shape is matched with the first wafer to form a cavity, the arc top of the cavity may resist a larger pressure, which is beneficial to improving the reliability of the obtained chip package structure. Of course, the cross-sectional shape of the second groove is not limited to a rectangle or an arc, and in other embodiments of the present application, the cross-sectional shape of the second groove may also be a rectangular rounded arc as shown in fig. 14, which is not limited in this application, as the case may be.
Referring to fig. 15, the forming a plurality of second grooves on the second wafer includes: forming a plurality of second grooves on the second wafer and at least one support structure in the second grooves for ensuring structural strength and stability of the cavity. The structure shown in fig. 15 is used in many cases when the required cavity volume is large when the number of the predetermined circuit structures is plural. Reference numeral 24 in fig. 15 denotes the support structure.
Referring to fig. 16 and 17, when the connection terminals are solder balls, the cross-sectional shape of the first groove is arc-shaped to improve the matching degree between the solder balls and the first groove, fig. 16 is a schematic cross-sectional structure diagram of the second wafer after the first groove is formed, and fig. 17 is a schematic cross-sectional structure diagram of a chip package structure prepared from the second wafer shown in fig. 16. In fig. 16 and 17, reference numeral 21 denotes the first groove, and reference numeral 41 denotes the solder ball. Referring to fig. 9, when the connection terminal is a metal bump, the first groove may have a rectangular cross-sectional shape.
On the basis of the above embodiments, in an optional embodiment of the present application, as shown in fig. 18, the chip packaging method includes:
s201: providing a first wafer and a second wafer, wherein the surface of the first wafer is provided with a plurality of chip units, and each chip unit is provided with a packaging area and a preset circuit structure;
s202: forming a plurality of second grooves on the second wafer, wherein the forming areas of the second grooves correspond to the areas where the preset circuit structures of the chip units are located;
the depth of the second groove is smaller than that of the first groove;
s203: forming a plurality of first grooves on the second wafer, wherein the area surrounded by one first groove corresponds to one chip unit;
s204: coating bonding glue in each first groove, wherein the coating area of the bonding glue corresponds to the packaging area;
s205: bonding the surface of one side, provided with the chip units, of the first wafer with the second wafer by using the bonding glue, thinning the second wafer until the first groove is exposed, so that the second wafer becomes a plurality of packaging wafers, and each packaging wafer corresponds to one chip unit;
s206: forming a protective layer covering the exposed surface of the second wafer and the exposed surface of the bonding glue;
s207: and performing subsequent processes on the first wafer to form a single chip packaging structure.
In this embodiment, step S206 is added, that is, after the thinning process is completed, a protective layer is formed as shown in fig. 19, and the protective layer may be a silicon dioxide layer or a silicon nitride layer or an amorphous aluminum nitride layer. In fig. 19, reference numeral 50 denotes the protective layer.
The protective layer can further increase the reliability of the prepared chip packaging structure.
The chip package structure provided by the embodiments of the present application is described below, and the chip package structure described below may be referred to in correspondence with the chip package method described above.
Correspondingly, an embodiment of the present application further provides a chip package structure, as shown in fig. 9, the chip package structure includes:
the wafer structure comprises a first wafer 10 and a packaging wafer 30 which are arranged oppositely, wherein one side of the first wafer 10, which faces the packaging wafer 30, is provided with a preset circuit structure and a packaging area;
a bonding glue 22 covering the packaging area and used for bonding the first wafer 10 and the packaging wafer 30;
and the connecting terminals are positioned on the surface of the first wafer 10 and on both sides of the packaging wafer 30 and are electrically connected with the preset circuit structure. In fig. 9, a metal bump 40 serves as the connection terminal.
Optionally, referring to fig. 11-14, the package wafer 30 further includes a second recess 23 disposed toward the first wafer 10.
Optionally, referring to fig. 15, the package wafer 30 further includes at least one support structure 24 located in the second recess.
Alternatively, referring to fig. 17, when the connection terminal is a solder ball, a side wall of the package wafer 30 facing the solder ball is an arc-shaped side wall.
Optionally, referring to fig. 19, the chip package structure further includes: and a protective layer 50 covering the exposed surface of the second wafer and the exposed surface of the bonding glue 22.
In summary, the embodiments of the present application provide a chip packaging method and a chip packaging structure, wherein the chip packaging method first forms a plurality of first grooves on a second wafer, then after the first wafer and the second wafer are bonded, the first groove is exposed in a mode of thinning the second wafer, therefore, the second wafer becomes a packaging wafer of a plurality of chip units, the area for executing subsequent processes on the first wafer is exposed, and finally the subsequent processes are executed in the area of the first wafer which is not covered by the packaging wafer to form a single chip packaging structure. And the second wafer has good strength and hardness as a packaging wafer, and can adapt to high injection molding pressure, so that the finally obtained chip packaging structure has very high reliability.
In addition, the chip packaging method does not need a TSV (through Silicon vias) process, and does not need a complex photoetching and etching process and a complex routing design.
Furthermore, the first wafer and the second wafer are bonded through the photoresist, so that the method is suitable for various bonding interfaces and various materials, and is suitable for preparing various surface acoustic wave and bulk acoustic wave filter chips.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (13)
1. A method of chip packaging, comprising:
providing a first wafer and a second wafer, wherein the surface of the first wafer is provided with a plurality of chip units, and each chip unit is provided with a packaging area and a preset circuit structure;
forming a plurality of first grooves on the second wafer, wherein the area surrounded by one first groove corresponds to one chip unit;
coating bonding glue in each first groove, wherein the coating area of the bonding glue corresponds to the packaging area;
bonding the surface of one side, provided with the chip units, of the first wafer with the second wafer by using the bonding glue, thinning the second wafer until the first groove is exposed, so that the second wafer becomes a plurality of packaging wafers, and each packaging wafer corresponds to one chip unit;
and performing subsequent processes on the first wafer to form a single chip packaging structure.
2. The method of claim 1, wherein prior to forming the first plurality of grooves on the second wafer, further comprising:
forming a plurality of second grooves on the second wafer, wherein the forming areas of the second grooves correspond to the areas where the preset circuit structures of the chip units are located;
the depth of the second groove is smaller than the depth of the first groove.
3. The method of claim 2, wherein the cross-sectional shape of the second groove is rectangular or arcuate.
4. The method of claim 2, wherein the forming a plurality of second grooves on the second wafer comprises:
a plurality of second grooves and at least one support structure located in the second grooves are formed on the second wafer.
5. The method of claim 1, wherein bonding the surface of the first wafer having the chip units with the second wafer by using the bonding paste, and thinning the second wafer until the first groove is exposed further comprises:
and forming a protective layer covering the exposed surface of the second wafer and the exposed surface of the bonding glue.
6. The method of claim 5, wherein the protective layer is a silicon dioxide layer, a silicon nitride layer, or an amorphous aluminum nitride layer.
7. The method of claim 1, wherein the first groove has a cross-sectional shape that is rectangular or arcuate.
8. The method of claim 1, wherein the performing the subsequent process on the first wafer to form a single chip package structure comprises:
forming connecting terminals electrically connected with the preset circuit structure on the surface of the first wafer and on two sides of the packaging wafer;
and cutting or etching the first wafer to separate the plurality of chip units from each other so as to obtain a single chip packaging structure.
9. A chip package structure, comprising:
the wafer packaging structure comprises a first wafer and a packaging wafer which are arranged oppositely, wherein one side of the first wafer, facing the packaging wafer, is provided with a preset circuit structure and a packaging area;
the bonding glue covers the packaging area and is used for bonding the first wafer and the packaging wafer;
and the connecting terminals are positioned on the surface of the first wafer and on two sides of the packaging wafer and are electrically connected with the preset circuit structure.
10. The chip package structure of claim 9, wherein the package wafer further comprises a second groove disposed toward the first wafer.
11. The chip package structure of claim 10, wherein the package wafer further comprises at least one support structure located in the second recess.
12. The chip package structure according to claim 9, wherein when the connection terminals are solder balls, the side walls of the package wafer facing the solder balls are arc-shaped side walls.
13. The chip package structure according to claim 9, further comprising:
and the protective layer covers the exposed surface of the second wafer and the exposed surface of the bonding glue.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910967685.XA CN110690869A (en) | 2019-10-12 | 2019-10-12 | Chip packaging method and chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910967685.XA CN110690869A (en) | 2019-10-12 | 2019-10-12 | Chip packaging method and chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110690869A true CN110690869A (en) | 2020-01-14 |
Family
ID=69112301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910967685.XA Withdrawn CN110690869A (en) | 2019-10-12 | 2019-10-12 | Chip packaging method and chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110690869A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112652545A (en) * | 2020-12-22 | 2021-04-13 | 北京航天微电科技有限公司 | Packaging method and packaging device for surface acoustic wave filter |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060290238A1 (en) * | 2005-06-22 | 2006-12-28 | Alps Electric Co., Ltd. | Electronic part having high sealing performance and method of manufacturing the same |
| CN105742255A (en) * | 2016-04-01 | 2016-07-06 | 江苏长电科技股份有限公司 | Metal-wafer-level groove buried hole type surface sound filtering chip packaging structure and method |
| CN105897210A (en) * | 2016-04-01 | 2016-08-24 | 江苏长电科技股份有限公司 | Grooved surface acoustic filter chip packaging structure and manufacturing method thereof |
| CN106876289A (en) * | 2017-03-09 | 2017-06-20 | 华进半导体封装先导技术研发中心有限公司 | A kind of chip and its method for packing |
-
2019
- 2019-10-12 CN CN201910967685.XA patent/CN110690869A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060290238A1 (en) * | 2005-06-22 | 2006-12-28 | Alps Electric Co., Ltd. | Electronic part having high sealing performance and method of manufacturing the same |
| CN105742255A (en) * | 2016-04-01 | 2016-07-06 | 江苏长电科技股份有限公司 | Metal-wafer-level groove buried hole type surface sound filtering chip packaging structure and method |
| CN105897210A (en) * | 2016-04-01 | 2016-08-24 | 江苏长电科技股份有限公司 | Grooved surface acoustic filter chip packaging structure and manufacturing method thereof |
| CN106876289A (en) * | 2017-03-09 | 2017-06-20 | 华进半导体封装先导技术研发中心有限公司 | A kind of chip and its method for packing |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112652545A (en) * | 2020-12-22 | 2021-04-13 | 北京航天微电科技有限公司 | Packaging method and packaging device for surface acoustic wave filter |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100594229B1 (en) | Semiconductor package including a chip or plural chips and method for manufacturing the semiconductor package | |
| JP3408987B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| JP4633971B2 (en) | Semiconductor device | |
| TWI611535B (en) | Semiconductor device | |
| EP1757556A2 (en) | Packaging a semiconductor device | |
| US10163808B2 (en) | Module with embedded side shield structures and method of fabricating the same | |
| JPH11354714A (en) | Multi-chip package | |
| US20060290238A1 (en) | Electronic part having high sealing performance and method of manufacturing the same | |
| JP2006197554A (en) | Surface acoustic wave device and method of manufacturing the same, ic card, and mobile electronic equipment | |
| US10985120B1 (en) | Chip packaging method and chip packaging structure | |
| US20060286718A1 (en) | Manufacturing method capable of simultaneously sealing a plurality of electronic parts | |
| JP7284683B2 (en) | Bulk acoustic wave components and wireless communication devices | |
| KR20170108383A (en) | Element package and manufacturing method for the same | |
| CN113675102A (en) | Method for chip packaging and chip particles | |
| CN110690869A (en) | Chip packaging method and chip packaging structure | |
| JP2005057577A (en) | Surface acoustic wave device | |
| JP4760357B2 (en) | Electronic component package | |
| CN116760385A (en) | Packaging substrate embedded with chip, module, electronic product and preparation method | |
| CN111245385A (en) | Chip packaging module, packaging method and electronic device with module | |
| CN110676372B (en) | Chip packaging method and chip packaging structure | |
| JP2009165102A (en) | Piezoelectric oscillator, and method for manufacturing piezoelectric oscillator | |
| CN112366184A (en) | Fan-out packaging structure of filter and packaging method thereof | |
| JP2008147368A (en) | Semiconductor device | |
| CN216120296U (en) | Fan-out type packaging structure and radio frequency module | |
| JP2001127244A (en) | Multichip semiconductor device and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20200114 |
|
| WW01 | Invention patent application withdrawn after publication |