CN110690268A - GCT chip structure and preparation method thereof - Google Patents
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Abstract
The invention belongs to the field of power semiconductor devices, and discloses a GCT chip structure and a preparation method thereof. The invention ensures that the occurrence of dynamic avalanche effect is reduced in the process of high-current turn-off so as to provide the high-current turn-off capability.
Description
Technical Field
The invention belongs to the field of power semiconductor devices, and particularly relates to a GCT chip structure and a preparation method thereof.
Background
The IGCT device is a new generation of current control device developed on the basis of GTO, and from the aspect of a chip, the GCT chip adopts a transparent anode technology and a buffer layer design, so that the trigger current level and the conduction voltage drop of the device are reduced. From the view of a gate driving circuit and an on-off mechanism, the IGCT adopts an integrated driving circuit mode, reduces stray parameters of a current conversion loop to a nano-Henry magnitude by optimizing a circuit layout, a tube shell packaging structure and the like, enables current to be completely converted to a gate from a cathode in a short time in the device turn-off process, and then enables the PNP triode to be naturally turned off.
Referring to fig. 1, fig. 1 is a schematic diagram of a conventional GCT chip structure. As shown in fig. 1, during the static blocking and dynamic turn-off process of the conventional GCT chip, the J2 junction shown in fig. 1 bears the voltage above kV between the anode and the cathode, and it is particularly noted that, in order to ensure the high voltage endurance, the n-type drift region is usually fabricated by using the original silicon single crystal as a low doping concentration region, and at this time, the voltage mainly drops in the n-type drift region in the figure. And according to the poisson equation, the change rate of the electric field is in direct proportion to the doping concentration, namely, the lower doping concentration means that a reasonably designed structure can bear higher blocking voltage.
However, during the turn-off process of the anode with large current, the J2 junction is continuously swept out of the hole-electron pair, and the equivalent n drift region doping becomes larger in the dynamic process due to the moving charge corresponding to the current, so that the breakdown voltage under the dynamic turn-off condition is reduced, that is, the "dynamic avalanche effect" occurs. The dynamic avalanche effect may further induce local current convergence or thermal breakdown effect, resulting in failure of the whole chip.
Therefore, it is urgently needed to develop a GCT chip structure and a preparation method thereof, which overcome the above defects.
Disclosure of Invention
In view of the above problems, the present invention provides a GCT chip structure for solving the above technical problems, wherein the GCT chip structure includes a P + emitter for leading out an anode, an n + buffer layer attached to the P + emitter, a P-type drift region attached to the n + buffer layer, and an n + emitter, and a voltage difference between the anode and the cathode is borne by the P-type drift region in a dynamic and static process.
The GCT chip structure further includes a P + region, the P + region is attached to the P-type drift region, and the P + region is connected to the n + emitter.
The GCT chip structure further comprises a P base region, wherein the P base region is attached to the P type drift region and is located between the P + region and the P type drift region.
In the above GCT chip structure, the P + region leads out a gate, the n + emitter leads out a cathode, a J3 junction is formed at a junction between the n + emitter and the P + region, a J2 junction is formed at a junction between the P-type drift region and the n + buffer layer, and a J1 junction is formed at a junction between the P + emitter and the n + buffer layer.
In the above GCT chip structure, the doping concentration of the P-type drift region is 3 × 1012/cm3-4×1013/cm3。
In the GCT chip structure, the thickness of the P-type drift region ranges from 300 μm to 700 μm.
In the GCT chip structure, the P-type drift region is made of a P-type silicon wafer.
In the above GCT chip structure, the surface doping concentration of the n + buffer layer is 1 × 1014/cm3-4×1016/cm3And the doping depth of the n + buffer layer is 60 mu m.
The invention also provides a preparation method of the GCT chip structure, which comprises the following steps:
step S10: a P-substrate with a specific resistivity and thickness is selected.
Step S11: diffusing or depositing and diffusing the implanted ions on the cathode surface of the P-substrate to form a P + region, a P base region and a P-type drift region;
step S12: forming an n + buffer layer on the anode surface of the P-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S13: forming a thin-layer high-concentration n-type doped region on the cathode surface by using an ion implantation or deposition mode;
step S14: forming a groove shape on the cathode surface of the P-substrate by a dry method or a wet method, and then pushing by thermal diffusion to form an n + emitter;
step S15: diffusing or depositing and diffusing after ion implantation on the n + buffer layer to form a p + emitter;
step S16: and forming two-side metal electrode contact and patterning, wherein the metal electrode on the surface of the cathode is higher than the metal electrode on the surface of the gate.
The preparation method described above, wherein step S10 includes:
step S101: estimating the lowest selectable resistivity;
step S102: obtaining a minimum thickness of the P-substrate according to the lowest selectable resistivity;
step S103: and selecting a P-type silicon wafer with the lowest optional resistivity and the minimum thickness as the P-substrate.
Aiming at the prior art, the invention has the following effects: the method ensures that the occurrence of dynamic avalanche effect is reduced in the process of high-current turn-off so as to provide high-current turn-off capability.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional GCT chip structure;
FIG. 2 is a diagram of a GCT chip structure according to a first embodiment of the present invention;
FIG. 3 is a diagram of a GCT chip structure according to a second embodiment of the present invention;
FIG. 4 is a flow chart of a production method of the present invention;
FIG. 5 is a flow chart of the substeps of FIG. 4;
FIG. 6 is a diagram illustrating the distribution of electric field strength of a prior art GCT chip with an n-type drift region;
FIG. 7 is a schematic diagram of the electric field intensity distribution of FIG. 6 during the dynamic voltage establishment process;
FIG. 8 is a schematic diagram of the distribution of electric field strength of a GCT chip with a P-type drift region according to the present invention;
FIG. 9 is a schematic diagram of the electric field intensity distribution in the first state during the dynamic voltage establishment process of FIG. 8;
FIG. 10 is a diagram illustrating the electric field intensity distribution of the second state in the dynamic voltage setup process of FIG. 8.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
With respect to directional terminology used herein, for example: up, down, left, right, front or rear, etc., are simply directions with reference to the drawings. Accordingly, the directional terminology used is intended to be illustrative and is not intended to be limiting of the present teachings.
As used herein, the terms "comprising," "including," "having," "containing," and the like are open-ended terms that mean including, but not limited to.
The exemplary embodiments of the present invention and the description thereof are provided to explain the present invention and not to limit the present invention. Additionally, the same or similar numbered elements/components used in the drawings and the embodiments are used to represent the same or similar parts.
Referring to fig. 2, fig. 2 is a schematic diagram of a GCT chip structure according to a first embodiment of the present invention. As shown in fig. 2, the GCT chip structure of the present invention includes: the dynamic turn-off circuit comprises a P + emitter for leading out an Anode (Anode), an n + buffer layer attached to the P + emitter, a P-type drift region attached to the n + buffer layer and an n + emitter, wherein the P-type drift region bears the main voltage difference between the Anode and the cathode in the dynamic turn-off process and the static turn-off process.
Wherein the P-type drift region is formed by P-type original silicon single crystal, specifically, the P-type drift region is P-type doped with typical doping concentration of 3 × 1012/cm3-4×1013/cm3The specific values are related to the corresponding static blocking voltage and the current density of the dynamic turn-off. In this embodiment, when the GCT chip is manufactured, the doping of the P-type drift region is not realized by using doping processes such as thermal diffusion and ion implantation, but directly uses a P-type original silicon single crystal with a corresponding resistivity. Since the doping of other regions does not diffuse into the P-type drift region, the corresponding single crystal region, the doping of this portion of the P-type original silicon single crystal is preserved and thus formed as a P-type drift region.
It should be noted that, in this embodiment, in order to improve the operability of the edge grinding process in the device manufacturing process, the depth of the n + buffer layer may be appropriately increased compared to the conventional structure, and it is preferable that the reference range of the depth of the n + buffer layer is between 30 μm and 100 μm, and the electric field is required to be cut off in the n + buffer layer.
In an embodiment of the present invention, when the designed breakdown voltage is 4500V-6500V, the thickness of the corresponding P-type drift region is preferably in the range of 300 μm-700 μm.
Furthermore, the GCT chip structure further comprises a P + region, the P + region is attached to the P-type drift region, the P + region is connected with the n + emitter, a Gate (Gate) is led out of the P + region, and a Cathode (Cathode) is led out of the n + emitter.
The interior of the GCT chip is of a typical asymmetric structure, a PN junction is arranged in the GCT chip, different doping processes are adopted for the PN junction, a P-type semiconductor and an N-type semiconductor are manufactured on the same semiconductor substrate through diffusion, and a space charge region called the PN junction is formed at the interface of the P-type semiconductor and the N-type semiconductor. In order to distinguish the PN junctions, a J3 junction is formed at the junction between the n + emitter and the P + region, a J2 junction is formed at the junction between the P drift region and the n + buffer layer, and a J1 junction is formed at the junction between the P + emitter and the n + buffer layer, but the invention is not limited thereto.
In an embodiment of the invention, the surface doping concentration of the n + buffer layer is 1 × 1014/cm3-4×1016/cm3。
In one embodiment of the present invention, the n + buffer layer has a doping depth of 60 μm and a surface concentration of 1 × 1015/cm3。
It should be noted that the n + buffer layer is formed by diffusion, so it is not uniformly doped, and the surface concentration and junction depth are generally defined to describe the structure, while the P-type drift region is uniformly doped, which is determined by the original silicon wafer, and only needs to define the concentration and thickness.
Referring to fig. 3, fig. 3 is a schematic diagram of a GCT chip structure according to a second embodiment of the present invention. The GCT chip structure shown in fig. 3 is substantially the same as the GCT chip structure shown in fig. 2, and therefore, the same parts are not described herein again, and different parts are described below. In this embodiment, the GCT chip structure further includes a P base region, and the P base region is attached to the P-type drift region and located between the P + region and the P-type drift region.
It should be noted that, based on the GCT chip structure of the present invention, when the doping concentration of the P-type drift region is higher and the designed off-current value is lower, the P-type base region can be omitted, thereby simplifying the GCT chip manufacturing process.
In an embodiment of the present invention, the GCT chip structure may further include an anode emitter short circuit, a buffer wave base region, and the like, which are all stacked on the GCT chip structure shown in fig. 2 and/or fig. 3.
Referring to fig. 4, fig. 4 is a flowchart of a manufacturing method of the present invention, and fig. 5 is a flowchart of sub-steps of fig. 4. As shown in fig. 4 to 5, the preparation method of the present invention comprises the following steps:
step S10: selecting a P-substrate with specific resistivity and thickness;
specifically, in selecting the P-substrate for preparing the P-type drift region, the voltage blocking capability of the device, i.e., the blocking capability of the device without anode current, should be considered first, and in order to ensure sufficient voltage blocking capability, therefore, in the present invention, it is preferable that the device must select a P-type silicon wafer higher than the lowest selectable resistivity and higher than the minimum thickness as the P-substrate.
Step S10 includes:
step S101: estimating the lowest selectable resistivity; wherein the lowest selectable resistivity is estimated in this embodiment according to the following formula:
wherein N isp,driftU is the designed blocking voltage value, epsilon, for the resistivity, i.e. the doping concentration of the P base region (according to the national standard, the doping concentration has a one-to-one correspondence relation with the resistivity, when the silicon wafer parameters are mentioned in the industry, the resistivity is commonly used, but the doping concentration is substantially the same), U is the designed blocking voltage valueSiIs the dielectric constant of silicon;
step S102: obtaining a minimum thickness of the P-substrate according to the lowest selectable resistivity; wherein the minimum thickness of the P-substrate is obtained in this embodiment according to the following formula:
wherein, wp,driftIs the minimum thickness of the P-substrate;
for example, taking the design blocking voltage of 4500V as an example, the maximum doping concentration of the p-type drift region required is 8.7 × 1012cm-3The corresponding lowest selectable resistivity, at which the minimum thickness is 310 μm, is about 480 Ω · m. On the basis, the lowest allowable resistivity and the corresponding appropriate thickness of the P-type silicon wafer should be considered and selected for manufacturing. In general, of thicknessThe choice will require consideration of the effect of the turn-on voltage drop in addition to exceeding the minimum thickness requirement described above to meet the blocking voltage requirement. But since an analytical solution generally does not exist for the optimal thickness value, a simulation tool is required to assist in the design. Taking 4500V blocking voltage as an example, the optimal thickness of the P-type drift region obtained under different carrier lifetime conditions is about 300 μm-450 μm.
Step S103: and selecting a P-type silicon wafer with the resistivity higher than the lowest selectable resistivity and the minimum thickness as the P-substrate.
Step S11: forming a P + region, a P base region and a P type drift region on the cathode surface of the P-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S12: forming an n + buffer layer on the anode surface of the P-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S13: forming a thin-layer high-concentration n-type doped region on the cathode surface by using an ion implantation or deposition mode;
step S14: forming a groove shape on the cathode surface of the P-substrate by a dry method or a wet method, and then pushing by thermal diffusion to form an n + emitter;
step S15: diffusing or depositing and diffusing after ion implantation on the n + buffer layer to form a p + emitter;
step S16: and forming two-side metal electrode contact and patterning, wherein the metal electrode on the surface of the cathode is higher than the metal electrode on the surface of the gate.
Referring to fig. 6-7, fig. 6 is a schematic diagram illustrating electric field intensity distribution of a GCT chip with an n-type drift region according to the prior art; fig. 7 is a schematic diagram of the electric field intensity distribution in the dynamic voltage establishment process of fig. 6.
Specifically, as shown in fig. 6, according to the poisson equation:
wherein N isdriftFor the doping concentration of the corresponding region (n-type drift region is negative, P-base region is positive), it can be seen that the rate of change of the electric field strength is proportional to the doping concentration. However, during dynamic voltage build-up, the electric field is strongThe distribution of the intensity is as shown in fig. 7, the change rate of the electric field intensity in the n-type drift region is increased, because when the anode current exists, the mobile charges corresponding to the anode current are positive charges in the P-base region and the n-type drift region, which can be equivalently n-type doping, and thus the change slope of the whole electric field intensity is increased after equivalence. The increase of the slope increases the electric field intensity at the peak under the same anode voltage condition, thereby enhancing the avalanche effect.
Referring to fig. 8-10, fig. 8 is a schematic diagram illustrating electric field intensity distribution of a GCT chip having a P-type drift region according to the present invention; FIG. 9 is a schematic diagram of the electric field intensity distribution in the first state during the dynamic voltage establishment process of FIG. 8; FIG. 10 is a diagram illustrating the electric field intensity distribution of the second state in the dynamic voltage setup process of FIG. 8.
Specifically, as shown in fig. 8, the distribution of the electric field intensity is different in the P-type drift region structure, and the peak electric field intensity is located at the boundary between the P-type drift region and the n + buffer layer in the no-current condition. However, in the process of establishing the dynamic voltage, the distribution of the electric field strength is as shown in fig. 9-10, when a certain anode current exists in the first state, but the value of the mobile charge corresponding to the anode current is smaller than the doping concentration, in the P-type drift region, the n-type doping equivalent to the mobile charge is not enough to invert the doping type of the P-type drift region, so that the n-type doping is reflected in the distribution of the electric field strength, the peak value of the electric field strength is still at the J2 junction formed by the P-type drift region and the n + buffer layer, but the slope of the electric field change in the P-type drift region is reduced; in the second state, after the anode current is further increased, the amount of the mobile charges exceeds the doping concentration in the P-type drift region, the P-type drift region is inverted into an n-type, and it can be seen that under the same anode current and anode voltage, the electric field change slope of the GCT chip with the P-type drift region structure in the drift region is slower than that of the GCT chip with the n-type drift region structure, so that the peak electric field intensity is effectively relieved, the dynamic avalanche process is inhibited, and the current turn-off capability of the device is improved.
In summary, the GTC chip structure and the design method thereof of the present invention have strong applicability, not only can achieve the conduction voltage drop of the existing GCT chip structure, but also have stronger current turn-off capability, i.e. the avalanche process is not easy to occur under a large current. While also eliminating the higher turn-off losses caused by the delay in the rate of voltage rise during turn-off.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A GCT chip structure is characterized by comprising a P + emitter, an n + buffer layer, a P type drift region and an n + emitter, wherein the P + emitter is led out of an anode, the n + buffer layer is attached to the P + emitter, the P type drift region is attached to the n + buffer layer, and the n + emitter is used for bearing the voltage difference between the anode and the cathode through the P type drift region in the dynamic turn-off process and the static blocking process.
2. The GCT chip structure of claim 1, further comprising a P + region, the P + region being attached to the P-type drift region, the P + region connecting the n + emitter.
3. The GCT chip structure of claim 2, further comprising a P base region attached to the P drift region and located between the P + region and the P drift region.
4. The GCT chip structure of claim 3, wherein the P + region leads out a gate, the n + emitter leads out a cathode, a junction of the n + emitter and the P + region forms a J3 junction, a junction of the P drift region and the n + buffer layer forms a J2 junction, and a junction of the P + emitter and the n + buffer layer forms a J1 junction.
5. The GCT chip structure of any of claims 1-4, wherein the P-type drift regionHas a doping concentration of 3X 1012/cm3-4×1013/cm3。
6. The GCT chip structure of any of claims 1 to 4, wherein the thickness of the P-type drift region is in a range from 300 μm to 700 μm.
7. The GCT chip structure of any one of claims 1 to 4, wherein the P-type drift region is made of a P-type silicon wafer.
8. The GCT chip structure of claim 2, wherein the n + buffer layer has a surface doping concentration of 1 x 1014/cm3-4×1016/cm3And the doping depth of the n + buffer layer is 60 mu m.
9. A preparation method of a GCT chip structure is characterized by comprising the following steps:
step S10: a P-substrate with a specific resistivity and thickness is selected.
Step S11: diffusing or depositing and diffusing the implanted ions on the cathode surface of the P-substrate to form a P + region, a P base region and a P-type drift region;
step S12: forming an n + buffer layer on the anode surface of the P-substrate by utilizing diffusion or deposition diffusion after ion implantation;
step S13: forming a thin-layer high-concentration n-type doped region on the cathode surface by using an ion implantation or deposition mode;
step S14: forming a groove shape on the cathode surface of the P-substrate by a dry method or a wet method, and then pushing by thermal diffusion to form an n + emitter;
step S15: diffusing or depositing and diffusing after ion implantation on the n + buffer layer to form a p + emitter;
step S16: and forming two-side metal electrode contact and patterning, wherein the metal electrode on the surface of the cathode is higher than the metal electrode on the surface of the gate.
10. The method according to claim 9, wherein the step S10 includes:
step S101: estimating the lowest selectable resistivity;
step S102: obtaining a minimum thickness of the P-substrate according to the lowest selectable resistivity;
step S103: and selecting a P-type silicon wafer with the lowest optional resistivity and the minimum thickness as the P-substrate.
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| CN115274626A (en) * | 2022-08-04 | 2022-11-01 | 四川大学 | Anti-irradiation power semiconductor device with isolated voltage division layer |
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