CN110690180A - Circuit board element and manufacturing method thereof - Google Patents
Circuit board element and manufacturing method thereof Download PDFInfo
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- CN110690180A CN110690180A CN201810722770.5A CN201810722770A CN110690180A CN 110690180 A CN110690180 A CN 110690180A CN 201810722770 A CN201810722770 A CN 201810722770A CN 110690180 A CN110690180 A CN 110690180A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 50
- 239000010410 layer Substances 0.000 claims abstract description 386
- 229910000679 solder Inorganic materials 0.000 claims abstract description 167
- 238000000034 method Methods 0.000 claims abstract description 106
- 239000011241 protective layer Substances 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims description 169
- 229920002120 photoresistant polymer Polymers 0.000 claims description 155
- 238000002161 passivation Methods 0.000 claims description 63
- 239000000758 substrate Substances 0.000 claims description 46
- 238000005530 etching Methods 0.000 claims description 13
- 239000012792 core layer Substances 0.000 claims description 9
- 239000000945 filler Substances 0.000 claims description 7
- 239000002131 composite material Substances 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims description 6
- 239000003365 glass fiber Substances 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims 1
- 238000003466 welding Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 2
- 229910002113 barium titanate Inorganic materials 0.000 description 2
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
The invention provides a circuit board element, which comprises an insulating layer, a circuit layer, a protective layer, a plurality of welding balls and a dielectric layer. The circuit layer is located on the insulating layer. The protective layer is located on the circuit layer and is provided with a plurality of openings exposing the circuit layer. The solder balls are arranged on the protective layer and are embedded into the corresponding openings. The dielectric layer is located between the solder ball and the protection layer. A method for manufacturing a circuit board element is also provided.
Description
Technical Field
The present disclosure relates to electronic devices, and particularly to a circuit board device and a method for manufacturing the same.
Background
The circuit board is usually electrically connected to other electronic components through solder balls. However, the solder ball may be detached due to internal stress such as poor soldering, thermal expansion and contraction, or other external stress (so-called ball drop). Therefore, how to reduce the possibility of solder ball detachment on the circuit board has become an issue to be solved.
Disclosure of Invention
The invention provides a circuit board element and a manufacturing method thereof, which have better yield.
The method of manufacturing a circuit-board element according to the invention comprises the following steps. A circuit substrate is provided. The circuit substrate comprises an insulating layer, a circuit layer, a protective layer and a plurality of solder balls. The circuit layer is located on the insulating layer. The protective layer is located on the circuit layer and is provided with a plurality of openings exposing the circuit layer. The solder balls are arranged on the protective layer and embedded into the corresponding openings, and gaps are formed between each solder ball and the protective layer. The circuit substrate is placed on the carrier, and the solder balls are far away from the carrier. At least one trench penetrating the circuit substrate is formed to expose the carrier. A photoresist material layer is formed on the circuit substrate to cover the circuit substrate and fill the gap, and to fill the trench to cover the carrier. And curing the part of the photoresist material layer filled in the gap to form a dielectric layer at least between the solder ball and the protective layer. Removing part of the photoresist material layer filled in the trench to expose the carrier. The carrier is removed.
In an embodiment of the invention, the material of the photoresist material layer includes a photoresist and a filler.
In an embodiment of the invention, a material of the photoresist material layer includes a positive photoresist, and the manufacturing method further includes the following steps. Before forming the dielectric layer, the photoresist material layer is exposed and developed to remove part of the photoresist material layer not filled in the gap and expose the solder ball and part of the protective layer.
In an embodiment of the invention, a material of the photoresist material layer includes a positive photoresist, and the manufacturing method further includes the following steps. Before forming the dielectric layer, the photoresist material layer is exposed and developed to remove part of the photoresist material layer not filled in the gap and expose the solder ball, part of the protective layer and the carrier corresponding to the trench.
In an embodiment of the invention, a material of the photoresist material layer includes a positive photoresist, and the manufacturing method further includes the following steps. Before forming the dielectric layer, the photoresist material layer is exposed and developed by the mask to remove part of the photoresist material layer and expose the solder ball and part of the passivation layer. And curing the photoresist material layer filled in the gap and covering the part of the photoresist material layer on the side wall of the ditch to form the dielectric layer.
In an embodiment of the present invention, the mask has a plurality of slits.
In an embodiment of the invention, a material of the photoresist material layer includes a negative photoresist, and the manufacturing method further includes the following steps. Before forming the dielectric layer, an anisotropic etching process is performed on the photoresist material layer to remove a portion of the photoresist material layer and expose the solder ball and a portion of the passivation layer.
In an embodiment of the invention, a material of the photoresist material layer includes a negative photoresist, and the manufacturing method further includes the following steps. Before forming the dielectric layer, an anisotropic etching process is performed on the photoresist material layer to remove a portion of the photoresist material layer not filled in the gap and expose the solder ball and a portion of the passivation layer. The photoresist material layer is exposed to light through the mask to solidify the part of the photoresist material layer filled in the gap to form the dielectric layer.
In an embodiment of the invention, the exposing process further cures a portion of the photoresist material layer covering the sidewalls of the at least one trench to form the dielectric layer.
In an embodiment of the invention, a material of the photoresist material layer includes a negative photoresist, and the manufacturing method further includes the following steps. Before forming the dielectric layer, an anisotropic etching process is performed on the photoresist material layer to remove a portion of the photoresist material layer not filled in the gap and expose the solder ball and a portion of the passivation layer. An exposure process is performed on the photoresist material layer to cure the portion of the photoresist material layer filled in the gap and the at least one trench. Removing the partially cured photoresist material layer filled in the at least one trench to form a dielectric layer.
In an embodiment of the present invention, the partially cured photoresist material layer filled in the at least one trench is removed by cutting.
The invention provides a circuit board element, which comprises an insulating layer, a circuit layer, a protective layer, a plurality of welding balls and a dielectric layer. The circuit layer is located on the insulating layer. The protective layer is located on the circuit layer and is provided with a plurality of openings exposing the circuit layer. The solder balls are arranged on the protective layer and are embedded into the corresponding openings. The dielectric layer is located between the solder ball and the protection layer.
In an embodiment of the invention, the insulating layer includes a core layer.
In an embodiment of the invention, the material of the core layer is different from the materials of the protective layer and the dielectric layer, and the material of the core layer includes a polymer glass fiber composite substrate, a glass substrate, a ceramic substrate, an insulating silicon substrate, or a polyimide glass fiber composite substrate.
In an embodiment of the invention, a material of the dielectric layer includes a photosensitive dielectric material.
In an embodiment of the invention, the material of the dielectric layer further includes a filler.
In an embodiment of the invention, an orthogonal projection of the dielectric layer on the passivation layer is overlapped in an orthogonal projection of the solder ball on the passivation layer.
In an embodiment of the invention, the edge of the dielectric layer is cut to be flush with the edge of the solder ball.
In an embodiment of the invention, the dielectric layer further covers sidewalls of the insulating layer and sidewalls of the passivation layer.
In an embodiment of the invention, the solder balls include a plurality of first solder balls and a plurality of second solder balls, a size of the first solder balls is larger than a size of the second solder balls, and a size of the dielectric layer between the first solder balls and the passivation layer is larger than a size of the dielectric layer between the second solder balls and the passivation layer.
Based on the above, the present invention forms a dielectric layer between the solder ball and the passivation layer through the photoresist. The dielectric layer between the solder ball and the protective layer can directly contact the arc-shaped bottom surface of the spherical top end of the solder ball so as to support or fix the spherical top end of the solder ball. In other words, the dielectric layer between the solder balls and the passivation layer can also be referred to as a dielectric block surrounding the base of the solder balls to support and protect the solder balls. Therefore, the possibility of solder ball detachment can be reduced, and the yield of the circuit board element can be improved. In addition, even though the solder balls have different sizes, the dielectric layer between the solder balls with different sizes and the protective layer can have different sizes by the manufacturing method of the invention. Therefore, even if the solder balls have different sizes, the solder balls can pass through the corresponding dielectric layers to reduce the possibility of separation, and the electrical connection with other electronic elements cannot be influenced because the dielectric layers between the solder balls with different sizes and the protective layer have the same size or height.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to fig. 1K are schematic cross-sectional views illustrating a method for manufacturing a circuit board element according to a first embodiment of the invention.
Fig. 2A to fig. 2D are schematic cross-sectional views illustrating a part of a method for manufacturing a circuit board element according to a second embodiment of the invention.
Fig. 3A to fig. 3H are schematic cross-sectional views illustrating a part of a method for manufacturing a circuit board element according to a third embodiment of the invention.
Fig. 4A to 4C are schematic cross-sectional views illustrating a part of a method for manufacturing a circuit board element according to a fourth embodiment of the invention.
Fig. 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing a circuit board element according to a fifth embodiment of the invention.
Description of reference numerals:
100. 200, 300, 400, 500: a circuit board element;
110: a circuit substrate;
111: a trench;
120: an insulating layer;
120 a: a first surface;
120 b: a second surface;
120 c: a side wall;
121: a conductive via;
130. 130': a circuit layer;
131. 131': a dielectric layer;
132. 132': a conductive layer;
133: a via hole;
140. 140': a protective layer;
140 a: a surface;
140 b: a side wall;
145: a first opening;
146: a second opening;
150: a first solder ball;
151: a top end;
151 a: a top surface;
151 b: a bottom surface;
151 c: an edge;
152: a bottom end;
153: a first void;
160: a second solder ball;
161: a top end;
161 a: a top surface;
161 b: a bottom surface;
161 c: an edge;
162: a bottom end;
163: a second void;
171. 172, 272, 273', 372, 472, 573': a layer of photoresist material;
173. 273, 373', 473, 573: a dielectric layer;
173c, 373 c: an edge;
10: a carrier;
22. 32, 42: a mask;
22 a: a slit;
r1, R2, R3, R3', R4, R4', R5, R6, R7, R7', R7 ": an area;
l1, L2: light rays.
Detailed Description
Fig. 1A to fig. 1I are schematic cross-sectional views illustrating a method for manufacturing a circuit board element according to a first embodiment of the invention. Fig. 1D may be an enlarged view of region R1 in fig. 1A, 1B, or 1C. Fig. 1F may be an enlarged view of region R2 in fig. 1E. Fig. 1H may be an enlarged view of region R3 in fig. 1G. FIG. 1K may be an enlarged view of region R4 in FIG. 1I or FIG. 1J.
First, the method for manufacturing the circuit board structure of the present embodiment includes the following steps. First, referring to fig. 1A and fig. 1D, a circuit substrate 110 is provided. The circuit substrate 110 includes an insulating layer 120, circuit layers 130, 130', protective layers 140, 140', and a plurality of solder balls, such as a plurality of first solder balls 150 and a plurality of second solder balls 160. The circuit layer 130 is disposed on the first surface 120a of the insulating layer 120, and the circuit layer 130' is disposed on the second surface 120b of the insulating layer 120. The protection layer 140 is disposed on the circuit layer 130, and the protection layer 140 'is disposed on the circuit layer 130'. The circuit layer 130 may include a dielectric layer 131 and a conductive layer 132, and the circuit layer 130' may include a dielectric layer 131' and a conductive layer 132 '. The protection layer 140 has a plurality of openings, such as a plurality of first openings 145 and a plurality of second openings 146, to expose the conductive layer 132 in the circuit layer 130. The first solder balls 150 are disposed on the passivation layer 140 and embedded in the corresponding first openings 145, and a first gap 153 is formed between the first solder balls 150 and the passivation layer 140. The second solder balls 160 are disposed on the passivation layer 140 and embedded in the corresponding second openings 146, and a second gap 163 is formed between the second solder balls 160 and the passivation layer 140.
In the present embodiment, the insulating layer 120 may include a core layer, and the core layer may include a polymer glass fiber composite substrate, a glass substrate, a ceramic substrate, an insulating silicon substrate, a Polyimide (PI) glass fiber composite substrate, or the like, but the present invention is not limited thereto. In other embodiments, the insulating layer 120 may be a dielectric layer having a single layer or multiple layers of dielectric materials.
In the present embodiment, if the insulating layer 120 is a core layer, the insulating layer 120 may form a double-sided circuit board (double-sided wired board) with the circuit layer 130 on the first surface 120a and the circuit layer 130' on the second surface 120 b. In addition, the insulating layer 120 may have a conductive through via (121) penetrating through the first surface 120a and the second surface 120b, so that the circuit layer 130 on the first surface 120a and the circuit layer 130' on the second surface 120b may be electrically connected to each other.
In the present embodiment, the dielectric layers 131 and 131 'of the circuit layers 130 and 130' may be one or more layers, but the invention is not limited thereto. Furthermore, if the dielectric layers 131 and 131' of the circuit layers 130 and 130' are multiple layers, the dielectric layers 131 and 131' may have different or the same material or formation method.
In the present embodiment, the conductive layers 132 and 132 'of the circuit layers 130 and 130' may be one or more layers, but the invention is not limited thereto. In addition, if the conductive layers 132 and 132' of the circuit layers 130 and 130' are multiple layers, the conductive layers 132 and 132' may have different or the same material or formation method. Taking the conductive layer 132 of the circuit layer 130 as an example, the conductive layers 132 having a multi-layer structure may be electrically connected to each other through a conductive via (conductive via)133 between the layers.
In other embodiments, the material of the insulating layer 120 may be the same as or similar to the material of the dielectric layers 131 and 131 'of the circuit layers 130 and 130', that is, the insulating layer 120 may be a common dielectric layer, and thus the circuit substrate 110 may be a coreless (core) circuit board structure.
The protective layers 140, 140' may be Dry Film Solder Mask (DFSM) or Liquid Photosensitive Solder Mask (LPSM). During the formation of the solder balls 150, 160, the passivation layer 140 can reduce the possibility of undesired connection between two adjacent solder balls (e.g., between two solder balls 150, between two solder balls 160, and/or between a solder ball 150 and a solder ball 160).
The protective layer 140 may have one or more sizes of solder balls 150, 160 thereon. For example, in the embodiment, the protection layer 140 has a plurality of first solder balls 150 and a plurality of second solder balls 160 thereon, and the size of the first solder balls 150 is larger than that of the second solder balls 160, but the invention is not limited thereto.
Generally, the solder balls 150, 160 may be formed by cooling to solidify the molten metal solder. Therefore, the portions 151, 161 of the solder balls 150, 160 protruding from the surface 140a of the protective layer 140 may be substantially spherical.
Taking the first solder ball 150 as an example, the first solder ball 150 may include a bottom end 152 and a top end 151 connected to each other. The bottom end 152 is embedded in the corresponding first opening 145, and the shape of the bottom end 152 corresponds to the shape of the first opening 145. The spherical tip 151 protrudes outward from the first opening 145, and the spherical tip 151 has an arc-shaped top surface 151a and an arc-shaped bottom surface 151b connected thereto. The arc-shaped bottom surface 151b faces the protective layer 140 so that a first gap 153 is formed between the spherical tip 151 and the protective layer 140.
Taking the second solder ball 160 as an example, the second solder ball 160 may include a bottom end 162 and a top end 161 connected to each other. The bottom ends 162 are embedded within the corresponding second openings 146, and the shape of the bottom ends 162 corresponds to the shape of the second openings 146. The spherical tip 161 protrudes outward from the second opening 146, and the spherical tip 161 has an arc-shaped top surface 161a and an arc-shaped bottom surface 161b connected thereto. The arc-shaped bottom surface 161b faces the protective layer 140 so that a second gap 163 is formed between the spherical tip 161 and the protective layer 140.
Next, please refer to fig. 1B. In this embodiment, the circuit substrate 110 may be disposed on the carrier 10, and the solder balls 150 and 160 of the circuit substrate 110 are far away from the carrier 10. In some embodiments, the carrier 10 may be a carrier tape (carrier tape), such as a blue tape (blue tape), but the invention is not limited thereto.
Next, please refer to fig. 1C. In this embodiment, a single-processing process (singulation process) may be performed on the circuit substrate 110 (shown in fig. 1B) on the carrier 10 to form a plurality of circuit substrates 110 shown in fig. 1B. The singulation process includes cutting the circuit substrate 110 with a blade, a wheel knife or a laser beam to form at least one trench 111 penetrating through the circuit substrate 110, wherein the trench 111 exposes the carrier 10.
It is noted that similar reference numerals will be used for the elements after singulation process. For example, the circuit substrate 110 (shown in fig. 1B) may be a plurality of circuit substrates 110 (shown in fig. 1C) after being singulated, the insulating layer 120 (shown in fig. 1B) may be a plurality of insulating layers 120 (shown in fig. 1C) after being singulated, the circuit layers 130 and 130 '(shown in fig. 1B) may be a plurality of circuit layers 130 and 130' (shown in fig. 1C) after being singulated, the protective layers 140 and 140 '(shown in fig. 1B) may be a plurality of protective layers 140 and 140' (shown in fig. 1C) after being singulated, the plurality of first solder balls 150 (shown in fig. 1B) may be a plurality of first solder balls 150 (shown in fig. 1C) after being singulated, and the plurality of second solder balls 160 (shown in fig. 1B) may be a plurality of second solder balls 160 (shown in fig. 1C) after being singulated, and the like. Other elements after being singulated will follow the same element notation rules as above, and will not be described further herein.
In addition, the sequence of the singulation process is not limited in the present invention. In other words, in other possible embodiments, a singulation process similar to that shown in fig. 1D may be performed after any suitable subsequent step. Alternatively, in other possible embodiments, the circuit substrates 110 may be directly disposed on the carrier 10 in a manner similar to that shown in fig. 1C, and the circuit substrates 110 are separated from each other to form the trenches 111 therebetween.
Next, referring to fig. 1E and fig. 1F, a photoresist material layer 171, such as a photoresist packaging material (photoresist) is formed on the circuit substrate 110. The photoresist material layer 171 covers the protection layer 140, the ball tops 151 of the first solder balls 150, and the ball tops 161 of the second solder balls 160. In other words, the photoresist material layer 171 directly contacts the surface 140a of the passivation layer 140, the arc-shaped top surface 151a and the arc-shaped bottom surface 151b of the ball tip 151, and the arc-shaped top surface 161a and the arc-shaped bottom surface 161b of the ball tip 161. That is, the photoresist material layer 171 is not only located on the passivation layer 140, the first solder balls 150 and the second solder balls 160, but also fills the first gaps 153 between the passivation layer 140 and the first solder balls 150 and the second gaps 163 between the passivation layer 140 and the second solder balls 160.
In the present embodiment, the material of the photoresist material layer 171 may be positive photoresist (positive photoresist). And in some embodiments, the material of the photoresist material layer 171 may include barium titanate (BaTiO) in addition to the positive photoresist3) Boron Nitride (BN), alumina, silica, strontium titanate, barium strontium titanate, quartz or other suitable filler (filler).
In the present embodiment, if the singulation process shown in fig. 1C is performed before the photoresist material layer 171 is formed, the photoresist material layer 171 may also fill the trench 111.
Next, please refer to fig. 1G and fig. 1H. After forming the photoresist material layer 171 (shown in fig. 1E or fig. 1F) on the wiring substrate 110, an exposure process is performed on the photoresist material layer 171. In general, during the exposure process, the positive photoresist is softened or decomposed by the light L1. In other words, portions of the photoresist material layer 172 may be softened or decomposed by the irradiation of the light L1 perpendicular to the surface 140a of the protection layer 140. Specifically, in the direction perpendicular to the surface 140a of the protection layer 140, the photoresist material layer 171 filled in the first gap 153 and the second gap 163 is shielded by the top end 151 of the first solder ball 150 and the top end 161 of the second solder ball 160, respectively. Therefore, the photoresist material layer 172 on the arc-shaped top surfaces 151a and 161a and the arc-shaped top surfaces 151a and 161a can be softened or decomposed, and the portion of the photoresist material layer 171 filled in the first gap 153 and the second gap 163 is less prone to be softened or decomposed.
Next, please refer to fig. 1I and fig. 1K. After the exposure process, a developing process may be performed to remove the photoresist material layer 172 (shown in fig. 1G or fig. 1H) softened or decomposed by the light L1 (shown in fig. 1G or fig. 1H) outside the first and second gaps 153 and 163, so as to expose the arc-shaped top surfaces 151a and 161a of the first solder balls 150, the arc-shaped top surfaces 151a and 161a of the second solder balls 160, and a portion of the passivation layer 140.
In the present embodiment, the photoresist material layer 172 softened or decomposed by the light L1 in the trench 111 can be removed to expose the carrier 10.
Please continue to refer to fig. 1I and fig. 1K. After the developing process, a curing process may be performed to cure a portion of the photoresist material layer 171 (shown in fig. 1G or fig. 1H) filled in the first voids 153 and the second voids 163, so as to form a dielectric layer 173 between the first solder balls and the passivation layer 140 and between the second solder balls and the passivation layer 140. In other words, the dielectric layer 173 can also be referred to as a dielectric block surrounding the base of the first solder balls 150 and the second solder balls 160 to achieve the effect of supporting and protecting the first solder balls 150 and the second solder balls 160, thereby reducing the probability of ball dropping of the first solder balls 150 and the second solder balls 160.
In the present embodiment, the dielectric layer 173 is formed by curing the photoresist, and thus, the material of the dielectric layer 173 includes a photosensitive dielectric material (PID).
The above-described process may substantially complete the fabrication of one or more circuit board elements 100.
In the present embodiment, if the singulation process shown in fig. 1C is performed in any previous step, the carrier 10 for placing the circuit board elements 100 may be removed to form the circuit board elements 100 shown in fig. 1J.
Structurally, the circuit board element 100 of the present embodiment includes an insulating layer 120, circuit layers 130 and 130', protective layers 140 and 140', a plurality of first solder balls 150, a plurality of second solder balls 160, and a dielectric layer 173. The circuit layer 130 and the circuit layer 130' are respectively located on two opposite sides of the insulating layer 120. The protection layer 140 is disposed on the circuit layer 130, and the protection layer 140 'is disposed on the circuit layer 130'. The passivation layer 140 has a plurality of first openings 145 and a plurality of second openings 146 exposing the circuit layer 130. The first solder balls 150 are disposed on the passivation layer 140 and embedded in the corresponding first openings 145. The second solder balls 160 are disposed on the passivation layer 140 and embedded in the corresponding second openings 146. The dielectric layer 173 is located between the first solder ball 150 and the passivation layer 140 and between the second solder ball 160 and the passivation layer 140.
In the present embodiment, in a direction perpendicular to the surface 140a of the passivation layer 140, an orthogonal projection of the dielectric layer 173 on the surface 140a of the passivation layer 140 substantially overlaps and is located within an orthogonal projection of the corresponding first solder ball 150 or the second solder ball 160 on the surface 140a of the passivation layer 140. In other words, in a direction perpendicular to the surface 140a of the passivation layer 140, the edge 173c of the dielectric layer 173 may be aligned with the corresponding edge 151c of the top end 151 of the first solder ball 150 (i.e., the tangent plane of the first solder ball 150 perpendicular to the surface 140a of the passivation layer 140) or the edge 161c of the top end 161 of the second solder ball 160 (i.e., the tangent plane of the second solder ball 160 perpendicular to the surface 140a of the passivation layer 140).
In some possible embodiments, during the formation of the dielectric layer 173, the orthographic projection of the dielectric layer 173 on the surface 140a of the passivation layer 140 may slightly exceed the orthographic projection of the corresponding first solder ball 150 or the second solder ball 160 on the surface 140a of the passivation layer 140 due to slight deviation of the exposure process, a slight amount of photoresist material removed but not removed in the development process, or partial softening of the photoresist material in the curing process, but the foregoing situation may be covered in the equivalent range that "the orthographic projection of the dielectric layer 173 on the surface 140a of the passivation layer 140 is substantially overlapped and located within the orthographic projection of the corresponding first solder ball 150 or the second solder ball 160 on the surface 140a of the passivation layer 140" or has the same or similar meaning, without departing from the spirit of the present invention.
Fig. 2A to fig. 2D are schematic cross-sectional views illustrating a part of a method for manufacturing a circuit board element according to a second embodiment of the invention. The manufacturing method of the circuit board element 200 of the present embodiment is similar to the manufacturing method of the circuit board element 100 of the first embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials, or forming manners, and descriptions thereof are omitted. Specifically, fig. 2A to 2D are schematic cross-sectional views illustrating a part of the manufacturing method following the step in fig. 1E. Also, the enlarged view of region R3 'in fig. 2A may be the same as or similar to region R3 in fig. 1H, and the enlarged view of region R4' in fig. 2B, 2C, or 2D may be the same as or similar to region R4 in fig. 1K.
Referring to fig. 2A, a singulation process shown in fig. 1C is performed before forming the photoresist material layer 171 (shown in fig. 1E or fig. 1F) in the following step of fig. 1E. After forming the photoresist material layer 171 on the wiring substrate 110, the photoresist material layer 171 is exposed by the mask 22. In the present embodiment, the material of the photoresist material layer 171 is a positive photoresist.
In the present embodiment, the region of the mask 22 shielding the light L1 at least overlaps the trench 111 (shown in fig. 1C). In some embodiments, not shown, the region of the mask 22 shielding the light L1 may overlap the first solder balls 150 and/or the second solder balls 160 in addition to the trench 111. In another embodiment, the mask 22 may have a plurality of slits 22a overlapping the trench 111, and a gray-scale mask is formed by slit interference, so that the exposure depth of the light L1 in the trench 111 can be adjusted to expose only a portion of the photoresist material layer 171 on the trench 111.
Next, please refer to fig. 2B. After the exposure process, a developing process may be performed to remove the first and second gaps 153 and 163, and the photoresist material layer 272 (shown in fig. 2A) softened or decomposed by the light L1 (shown in fig. 2A) to expose the arc-shaped top surfaces 151a and 161a of the first and second solder balls 150 and 160 and a portion of the passivation layer 140.
Please continue with fig. 2B. After the developing process, a curing process may be performed to cure a portion of the photoresist material layer 171 (shown in fig. 1H) filled in the first and second voids 153 and 163 and a portion of the photoresist material layer 171 (shown in fig. 2A) in the trench 111.
In another embodiment, before or after the curing process, a portion of the photoresist material layer 171 (shown in fig. 2A) on the trench 111 can be thinned by a plasma etching process, so that the top surface of the partially cured photoresist material layer 273' is approximately coplanar (coplanar) with the top surface of the protection layer 140, but the invention is not limited thereto.
Next, referring to fig. 2C, after the curing process, the partially cured photoresist material layer 273 '(shown in fig. 2B) in the trench 111 may be removed, for example, by cutting the partially cured photoresist material layer 273' in the trench 111 with a blade, a wheel knife or a laser beam, so as to further form the dielectric layer 273 in the trench 111 and expose the carrier 10 from the trench 111.
The fabrication of one or more circuit board elements 200 may be substantially completed by the above-described process. Also, the carrier 10 for placing the plurality of circuit board elements 200 may be removed to form a plurality of circuit board elements 100 as shown in fig. 2D.
Structurally, the circuit board element 200 of the present embodiment is similar to the circuit board element 100 of the first embodiment, with the main differences being: of the dielectric layers 173, 273 of the circuit board element 200, a portion of the dielectric layer 273 further covers the sidewall 120c of the insulating layer 120 and the sidewall 140b of the protection layer 140.
Fig. 3A to fig. 3E are schematic cross-sectional views illustrating a part of a method for manufacturing a circuit board element according to a third embodiment of the invention. The manufacturing method of the circuit board element 300 of the present embodiment is similar to the manufacturing method of the circuit board element 100 of the first embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials or forming manners, and descriptions thereof are omitted. Specifically, fig. 3A to 3E show schematic cross-sectional views of a part of the method of manufacturing the circuit board element 100 following the steps in fig. 1E. Fig. 3B may be an enlarged view of region R5 in fig. 3A. Fig. 3D may be an enlarged view of region R6 in fig. 3C. Fig. 3H may be an enlarged view of region R7 in fig. 3E, 3F, or 3G.
Referring to fig. 3A and 3B, a singulation process shown in fig. 1C is performed before the photoresist material layer 371 is formed. Furthermore, a photoresist material layer 371 is formed on the circuit substrate 110, and the photoresist material layer 371 may further fill the trench 111 (shown in fig. 1C). The photoresist material layer 371 directly contacts to cover the surface 140a of the passivation layer 140, the arc-shaped top surface 151a of the ball top 151, the arc-shaped bottom surface 151b of the ball top 151, the arc-shaped top surface 161a of the ball top 161, the arc-shaped bottom surface 161b of the ball top 161, and the exposed carrier 10 of the trench 111. That is, the photoresist material layer 371 is located on the passivation layer 140, the first solder balls 150, the second solder balls 160 and the filling trenches 111, and also fills the first gaps 153 between the passivation layer 140 and the first solder balls 150 and the second gaps 163 between the passivation layer 140 and the second solder balls 160.
In the present embodiment, the material of the photoresist material layer 371 may be a negative photoresist (negative photoresist). And in some embodiments, the material of the photoresist material layer 371 may include barium titanate, boron nitride, alumina, silicon dioxide, strontium titanate, barium strontium titanate, quartz or other suitable filler besides the negative photoresist.
Next, please refer to fig. 3C and fig. 3D. After forming the photoresist material layer 371 (shown in fig. 3A or fig. 3B) on the circuit substrate 110, an anisotropic etching process is performed on the photoresist material layer 371 to remove a portion of the photoresist material layer 371 outside the first and second voids 153 and 163. After the anisotropic etching process, the photoresist material layer 371' (shown in fig. 3D) on the surface 140a of the passivation layer 140 may be located in the first gap 153 and the second gap 163, and may expose the arc-shaped top surface 151a of the first solder ball 150, the arc-shaped top surface 161a of the second solder ball 160, and a portion of the passivation layer 140.
In the present embodiment, the anisotropic etching process is, for example, a reactive-ion etching (RIE) process or a plasma etching (plasma etching) process, but the invention is not limited thereto.
In the present embodiment, after the anisotropic etching process, the photoresist material layer 371' filled in the trench 111 may be coplanar (coplanar) with the surface 140a of the protection layer 140, but the invention is not limited thereto.
Please refer to fig. 3E. After the anisotropic etching process, the photoresist material layer 371 ' (shown in fig. 3C or fig. 3D) is exposed to light through the mask 32 to cure the photoresist material layer 371 ' irradiated by the light L2, thereby forming the dielectric layers 373, 373 '.
In the present embodiment, the exposure process is, for example, a strong exposure process (strong exposure process) or a multiple exposure process (e.g., double exposure process). Therefore, even though the portion of the photoresist material layer 371' (shown in fig. 3D) filled in the first gap 153 and the second gap 163 in the direction perpendicular to the surface 140a of the passivation layer 140 is shielded by the top end 151 of the first solder ball 150 and the top end 161 of the second solder ball 160, the photoresist material layer can still be irradiated by the scattered light of the light L2 or the light L2 slightly deviating from the direction perpendicular to the surface 140a of the passivation layer 140, so as to form the dielectric layer 373.
In the present embodiment, the area of the mask 32 shielding the light L2 at least does not overlap the first solder balls 150 and the second solder balls 160. In some embodiments, the region of the mask 32 that shields the light L2 does not overlap the sidewalls of the trench 111, and the portion of the photoresist material 371 '(shown in fig. 3D) that covers the sidewalls of the trench 111 may form a dielectric layer 373'.
Next, please refer to fig. 3F. After the exposure process, a developing process may be performed to remove the uncured photoresist material layer 372 (shown in fig. 3E) in the trench 111 to expose a portion of the carrier 10.
The fabrication of one or more circuit board elements 300 may be substantially completed by the above-described processes.
In the present embodiment, the carrier 10 for placing the plurality of circuit board elements 300 may be removed to form the plurality of circuit board elements 300.
Structurally, the circuit board element 300 of the present embodiment is similar to the circuit board element 200 of the second embodiment, with the main differences being: the material forming the dielectric layers 373, 373' may be a negative photoresist. That is, the material of the dielectric layers 373, 373' includes a photosensitive dielectric material.
Specifically, the circuit board element 100 of the present embodiment includes an insulating layer 120, circuit layers 130 and 130', protective layers 140 and 140', a plurality of first solder balls 150, a plurality of second solder balls 160, and a dielectric layer 373. The dielectric layer 373 is disposed between the first solder ball 150 and the passivation layer 140 and between the second solder ball 160 and the passivation layer 140.
In the present embodiment, in a direction perpendicular to the surface 140a of the passivation layer 140, an orthogonal projection of the dielectric layer 373 on the surface 140a of the passivation layer 140 substantially overlaps and is located within an orthogonal projection of the corresponding first solder ball 150 or second solder ball 160 on the surface 140a of the passivation layer 140. In other words, in a direction perpendicular to the surface 140a of the protection layer 140, an edge 373c of the dielectric layer 373 may be aligned with a corresponding edge 151c of the top end 151 of the first solder ball 150 or an edge 161c of the top end 161 of the second solder ball 160.
In some possible embodiments, during the formation of the dielectric layer 373, the orthographic projection of the dielectric layer 373 on the surface 140a of the passivation layer 140 may slightly exceed the orthographic projection of the corresponding first solder ball 150 or the second solder ball 160 on the surface 140a of the passivation layer 140 due to slight deviation of the exposure process, a slight amount of photoresist material removed but not removed in the development process, or partial softening of the photoresist material in the curing process, but the foregoing situation may be covered in the equivalent range that the orthographic projection of the dielectric layer 373 on the surface 140a of the passivation layer 140 is substantially overlapped and located within the orthographic projection of the corresponding first solder ball 150 or the second solder ball 160 on the surface 140a of the passivation layer 140 or has the same or similar meaning, without departing from the spirit of the present invention.
Fig. 4A to 4C are schematic cross-sectional views illustrating a part of a method for manufacturing a circuit board element according to a fourth embodiment of the invention. The manufacturing method of the circuit board element 400 of the present embodiment is similar to the manufacturing method of the circuit board element 300 of the third embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials or forming manners, and descriptions thereof are omitted. Specifically, fig. 4A to 4C show schematic cross-sectional views of a part of a method of manufacturing the circuit board element 300 following the steps in fig. 3C. Also, the enlarged view of region R7' in fig. 4A, 4B, or 4C may be the same as or similar to region R7 in fig. 3H.
Referring to fig. 4A, after the anisotropic etching process, an exposure process is performed on the photoresist material layer 371 '(shown in fig. 3C or fig. 3D) by using the mask 42 to cure the photoresist material layer 371' irradiated by the light L2, so as to form a dielectric layer 373, as shown in fig. 3C. In the present embodiment, the material of the photoresist material layer 371' may be a negative photoresist.
In the present embodiment, the area of the mask 42 shielding the light L2 at least does not overlap the first solder balls 150 and the second solder balls 160, and completely overlaps the trench 111. That is, the photoresist material layer 472 in the trench 111 is not irradiated by the light L2 and is not cured.
In the present embodiment, the exposure process shown in fig. 4A may be the same as or similar to the exposure process shown in fig. 3C.
Next, please refer to fig. 4B. After the exposure process, a developing process may be performed to remove the uncured photoresist material layer 472 (shown in fig. 4A) in the trench 111 (shown in fig. 1C) to expose a portion of the carrier 10.
The fabrication of one or more circuit board elements 400 may be substantially completed by the above-described processes.
In the present embodiment, the carrier 10 for placing the plurality of circuit board elements 400 may be removed to form the plurality of circuit board elements 400.
Structurally, the circuit board element 400 of the present embodiment is similar to the circuit board element 100 of the first embodiment, with the main differences being: the material forming the dielectric layer 473 may be a negative photoresist. That is, the material of the dielectric layer 473 includes a photosensitive dielectric material.
Fig. 5A to 5C are schematic cross-sectional views illustrating a part of a method for manufacturing a circuit board element according to a fifth embodiment of the invention. The manufacturing method of the circuit board element 500 of the present embodiment is similar to the manufacturing method of the circuit board element 100 of the third embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials or forming manners, and descriptions thereof are omitted. Specifically, fig. 5A to 5C show schematic cross-sectional views of a part of a method of manufacturing the circuit board element 300 following the steps in fig. 3C. Also, the enlarged view of region R7 "in fig. 5A, 5B, or 5C may be the same as or similar to region R7 in fig. 3H.
Referring to FIG. 5A, after the anisotropic etching process, an exposure process is performed on the photoresist material layer 371' (shown in FIG. 3C or FIG. 3D), such as a strong exposure process (strong exposure process) or a multiple exposure process (double exposure process) (e.g., double exposure process). To cure the photoresist material layer 371' within the first voids 153, the second voids 163, and the trenches 111 (shown in fig. 1C).
In the present embodiment, the exposure process shown in fig. 5A is similar to the exposure process shown in fig. 3C, and the main difference is: no mask is used in the exposure process shown in fig. 5A. Thus, the portion of the photoresist material layer 371 'located in the trench 111 can be irradiated by the light L2 to form a cured photoresist material layer 573'.
Next, referring to fig. 5B, after the curing process, the partially cured photoresist material layer 573 '(shown in fig. 5A) in the trench 111 may be cut or removed, for example, by cutting the partially cured photoresist material layer 273' in the trench 111 with a blade, a wheel knife or a laser beam, so as to form the dielectric layer 573 and expose the carrier 10 from the trench 111.
The fabrication of one or more circuit board elements 500 may be substantially completed by the above-described processes.
In this embodiment, the carrier 10 for placing the plurality of circuit board elements 500 may be removed to form a plurality of circuit board elements 500 as shown in fig. 5C.
The circuit board element 500 of the present embodiment is the same as or similar to the circuit board element 300 of the third embodiment in structure or material. Specifically, the dielectric layer 573 in the circuit board element 500 may be identical or similar in structure or material to the dielectric layer 373' in the circuit board element 300.
In summary, the dielectric layer is formed between the solder ball and the passivation layer by the photoresist. The dielectric layer between the solder ball and the protective layer can directly contact the arc-shaped bottom surface of the spherical top end of the solder ball so as to support or fix the spherical top end of the solder ball. In other words, the dielectric layer between the solder balls and the passivation layer can also be referred to as a dielectric block surrounding the base of the solder balls to support and protect the solder balls. Therefore, the possibility of solder ball detachment can be reduced, and the yield of the circuit board element can be improved. In addition, even though the solder balls have different sizes, the dielectric layer between the solder balls with different sizes and the protective layer can have different sizes by the manufacturing method of the invention. Therefore, even if the solder balls have different sizes, the solder balls can pass through the corresponding dielectric layers to reduce the possibility of separation, and the electrical connection with other electronic elements cannot be influenced because the dielectric layers between the solder balls with different sizes and the protective layer have the same size or height.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.
Claims (20)
1. A method of making a circuit board component, comprising:
providing a circuit substrate, the circuit substrate comprising:
an insulating layer;
a circuit layer on the insulating layer;
the protective layer is positioned on the circuit layer and is provided with a plurality of openings for exposing the circuit layer; and
a plurality of solder balls, which are configured on the protective layer and are embedded into the corresponding openings, and gaps are arranged between the solder balls and the protective layer;
placing the circuit substrate on a carrier, wherein the plurality of solder balls are far away from the carrier;
forming at least one trench penetrating through the circuit substrate to expose the carrier;
forming a photoresist material layer on the circuit substrate to cover the circuit substrate and fill in the plurality of gaps, and to fill in the at least one trench to cover the carrier;
curing the photoresist material layer filled into the gaps to form a dielectric layer at least between the solder balls and the protective layer;
removing a portion of the photoresist material layer filled in the at least one trench to expose the carrier; and
removing the carrier.
2. A method for manufacturing a circuit board element as claimed in claim 1, characterized in that the material of said layer of photoresist material comprises photoresist and filler.
3. A method for manufacturing a circuit board element according to claim 1, characterized in that the material of said layer of photoresist material comprises positive photoresist, and that said method further comprises:
before the dielectric layer is formed, exposing and developing the photoresist material layer to remove the part of the photoresist material layer which is not filled in the gaps and expose the solder balls and part of the protective layer.
4. A method for manufacturing a circuit board element according to claim 1, characterized in that the material of said layer of photoresist material comprises positive photoresist, and that said method further comprises:
before the dielectric layer is formed, exposing and developing the photoresist material layer to remove a portion of the photoresist material layer not filled in the plurality of gaps and expose the plurality of solder balls, a portion of the protective layer and the carrier corresponding to the trench.
5. A method for manufacturing a circuit board element according to claim 1, characterized in that the material of said layer of photoresist material comprises positive photoresist, and that said method further comprises:
before forming the dielectric layer, exposing and developing the photoresist material layer by a mask to remove part of the photoresist material layer and expose the solder balls and part of the protective layer;
and curing the photoresist material layer filled in the plurality of gaps and covering the part of the photoresist material layer on the side wall of the ditch to form the dielectric layer.
6. The method of claim 5, wherein said mask has a plurality of slits.
7. A method for manufacturing a circuit board element according to claim 1, characterized in that the material of the layer of photoresist material comprises negative photoresist, and the method further comprises:
before forming the dielectric layer, an anisotropic etching process is performed on the photoresist material layer to remove a portion of the photoresist material layer and expose the solder balls and a portion of the passivation layer.
8. A method for manufacturing a circuit board element according to claim 1, characterized in that the material of the layer of photoresist material comprises negative photoresist, and the method further comprises:
before forming the dielectric layer, performing an anisotropic etching process on the photoresist material layer to remove a portion of the photoresist material layer not filled in the plurality of voids and expose the plurality of solder balls and a portion of the passivation layer; and
and carrying out an exposure process on the photoresist material layer by using the mask so as to solidify and fill part of the photoresist material layer in the plurality of gaps to form the dielectric layer.
9. The method as claimed in claim 8, wherein said exposing further cures a portion of said photoresist material layer overlying a sidewall of said at least one trench to form said dielectric layer.
10. A method for manufacturing a circuit board element according to claim 1, characterized in that the material of the layer of photoresist material comprises negative photoresist, and the method further comprises:
before forming the dielectric layer, performing an anisotropic etching process on the photoresist material layer to remove a portion of the photoresist material layer not filled in the plurality of voids and expose the plurality of solder balls and a portion of the passivation layer;
performing an exposure process on the photoresist material layer to cure a portion of the photoresist material layer filled in the plurality of voids and the at least one trench; and
removing the part of the photoresist material layer filled in the at least one trench to solidify the photoresist material layer so as to form the dielectric layer.
11. The method of claim 1, wherein said removing of said partially cured photoresist material layer filling said at least one trench is by dicing.
12. A circuit board component, comprising:
an insulating layer;
a circuit layer on the insulating layer;
the protective layer is positioned on the circuit layer and is provided with a plurality of openings for exposing the circuit layer; and
a plurality of solder balls which are configured on the protective layer and are embedded into the corresponding openings; and
and the dielectric layer is positioned between the solder balls and the protective layer.
13. A circuit board element according to claim 12, characterised in that the insulating layer comprises a core layer.
14. The circuit board element of claim 13, wherein the material of the core layer is different from the material of the protective layer and the dielectric layer, and the material of the core layer comprises a polymer glass fiber composite substrate, a glass substrate, a ceramic substrate, a silicon-on-insulator substrate, or a polyimide glass fiber composite substrate.
15. The circuit board element of claim 12, wherein the dielectric layer comprises a photosensitive dielectric material.
16. The circuit board element of claim 15, wherein the dielectric layer further comprises a filler.
17. The circuit board element of claim 12, wherein an orthographic projection of the dielectric layer on the passivation layer is overlapped with an orthographic projection of the solder balls on the passivation layer.
18. The circuit board element of claim 12, wherein edges of the dielectric layer are aligned with edges of the plurality of solder balls.
19. The circuit board element of claim 12, wherein the dielectric layer further covers sidewalls of the insulating layer and sidewalls of the protective layer.
20. The circuit board element of claim 12, wherein the plurality of solder balls comprises a plurality of first solder balls and a plurality of second solder balls, wherein the size of the plurality of first solder balls is larger than the size of the plurality of second solder balls, and wherein the size of the dielectric layer between the plurality of first solder balls and the protective layer is larger than the size of the dielectric layer between the plurality of second solder balls and the protective layer.
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| US20050020051A1 (en) * | 2003-07-21 | 2005-01-27 | Advanced Semiconductor Engineering, Inc. | Method for forming bump protective collars on a bumped wafer |
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