CN110677145A - Impulse current suppression circuit and method for suppressing impulse current thereof - Google Patents
Impulse current suppression circuit and method for suppressing impulse current thereof Download PDFInfo
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Abstract
A surge current suppression circuit comprises a first switch, a pre-charging branch circuit, a third switch and a control device. The first switch is connected between the input voltage and the bus capacitor; the pre-charging branch circuit is connected with the first switch in parallel and comprises a second switch and a resistor which are connected in series; the third switch is connected between the bus capacitor and the load, and the load is connected with the bus capacitor in parallel. The output end of the control device is respectively connected with the control ends of the first switch, the second switch and the third switch. The invention also discloses a method for inhibiting the impact current by the impact current inhibiting circuit. The invention can effectively inhibit the impact current generated when the switch is conducted, and has good universality and low cost.
Description
Technical Field
The present invention relates to a rush current suppression technique.
Background
A large number of controllers are used in a vehicle, some of which contain power modules, such as power converters that provide power, which can directly drive an electric motor or solenoid valve load. In a power module, a bus capacitor with a large capacitance value is required to maintain normal operation of the device, and an internal bus of a controller is usually connected to an input power supply of the controller through an input power switch, which is usually a semiconductor switch, such as a MOS transistor, a triode, or the like. In the process of electrifying the controller, the input power switch is conducted, and the bus capacitor is charged. If left uncontrolled, a large inrush current can be generated when the input power switch is turned on, thereby affecting the power supply network and causing undesirably large stresses on the semiconductor devices.
At present, the following two methods are mainly used to reduce the inrush current when the input power switch is closed:
Disclosure of Invention
The invention aims to provide an impact current suppression circuit which can effectively suppress impact current generated when a switch is conducted, has good universality and is low in cost.
Another object of the present invention is to provide a method for suppressing a rush current.
An embodiment of the present invention provides an impulse current suppression circuit, including: a first switch connected between the input voltage and the bus capacitor; a pre-charging branch connected in parallel with the first switch, the pre-charging branch comprising a second switch and a resistor connected in series; the third switch is connected between the bus capacitor and the load, and the load is connected with the bus capacitor in parallel; the output end of the control device is respectively connected with the control end of the first switch, the control end of the second switch and the control end of the third switch; the control device is used for controlling the second switch to be connected and controlling the first switch and the third switch to be disconnected so as to enable the input voltage to charge the bus capacitor through the pre-charging branch, when the voltage difference value between the input voltage and the voltage of the bus capacitor is smaller than or equal to a preset first voltage difference threshold value, the first switch is firstly controlled to be connected, and after the first switch is normally connected, the second switch is sequentially controlled to be disconnected and the third switch is sequentially controlled to be connected.
The embodiment of the invention also provides a method for inhibiting the impact current by the impact current inhibiting circuit, which comprises the following steps:
the control device controls the second switch to be connected and controls the first switch and the third switch to be disconnected, so that the input voltage charges the bus capacitor through the pre-charging branch circuit;
the control device judges whether a voltage difference value between the input voltage and the bus capacitor voltage is smaller than or equal to a preset first voltage difference threshold value or not, when the voltage difference value between the input voltage and the bus capacitor voltage is smaller than or equal to the preset first voltage difference threshold value, the first switch is controlled to be switched on, and after the first switch is normally switched on, the second switch is controlled to be switched off and the third switch is controlled to be switched on in sequence.
Another embodiment of the present invention provides a rush current suppression circuit, including: the first switch is connected between the input voltage and the bus capacitor, and the bus capacitor is connected with the load in parallel; a pre-charging branch connected in parallel with the first switch, the pre-charging branch comprising a second switch and a resistor connected in series; the output end of the control device is respectively connected with the control end of the first switch, the control end of the second switch and the enabling end of the load; the control device is used for controlling the second switch to be connected and controlling the first switch to be disconnected and the load to be disabled so that the input voltage charges the bus capacitor through the pre-charging branch, when the voltage difference value between the input voltage and the voltage of the bus capacitor is smaller than or equal to a preset first voltage difference threshold value, the first switch is controlled to be connected, and after the first switch is normally connected, the second switch is sequentially controlled to be disconnected and the load is enabled.
Another embodiment of the present invention further provides a method for suppressing a rush current by using the above-mentioned rush current suppression circuit, including the following steps:
the control device controls the second switch to be switched on and controls the first switch to be switched off and the load to be disabled, so that the input voltage charges the bus capacitor through the pre-charging branch circuit;
the control device judges whether a voltage difference value between the input voltage and the bus capacitor voltage is smaller than or equal to a preset first voltage difference threshold value or not, when the voltage difference value between the input voltage and the bus capacitor voltage is smaller than or equal to the preset voltage difference threshold value, the first switch is controlled to be switched on, and after the first switch is normally switched on, the second switch is sequentially controlled to be switched off and enable the load.
After the technical scheme is adopted, the invention at least has the following advantages and characteristics:
1. in the invention, the load can be cut off by controlling the third switch to be switched off or disabling the load, and after the second switch is switched on and the charging of the bus capacitor is completed, the voltage difference between two ends of the first switch is closer to 0V when the first switch is switched on, so that the surge current and the stress of the first switch are smaller when the first switch is switched on, and the harsher surge current requirement can be met. Correspondingly, a low-current low-power semiconductor switch device with low cost can be selected as the first switch, so that the effect of reducing the cost is achieved;
2. compared with the prior art, the embodiment of the invention can select the resistor with higher resistance value and lower power level under the same condition, not only can not obviously influence surge current in the conduction process of the first switch, but also can ensure that the impulse current in the conduction process of the second switch is lower, and the encapsulation of the resistor with larger resistance value and lower power level is smaller, thereby reducing the cost and reducing the current consumption of a bus circuit in the pre-charging stage. Correspondingly, in the embodiment of the invention, a low-current low-power semiconductor switch device with lower cost can be selected as the second switch, so that the effect of reducing the cost is achieved;
3. by adopting the embodiment of the invention, the adjustment of the load can not cause the obvious change of the surge current in the conducting process of the first switch. This means that embodiments of the invention are more versatile, e.g. the design may be unchanged only in case of load changes, so that the costs in the design, test and production phases can be reduced;
4. in the process of conducting the second switch, because the load is in a non-working state, even if unexpected change occurs in the load, surge current cannot be increased, and the switching device cannot be damaged.
Drawings
Fig. 1 shows a circuit schematic of a conventional inrush current suppression circuit.
Fig. 2 shows a circuit schematic of a rush current suppression circuit according to a first embodiment of the present invention.
Fig. 3 shows a schematic diagram of control signals sent by the control device to the first switch, the second switch and the third switch according to the first embodiment of the invention.
Fig. 4 shows a circuit schematic of a rush current suppression circuit according to a second embodiment of the present invention.
Fig. 5 shows simulated waveforms of bus capacitor voltage, inrush current when the first switch S1 is turned on, and instantaneous power consumption when the first switch S1 is turned on in the precharge stage of the conventional vehicle chassis controller product without the third switch S3.
Fig. 6 shows simulated waveform diagrams of bus capacitor voltage, inrush current when the first switch S1 is turned on, and instantaneous power consumption when the first switch S1 is turned on of the vehicle chassis controller product provided with the third switch S3 after improvement in the precharge stage.
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments.
The inventors have found in practice that the method 2 described in the "background" section of the present specification suffers from the following disadvantages:
1. after the second switch S2 is turned on, the load 9 is also energized to generate an operating current, which causes a voltage drop across the resistor R1, so that a certain surge current still exists during the turn-on of the first switch S1, and a high-cost, large-current and high-power semiconductor switching device has to be used. In addition, with the increasing precision of automobile electronic design, the control requirement on surge current will be more and more strict, so that the method 2 cannot meet the more and more severe surge current requirement in the future;
2. in the prior art, generally, a resistor R1 with a lower resistance value and a higher power level is selected as much as possible, so that the voltage drop across the resistor R1 can be reduced to a certain extent, and thus the surge current when the first switch S1 is closed is reduced, but correspondingly, the lower resistance value of R1 also means that the suppression effect of the surge current when the second switch S2 is turned on is poor, and in addition, the lower resistance value of the high-power resistor R1 means higher power consumption and larger package, and a high-cost high-current high-power semiconductor switching device is required to be used as the second switch S2, which leads to increased cost and power consumption;
3. in different design schemes, the resistor R1 needs to be adjusted according to the input voltage, the load 9 and the surge current design requirement, which means more time, equipment and manpower are needed to reselect and test the resistor R1 to meet the design requirement of the scheme, and more types of resistors R1 need to be stored and managed in the factory, thereby causing the cost to rise greatly;
4. if unexpected changes occur in the load 9 during the conduction of the second switch S2, for example, if the current flowing through the load 9 is larger than the normal range due to a fault or deterioration of the use environment of the load 9, unexpected increases in the voltage across the load 9 may occur, that is, the inrush current during the conduction of the first switch S1 may also become larger than expected, which may further lead to undesirable consequences, for example, damage or malfunction of the switching device, or malfunction of other circuits than the load 9.
The prior art cannot solve the technical problems.
Fig. 2 shows a circuit schematic of a rush current suppression circuit according to a first embodiment of the present invention. The inrush current suppression circuit according to the first embodiment of the present invention includes a first switch S1, a precharge branch, a third switch S3, a first voltage detection circuit 11, a second voltage detection circuit 12, and a control device 3.
The first switch S1 is connected between the input voltage and the bus capacitance C1. The pre-charging branch is connected in parallel with the first switch S1, and includes a second switch S2 and a resistor R1 connected in series. The third switch S3 is connected between the bus capacitor C1 and the load 9, and the load 9 is connected in parallel with the bus capacitor C1. The input voltage can be provided by a power supply or a voltage conversion circuit. The first switch S1 is an input safety switch of a product, and a semiconductor power switch, such as a MOS transistor, is generally used. In the present embodiment, the second switch S2 and the third switch S3 also employ semiconductor switches.
The first voltage detection circuit 11 is used for detecting the magnitude of the input voltage; the second voltage detection circuit 12 is used for detecting the voltage of the bus capacitor C1.
The input terminals of the control device 3 are connected to the output terminals of the first voltage detection circuit 11 and the second voltage detection circuit 12, respectively, and the output terminal of the control device 3 is connected to the control terminal of the first switch S1, the control terminal of the second switch S2, and the control terminal of the third switch S3, respectively. The control device 3 is configured to control the second switch S2 to be turned on and control the first switch S1 and the third switch S3 to be turned off, so that the input voltage charges the bus capacitor C1 through the pre-charging branch, and determine whether a voltage difference between the input voltage and the voltage of the bus capacitor C1 is smaller than or equal to a preset voltage difference threshold in real time, when the voltage difference between the input voltage and the voltage of the bus capacitor C1 is smaller than or equal to the preset voltage difference threshold, control the first switch S1 to be turned on first, and after the first switch S1 is normally turned on, sequentially control the second switch S2 to be turned off and the third switch S3 to be turned on.
Optionally, the control device is an MCU inside the product.
A method for suppressing a rush current by a rush current suppression circuit according to a first embodiment of the present invention includes the steps of:
step a1, the control device 3 controls the second switch S2 to be turned on and controls the first switch S1 and the third switch S3 to be turned off, so that the input voltage is charged to the bus capacitor C1 through the pre-charging branch;
in the power-on stage of the product, the first switch S1, the second switch S2 and the third switch S3 are all turned off, when the control device 3 detects that the product meets the power-on condition (for example, the power-on button is pressed, or the input voltage enters a predetermined power-on range, or the product is awakened by the internet), the second switch S2 is controlled to be turned on, at this time, the input voltage charges the bus capacitor C1 through the pre-charging branch formed by the resistor R1 and the second switch S2, the magnitude of the charging peak current does not exceed the input voltage/R1, so the peak current is controllable and easy to adjust, and the value of the resistor R1 can be preset according to the peak charging current to be controlled and the required charging time. The third switch S3 is used to disconnect the load 9 of the bus from the bus during the charging process, so that the actual load on the bus is very small and the voltage of the bus capacitor C1 is very close to the input voltage after the charging process is over;
in step a2, the control device 3 determines whether the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to a preset first voltage difference threshold (the magnitude of the first voltage difference threshold is, for example, 1V), and when the voltage difference between the input voltage and the voltage of the bus capacitor is less than or equal to the preset first voltage difference threshold, the first switch S1 is first controlled to be turned on, and after the first switch S1 is normally turned on, the second switch S2 is sequentially controlled to be turned off, and the third switch S3 is sequentially controlled to be turned on. When the first switch S1 is controlled to be turned on, the first switch S1 does not generate large rush current and high stress during the turn-on process because the bus capacitor voltage at this time is already pre-charged to be very close to the input voltage. Fig. 3 shows a schematic diagram of the control signals sent by the control device 3 to the first switch S1, the second switch S2 and the third switch S3 according to the first embodiment of the invention.
Further, when a first preset time elapses from the time when the second switch S2 is turned on and the first switch S1 and the third switch S3 are controlled to be turned off, if it is determined that the voltage difference between the input voltage and the bus capacitor voltage is still greater than the preset first voltage difference threshold, it indicates that a product has a defect or that the external condition does not meet the requirement, the control device 3 controls the first switch S1 and the third switch S3 to be turned off to protect the circuit. The first preset time may be selected to be 300 ms. The first preset time can also be adjusted according to actual circuit parameters.
Further, the control device 3 determines in real time from when the first switch S1 is turned on whether the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to a preset second voltage difference threshold, and when the voltage difference between the input voltage and the voltage of the bus capacitor is less than or equal to the preset second voltage difference threshold, the control device 3 determines that the first switch S1 is normally turned on. When the first switch S1 is normally turned on, the voltage difference between the input voltage and the voltage of the bus capacitor C1 is close to 0V. The second voltage difference threshold is smaller than the first voltage difference threshold, in this embodiment, the preset second voltage difference threshold is selected to be 0.1V, and the threshold may also be adjusted according to the actual circuit parameter. Alternatively, after the control device 3 controls the first switch S1 to be turned on, the control device 3 may directly determine that the first switch S1 has been turned on normally after a second preset time, for example, 100 us. The second predetermined time may also be adjusted based on actual circuit parameters.
As a modification of the first embodiment, it is also optional not to provide the first voltage detection circuit 11 and the second voltage detection circuit 12. Accordingly, when a first preset time (optionally 300ms in this embodiment) elapses from when the control device 3 controls the second switch S2 to turn on and controls the first switch S1 and the third switch S3 to turn off, the control device 3 directly determines that the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold, the control device first controls the first switch S1 to turn on, and after the first switch S1 is normally turned on, the control device sequentially controls the second switch S2 to turn off and the third switch S3 to turn on. When a second predetermined time (for example, 100us) elapses after the control device 3 controls the first switch S1 to be turned on, the control device 3 determines that the first switch S1 is normally turned on.
Fig. 4 shows a circuit schematic of a rush current suppression circuit according to a second embodiment of the present invention. The inrush current suppression circuit according to the second embodiment of the present invention includes a first switch S1, a precharge branch, a first voltage detection circuit 11, a second voltage detection circuit 12, and a control device 3.
The first switch S1 is connected between the input voltage and the bus capacitor C1, and the bus capacitor C1 is connected in parallel with the load 9. The pre-charging branch is connected in parallel with the first switch S1, and includes a second switch S2 and a resistor R1 connected in series.
The first voltage detection circuit 11 is used for detecting the magnitude of the input voltage; the second voltage detection circuit 12 is used for detecting the voltage of the bus capacitor C1.
The input end of the control device 3 is connected to the output end of the first voltage detection circuit 11 and the output end of the second voltage detection circuit 12, respectively, and the output end of the control device 3 is connected to the control end of the first switch S1, the control end of the second switch S2, and the enable end of the load 9, respectively. The control device 3 is configured to control the second switch S2 to be turned on, control the first switch S1 to be turned off, and control the load 9 to be disabled (disable), so as to enable the input voltage to charge the bus capacitor C1 through the pre-charging branch, determine whether a voltage difference between the input voltage and the voltage C1 of the bus capacitor is smaller than or equal to a preset voltage difference threshold in real time, control the first switch S1 to be turned on first when the voltage difference between the input voltage and the voltage C1 of the bus capacitor is smaller than or equal to the preset voltage difference threshold, and sequentially control the second switch S2 to be turned off and enable the load 9 after the first switch S1 is normally turned on.
The main difference between the second embodiment and the first embodiment is that the third switch S3 is eliminated, and the function realized by the third switch S3 is realized by the enable signal and the disable signal sent by the control device 3. For example, some of the loads 9 are IC chips, which can receive a disable signal to enter a disable state (the disable state also includes a sleep state), so as to eliminate or reduce the consumption current of the IC chip.
A method for suppressing a rush current by a rush current suppression circuit according to a second embodiment of the present invention includes the steps of:
step b1, the control device 3 controls the second switch S2 to be turned on and controls the first switch S1 to be turned off and the load 9 to be disabled, so that the input voltage charges the bus capacitor C1 through the pre-charging branch;
step b2, the control device 3 determines whether the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to a preset first voltage difference threshold, when the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to the preset first voltage difference threshold, the first switch S1 is first controlled to be turned on, and after the first switch S1 is normally turned on, the second switch S2 is sequentially controlled to be turned off to enable the load 9.
Further, when a first preset time elapses from the time when the second switch S2 is turned on and the first switch S1 is turned off and the load 9 is disabled, if it is determined that the voltage difference between the input voltage and the bus capacitor voltage is greater than the preset first voltage difference threshold, it indicates that a defect exists in the product or that the external condition does not meet the requirement, and the control device 3 controls the first switch S1 to be turned off and the load to be disabled, so as to protect the circuit. The first preset time may be selected to be 300 ms.
Further, the control device 3 determines in real time from when the first switch S1 is turned on whether the voltage difference between the input voltage and the voltage of the bus capacitor C1 is less than or equal to a preset second voltage difference threshold, and when the voltage difference between the input voltage and the voltage of the bus capacitor is less than or equal to the preset second voltage difference threshold, the control device 3 determines that the first switch S1 is normally turned on. When the first switch S1 is normally turned on, the voltage difference between the input voltage and the voltage of the bus capacitor C1 is close to 0V. The second voltage difference threshold is smaller than the first voltage difference threshold, and the second voltage difference threshold preset in this embodiment is selected to be 0.1V, and the threshold may also be adjusted according to the actual circuit. Alternatively, when a second preset time (for example, 100us) elapses from the time when the control device 3 controls the first switch S1 to be turned on, the control device 3 directly determines that the first switch S1 has been normally turned on.
As a modification of the second embodiment, it is also optional not to provide the first voltage detection circuit 11 and the second voltage detection circuit 12. Accordingly, when a first preset time (optionally 300ms in this embodiment) has elapsed since the control of the second switch S2 on and the control of the first switch S1 off and the disabling of the load 9 by the control device 3, the control device 3 directly determines that the voltage difference between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold, the control device first controls the first switch S1 on, and after the first switch S1 is normally on, sequentially controls the second switch S2 off and enables the load 9. When a second preset time (for example, 100us) elapses from the time when the control device 3 controls the first switch S1 to be turned on, the control device 3 determines that the first switch S1 has been normally turned on. The working principle of the invention is explained below with reference to a specific application example.
The input voltage (supply voltage) of the automobile chassis controller is 13.5V, the bus capacitance is 710uF, and 100Ohm resistance is used for pre-charging. The current supplied by the input power through the 100Ohm resistor already allows the sensor interface chip (i.e., load 9) on the bus to function properly. When the third switch S3 is not provided, the load current on the bus is 30mA during the precharge phase, and after the sensor interface chip enters the standby state by providing the third switch S3 and opening the third switch S3, the load current on the bus is reduced to less than 4 mA.
Fig. 5 is a simulated waveform diagram showing the bus capacitor voltage, the rush current when the first switch S1 is turned on, and the instantaneous power consumption when the first switch S1 is turned on in the precharge phase of the conventional vehicle chassis controller without the third switch S3. When the automobile chassis controller is not provided with the third switch S3, the voltage of the bus capacitor can only be pre-charged to 10V after the second switch S2 is conducted for 300ms, the voltage of the bus capacitor is charged to a final value of 13.5V in the conducting process of the first switch S1, the maximum impact current in the process is 21A, and the energy loss of the first switch S1 is 1.8 mJ.
Fig. 6 shows simulated waveform diagrams of bus capacitor voltage, rush current when the first switch S1 is turned on, and instantaneous power consumption when the first switch S1 is turned on of the vehicle chassis controller provided with the third switch S3 after improvement in the precharge stage. After the automobile chassis controller is provided with the third switch S3, the voltage of the bus capacitor can be pre-charged to 12.6V after the second switch S2 is conducted for 300ms, the voltage of the bus capacitor is charged to a final value of 13.5V in the conducting process of the first switch S1, the maximum impact current in the process is only 7A, and the loss energy of the first switch S1 is 0.1 mJ.
The impulse current suppression circuit provided by the embodiment of the invention can better control the charging current and time, most of energy loss in the charging process is concentrated in the resistor, and the pressure on the semiconductor switch is small, so that low-current low-power semiconductor switches with low cost can be selected as the first switch and the second switch, and the cost is reduced.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (14)
1. A rush current suppression circuit, comprising;
a first switch connected between the input voltage and the bus capacitor;
a pre-charge branch connected in parallel with the first switch, the pre-charge branch comprising a second switch and a resistor connected in series;
a third switch connected between the bus capacitor and a load, the load being connected in parallel with the bus capacitor;
the output end of the control device is respectively connected with the control end of the first switch, the control end of the second switch and the control end of the third switch; the control device is used for controlling the second switch to be connected and controlling the first switch and the third switch to be disconnected so as to enable the input voltage to charge the bus capacitor through the pre-charging branch, when the voltage difference value between the input voltage and the voltage of the bus capacitor is smaller than or equal to a preset first voltage difference threshold value, the first switch is firstly controlled to be connected, and after the first switch is normally connected, the second switch and the third switch are sequentially controlled to be disconnected.
2. The inrush current suppression circuit of claim 1, wherein: the control device is used for judging that the voltage difference value between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold value after first preset time from the time of controlling the second switch to be switched on and controlling the first switch and the third switch to be switched off.
3. The inrush current suppression circuit of claim 1, further comprising:
the first voltage detection circuit is used for detecting the magnitude of the input voltage;
the second voltage detection circuit is used for detecting the voltage of the bus capacitor;
the input end of the control device is respectively connected with the output end of the first voltage detection circuit and the output end of the second voltage detection circuit; the control device is used for judging whether the voltage difference value between the input voltage and the bus capacitor voltage is smaller than or equal to a preset first voltage difference threshold value or not in real time.
4. The inrush current suppression circuit of claim 3, wherein the control means is configured to control the first switch and the third switch to be turned off when a first predetermined time elapses since the second switch is controlled to be turned on and the first switch and the third switch are controlled to be turned off, if the voltage difference between the input voltage and the bus capacitor voltage is greater than a predetermined first voltage difference threshold.
5. The inrush current suppression circuit of claim 3, wherein the control means is configured to determine in real time from when the first switch is controlled to be turned on whether a voltage difference between the input voltage and the voltage of the bus capacitor is less than or equal to a preset second voltage difference threshold, and determine that the first switch has been turned on normally when the voltage difference between the input voltage and the voltage of the bus capacitor is less than or equal to the preset second voltage difference threshold, where the second voltage difference threshold is less than the first voltage difference threshold.
6. The inrush current suppression circuit according to claim 2 or 3, wherein the control means is configured to determine that the first switch has been normally turned on when a second preset time elapses from when the first switch is controlled to be turned on.
7. A method of suppressing a rush current by a rush current suppression circuit as claimed in claim 1, including the steps of:
the control device controls the second switch to be connected and controls the first switch and the third switch to be disconnected, so that the input voltage charges the bus capacitor through the pre-charging branch circuit;
the control device judges whether a voltage difference value between the input voltage and the bus capacitor voltage is smaller than or equal to a preset first voltage difference threshold value or not, when the voltage difference value between the input voltage and the bus capacitor voltage is smaller than or equal to the preset first voltage difference threshold value, the first switch is controlled to be switched on, and after the first switch is normally switched on, the second switch is controlled to be switched off and the third switch is controlled to be switched on in sequence.
8. A rush current suppression circuit, comprising:
a first switch connected between an input voltage and a bus capacitor, the bus capacitor being connected in parallel with a load;
a pre-charge branch connected in parallel with the first switch, the pre-charge branch comprising a second switch and a resistor connected in series;
the output end of the control device is respectively connected with the control end of the first switch, the control end of the second switch and the enabling end of the load; the control device is used for controlling the second switch to be switched on and controlling the first switch to be switched off and the load to be disabled so as to enable the input voltage to charge the bus capacitor through the pre-charging branch, when the voltage difference value between the input voltage and the voltage of the bus capacitor is smaller than or equal to a preset first voltage difference threshold value, the first switch is controlled to be switched on first, and after the first switch is normally switched on, the second switch is sequentially controlled to be switched off and enabled to enable the load.
9. The inrush current suppression circuit of claim 8, wherein: the control device is used for judging that the voltage difference value between the input voltage and the bus capacitor voltage is less than or equal to a preset first voltage difference threshold value after a first preset time from the time of controlling the second switch to be switched on and controlling the first switch to be switched off and the load to be disabled.
10. The inrush current suppression circuit of claim 8, further comprising:
the first voltage detection circuit is used for detecting the magnitude of the input voltage;
the second voltage detection circuit is used for detecting the voltage of the bus capacitor;
the input end of the control device is respectively connected with the output end of the first voltage detection circuit and the output end of the second voltage detection circuit; the control device is used for judging whether the voltage difference value between the input voltage and the bus capacitor voltage is smaller than or equal to a preset first voltage difference threshold value or not in real time.
11. The inrush current suppression circuit of claim 10, wherein the control device is configured to control the first switch to turn off and disable the load if a voltage difference between the input voltage and the bus capacitor voltage is greater than a preset first voltage difference threshold after a first preset time elapses from when the second switch is controlled to turn on and the first switch is controlled to turn off and disable the load.
12. The inrush current suppression circuit of claim 10, wherein the control means is configured to determine in real time from when the first switch is controlled to be turned on whether a voltage difference between the input voltage and the voltage of the bus capacitor is less than or equal to a preset second voltage difference threshold, and determine that the first switch has been turned on normally when the voltage difference between the input voltage and the voltage of the bus capacitor is less than or equal to the preset second voltage difference threshold, and the second voltage difference threshold is less than the first voltage difference threshold.
13. The inrush current suppression circuit according to claim 9 or 10, wherein the control means is configured to determine that the first switch has been normally turned on when a second preset time elapses from when the first switch is controlled to be turned on.
14. The method of suppressing a rush current by a rush current suppression circuit as claimed in claim 8, including the steps of:
the control device controls the second switch to be switched on and controls the first switch to be switched off and the load to be disabled, so that the input voltage charges the bus capacitor through the pre-charging branch circuit;
the control device judges whether a voltage difference value between the input voltage and the bus capacitor voltage is smaller than or equal to a preset first voltage difference threshold value or not, when the voltage difference value between the input voltage and the bus capacitor voltage is smaller than or equal to the preset first voltage difference threshold value, the first switch is controlled to be switched on, and after the first switch is normally switched on, the second switch is sequentially controlled to be switched off and enable the load.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911067602.8A CN110677145A (en) | 2019-11-04 | 2019-11-04 | Impulse current suppression circuit and method for suppressing impulse current thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911067602.8A CN110677145A (en) | 2019-11-04 | 2019-11-04 | Impulse current suppression circuit and method for suppressing impulse current thereof |
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