CN115938860B - Step-down holding circuit of relay - Google Patents
Step-down holding circuit of relay Download PDFInfo
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- CN115938860B CN115938860B CN202211723626.6A CN202211723626A CN115938860B CN 115938860 B CN115938860 B CN 115938860B CN 202211723626 A CN202211723626 A CN 202211723626A CN 115938860 B CN115938860 B CN 115938860B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The application discloses a relay voltage-reducing and maintaining circuit, and belongs to the technical field of electric control. Wherein, the relay step-down holding circuit includes: a relay; the step-down holding circuit is connected with the relay; the control signal input end is connected with the step-down holding circuit and is used for inputting a control signal to the step-down holding circuit, and the step-down holding circuit is used for adjusting the coil voltage of the relay according to the state of the control signal so as to control the action, the step-down holding and the reset of the relay; the first voltage input end is connected with the step-down holding circuit and is used for supplying power to the step-down holding circuit; and the second voltage input end is connected with the relay and is used for supplying power to the relay.
Description
Technical Field
The application belongs to the technical field of electrical control, and particularly relates to a relay voltage-reducing holding circuit.
Background
The electromagnetic relay is used as a basic electronic device, has the advantages of simple structure, low price, good strong and weak electric isolation effect and the like, and is widely applied to the field of electric control. Normally, when the relay acts, a larger current needs to be provided for the relay coil so as to ensure the reliability and the action speed of the relay; and when the relay operation is finished and is in the holding state, the coil current required for maintaining the relay in the holding state is relatively small. Therefore, measures are required to reduce the holding current in the holding state of the relay and prevent the loss of the relay control coil from becoming too high.
The existing scheme for reducing the maintaining current in the maintaining state of the relay needs multiple signals or pulse width modulation signals to control, and the control process is complex.
Disclosure of Invention
The embodiment of the application aims to provide a relay voltage reduction maintaining circuit which can solve the problem that the control process is complex in the existing scheme for reducing the maintaining current in the maintaining state of a relay.
The application provides a relay step-down holding circuit, which comprises:
a relay;
the step-down holding circuit is connected with the relay;
the control signal input end is connected with the step-down holding circuit and is used for inputting a control signal to the step-down holding circuit, and the step-down holding circuit is used for adjusting the coil voltage of the relay according to the state of the control signal so as to control the action, the step-down holding and the reset of the relay;
the first voltage input end is connected with the step-down holding circuit and is used for supplying power to the step-down holding circuit;
and the second voltage input end is connected with the relay and is used for supplying power to the relay.
Optionally, the step-down holding circuit includes a first logic circuit, a second logic circuit, and a switching circuit connected to the relay;
the switching circuit comprises a first switching circuit, a second switching circuit and a voltage dividing resistor, wherein the second switching circuit is connected with the voltage dividing resistor in series and then connected with the first switching circuit in parallel;
the second logic circuit is used for outputting a second signal to the first logic circuit and the second switch circuit based on the control signal input by the control signal input end;
the first logic circuit is used for outputting a first signal to the first switch circuit based on the control signal input by the control signal input end and the second signal input by the second logic circuit;
the first signal is used for controlling the first switch circuit to be disconnected or connected;
the second signal is used for controlling the second switch circuit to be disconnected or connected.
Optionally, the first logic circuit includes a first and gate circuit, a not gate circuit, and a first delay circuit, and the first and gate circuit includes two first input ends;
the input end of the first delay circuit is connected with the output end of the second logic circuit, the output end of the first delay circuit is connected with the input end of the NOT gate circuit, the output end of the NOT gate circuit is connected with one first input end, the other first input end is connected with the control signal input end, and the output end of the first AND gate circuit is connected with the first switch circuit.
Optionally, the second logic circuit includes a second and gate circuit and a second delay circuit, where the second and gate circuit includes two second input ends, one of the second input ends is connected to the control signal input end, the output end of the second delay circuit is connected to the other second input end, the input end of the second delay circuit is connected to the control signal input end, and the output end of the second and gate circuit is connected to the first delay circuit and the second switch circuit.
Optionally, the first delay circuit includes a first rising circuit, a first comparator and a first voltage dividing circuit, an input end of the first rising circuit is connected with an output end of the second and gate circuit, an output end of the first rising circuit is connected with a non-inverting input end of the first comparator, and the first rising circuit includes a first resistor and a capacitor connected in series; the input end of the first voltage dividing circuit is connected with the first voltage input end, the output end of the first voltage dividing circuit is connected with the inverting input end of the first comparator, and the output end of the first comparator is connected with the NOT circuit.
Optionally, the first delay circuit further includes a first falling circuit, the first falling circuit is connected in parallel with the first resistor, the first falling circuit includes a fourth resistor and a first diode, and a forward direction of the first diode is consistent with a direction that a non-inverting input end of the first comparator flows to an output end of the second and gate circuit.
Optionally, the second delay circuit includes a second rising circuit, a second comparator, a second voltage dividing circuit and a second falling circuit, an input end of the second rising circuit is connected with the control signal input end, an output end of the second rising circuit is connected with a non-inverting input end of the second comparator, and the second rising circuit includes a fifth resistor and a second capacitor connected in series; the input end of the second voltage dividing circuit is connected with the first voltage input end, the output end of the second voltage dividing circuit is connected with the inverting input end of the second comparator, and the output end of the second comparator is connected with the input end of the second AND gate circuit; the second falling circuit is connected with the second rising circuit in parallel, the second falling circuit comprises a sixth resistor and a second diode, and the forward direction of the second diode is consistent with the direction of the non-inverting input end of the second comparator flowing to the control signal input end.
Optionally, the buck holding circuit further includes a third diode connected in parallel with the relay, and a forward direction of the second diode is consistent with a direction of the switching circuit flowing to the second voltage input terminal.
Optionally, the first switching circuit and the second switching circuit each include a switching device, and the switching devices are fully-controlled semiconductor switching devices.
Optionally, the first switching circuit and the second switching circuit each include a switching device, and the switching device is a mechanical switching device.
In the embodiment of the application, after the control signals are input into the voltage-reducing holding circuit, the voltage-reducing holding circuit controls the action, voltage-reducing holding and resetting of the relay, the voltage-reducing holding of the relay can be realized only by one path of control signals without the cooperation of multiple paths of control signals, and the control process is simpler.
Drawings
Fig. 1 is one of schematic structural diagrams of a relay step-down holding circuit provided in the present embodiment;
fig. 2 is a second schematic diagram of the configuration of the step-down holding circuit of the relay according to the present embodiment;
fig. 3 is a schematic diagram of a first delay circuit in the step-down holding circuit of the relay according to the present embodiment;
FIG. 4 is a signal timing diagram of the first delay circuit;
fig. 5 is a schematic diagram of a signal timing diagram of a relay buck hold circuit.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.
The embodiment of the application provides a relay voltage-reducing and maintaining circuit. As shown in fig. 1, the relay step-down holding circuit includes: and a relay. And the step-down holding circuit is connected with the relay. The control signal input end is connected with the step-down holding circuit and used for inputting a control signal to the step-down holding circuit, and the step-down holding circuit is used for adjusting the coil voltage of the relay according to the state of the control signal so as to control the action, the step-down holding and the reset of the relay. And the first voltage input end is connected with the step-down holding circuit and is used for supplying power to the step-down holding circuit. And the second voltage input end is connected with the relay and is used for supplying power to the relay.
The relay step-down holding circuit shown in fig. 1 can be applied to an overall system or product. The control signal input terminal inputs a control signal S1 to the buck holding circuit, the control signal S1 being generated by the remaining circuits of the overall system or product. The first voltage VCC input by the first voltage input end is the power supply voltage of the step-down holding circuit and the system or product integrated circuit, and the second voltage input by the second voltage input endU supply The power supply voltage of the relay. Both the first voltage and the second voltage are generated by a power circuit of the product or system. After the control signal is input to the step-down holding circuit, the step-down holding circuit controls the action, step-down holding and resetting of the relay. When the control signal is at a high level, the relay enters an action state first and enters a step-down holding state after a certain time, and when the control signal is at a low level, the relay enters a reset state. Therefore, the relay voltage reduction and holding circuit provided by the embodiment can realize voltage reduction and holding of the relay only by one path of control signals without matching of multiple paths of control signals, and the control process is simpler. In addition, the method does not need to rely on a microprocessor, and can be applied to products using the microprocessor or products not using the microprocessor.
Optionally, the step-down holding circuit includes a first logic circuit, a second logic circuit, and a switching circuit connected to the relay. The switching circuit comprises a first switching circuit, a second switching circuit and a voltage dividing resistor, wherein the second switching circuit is connected with the voltage dividing resistor in series and then connected with the first switching circuit in parallel. The second logic circuit is used for outputting a second signal to the first logic circuit and the second switch circuit based on the control signal input by the control signal input end. The first logic circuit is configured to output a first signal to the first switch circuit based on a control signal input from the control signal input terminal and a second signal input from the second logic circuit. The first signal is used for controlling the first switch circuit to be disconnected or connected. The second signal is used for controlling the second switch circuit to be disconnected or connected.
The first switch circuit is turned on when the first signal is at a high level, and turned off when the first signal is at a low level. The second switching circuit is turned on when the second signal is at a high level, and turned off when the second signal is at a low level. When the first switch circuit is turned on and the second switch circuit is turned off, the relay is in an action state, and the coil voltage of the relay is the second voltage U supply . The first switch circuit and the second switch circuit are both conductedThe relay is in an action state. When the first switching circuit is turned off and the second switching circuit is turned on, the relay coil voltage is lowered due to the presence of the voltage dividing resistor R1 shown in fig. 2, and the relay is in a step-down holding state. When the first switch circuit is opened and the second switch circuit is opened, the relay is in a reset state.
The control signal S6 input by the second logic circuit to the second switch circuit is determined by the control signal S1 at the control signal input end, and the control signal S5 input by the first logic circuit to the first switch circuit is determined by the control signal S1 and the control signal S6 together, so that in the relay voltage reduction maintaining circuit provided by the embodiment of the application, the action, voltage reduction maintaining and resetting of the relay can be completed only by inputting one control signal S1, and the control is simple.
The voltage dividing resistor R1 may be a resistor with a fixed resistance value or a negative temperature coefficient thermistor, and if R1 is a negative temperature coefficient thermistor, it is necessary to ensure that the temperature coefficient of R1 is complementary with the temperature coefficient of the relay coil as much as possible, so as to realize that the current of the relay in the state of maintaining the voltage reduction of the relay is unchanged when the ambient temperature changes, and ensure the reliability of the maintaining state of the relay. R1 is a value of R of the relay coil resistance K Holding voltage U hold Correlation:
U hold ＝[R K /(R1+R K )]U supply
wherein R is K R1 represents the resistance of the voltage dividing resistor, U supply Representing a second voltage, U hold Representing the holding voltage. The value of R1 can be determined according to the coil resistance value, the holding voltage and the second voltage of the relay.
Optionally, the first logic circuit includes a first and circuit, a not circuit, and a first delay circuit, and the first and circuit includes two first input terminals. The input end of the first delay circuit is connected with the output end of the second logic circuit, the output end of the first delay circuit is connected with the input end of the NOT gate circuit, the output end of the NOT gate circuit is connected with one first input end, the other first input end is connected with the control signal input end, and the output end of the first AND gate circuit is connected with the first switch circuit.
Referring further to fig. 2, the first delay circuit is configured to cause the signal to change after a delay period. It will be appreciated that when the control signal S6 changes from low to high, the control signal S2 input to the not gate by the first delay circuit will remain low and then change from low to high after a delay period. The not gate is used to change the level of the signal, and assuming that the control signal S2 is at a high level, the control signal S3 output from the not gate is at a low level. When the two first input ends of the first and gate circuit are both at the high level, the control signal S5 output by the first and gate circuit is at the high level, and the control signal S5 output by the first and gate circuit is at the low level in the rest cases.
When the control signal S1 input by the control signal input terminal is at a high level, and the control signal S6 output by the second logic circuit is changed from a low level to a high level, the second switch circuit is in a conductive state, the control signal S2 is still at a low level in the first stage due to the existence of the first delay circuit, the control signal S3 is at a high level, and the first signal output by the first and gate circuit is at a high level, the first switch circuit and the second switch circuit are both in a conductive state, and the relay is in an action state due to the control signal S1 and the control signal S3 being both at a high level. In the second stage, i.e. after a period of delay, the control signal S2 becomes high level, the control signal S3 becomes low level, the first signal S5 output by the first and gate circuit is low level, the first switch circuit is turned off, the second switch circuit is turned on, the relay coil voltage is reduced, and the relay is in a step-down holding state. In the process that the relay is changed from the action state to the voltage reduction maintaining state, a new control signal is not required to be input, and the control is simple.
Optionally, the second logic circuit includes a second and gate circuit and a second delay circuit, where the second and gate circuit includes two second input ends, one of the second input ends is connected to the control signal input end, the output end of the second delay circuit is connected to the other second input end, the input end of the second delay circuit is connected to the control signal input end, and the output end of the second and gate circuit is connected to the first delay circuit and the second switch circuit.
The initial state of the relay is the off state, the control signal S1 is low level, the second signal S6 is low level, the first signal S5 is low level, and the first switch circuit and the second switch circuit are both off. The relay needs to act and automatically enters a voltage reduction maintaining state, the control signal S1 becomes high level, the second signal S6 output by the second AND gate circuit is still low level, the control signal S2 is low level, the control signal S3 is high level, the first signal S6 output by the first AND gate circuit is high level, the first switch circuit is turned on, the second switch circuit is turned off, and the relay enters an action state in the first stage. In the second stage, the signal S4 output by the second delay circuit is changed from low level to high level, so that the second signal S6 output by the second and gate circuit is changed to high level, the control signal S2 is still low level, the control signal S3 is high level, the first signal is high level, the first switch circuit and the second switch circuit are both turned on, and the relay is in an action state. In the third stage, the control signal S2 output by the first delay circuit becomes high level, the control signal S3 becomes low level, the first i is good to become low level in the new year, the first switch circuit is turned off, the second switch circuit is turned on, and the relay automatically enters a step-down holding state. Through the cooperation of the first logic circuit and the second logic circuit, the relay can automatically enter the voltage-reducing maintaining state from the action state only by one path of control signal, and the control is simple.
Optionally, the first delay circuit includes a first rising circuit, a first comparator and a first voltage dividing circuit, an input end of the first rising circuit is connected with an output end of the second and gate circuit, an output end of the first rising circuit is connected with a non-inverting input end of the first comparator, and the first rising circuit includes a first resistor and a capacitor connected in series; the input end of the first voltage dividing circuit is connected with the first voltage input end, the output end of the first voltage dividing circuit is connected with the inverting input end of the first comparator, and the output end of the first comparator is connected with the NOT circuit.
As shown in fig. 3, the first voltage dividing circuit includes a second resistor R1 and a third resistor R2. The first resistance is R3. When the voltage at the non-inverting input terminal of the first comparator is greater than the voltage at the inverting input terminal, the signal S output by the first comparator O And is high, otherwise outputs low. Due to the arrangement of the capacitor, the voltage S input to the first rising circuit IN When the low level state is changed into the high level state, the voltage on the first rising circuit does not change instantaneously, but changes slowly in a curve. The voltage on the inverting input end of the first comparator does not change, and when the voltage on the first rising circuit, namely the voltage on the non-inverting input end, slowly increases until the voltage is larger than the inverting input end, the first comparator outputs a high level so as to achieve a delay effect. When the voltage on the first rising circuit changes from a low level to a high level state, the first delay time:
t rise ＝-R3×C1×ln(R1/(R1+R2))
wherein, R3 structure represents the resistance of the first resistor, R1 represents the resistance of the second resistor, R2 represents the resistance of the third resistor, and C1 represents the capacitance of the capacitor.
The first delay circuit has simple structure and stable control.
Optionally, the first delay circuit further includes a first falling circuit, the first falling circuit is connected in parallel with the first resistor, the first falling circuit includes a fourth resistor and a first diode, and a forward direction of the first diode is consistent with a direction that a non-inverting input end of the first comparator flows to an output end of the second and gate circuit.
Referring to fig. 3 and 4 in combination, the fourth resistor is R4. When the voltage S is input into the first delay circuit IN When the voltage is changed from high level to low level, the second delay time is passed, the output voltage S O The change will occur. Second delay time:
t fail ＝-R4×C1×ln(R2/(R1+R2))
wherein, R4 represents the resistance value of the fourth resistor, R1 represents the resistance value of the second resistor, R2 represents the resistance value of the third resistor, and C1 represents the capacitance value of the capacitor.
It should be noted that, in order to ensure that the second delay time is short, the fourth resistor R4 is much smaller than the first resistor R3. The first delay circuit can enable the level to change again after a period of delay time when the level changes from low to high, and can change in shorter time when the level changes from high to low, so that the working requirement of the relay can be met more quickly.
As shown in fig. 5, when the control signal S1 input from the control signal input terminal changes from low level to high level, the control signal S2 output from the first delay circuit needs to pass through the first delay time of the second delay circuit and the first delay time of the first delay circuit, and then S2 will change to high level. The level of the control signal S3 of the and circuit is opposite to S2. The control signal S4 of the second delay circuit changes from low level to high level after the corresponding first delay time. The first signal S5 is determined by S1 and S3. The second signal S6 is determined by S1 and S4. The voltage of the relay coil is determined by the first signal S5 and the second signal S6. When the control signal S1 changes from high level to low level, the principle is the same, and the description is omitted here.
Optionally, the second delay circuit includes a second rising circuit, a second comparator, a second voltage dividing circuit and a second falling circuit, an input end of the second rising circuit is connected with the control signal input end, an output end of the second rising circuit is connected with a non-inverting input end of the second comparator, and the second rising circuit includes a fifth resistor and a second capacitor connected in series; the input end of the second voltage dividing circuit is connected with the first voltage input end, the output end of the second voltage dividing circuit is connected with the inverting input end of the second comparator, and the output end of the second comparator is connected with the input end of the second AND gate circuit; the second falling circuit is connected with the second rising circuit in parallel, the second falling circuit comprises a sixth resistor and a second diode, and the forward direction of the second diode is consistent with the direction of the non-inverting input end of the second comparator flowing to the control signal input end.
It can be understood that, except for the difference between the input end and the output end, the second delay circuit has the same structure as the first delay circuit, and can achieve the same effect, and the details are not repeated here.
Optionally, the buck holding circuit further includes a third diode connected in parallel with the relay, and a forward direction of the second diode is consistent with a direction of the switching circuit flowing to the second voltage input terminal.
A third diode D1, shown in fig. 2, is used to provide a freewheeling path for the current of the relay during the reset of the relay, avoiding voltage spikes due to the inductance of the relay coil.
Optionally, the first switching circuit and the second switching circuit each include a switching device, and the switching devices are fully-controlled semiconductor switching devices. The fully-controlled semiconductor switching device has high switching speed, small switching loss, large safe working area and pulse current impact resistance.
Optionally, the first switching circuit and the second switching circuit each include a switching device, and the switching device is a mechanical switching device. The mechanical structure switch device has simple and reliable action and less links.
The foregoing is merely illustrative embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present application, and the application should be covered. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (9)
1. A relay step-down holding circuit, characterized by comprising:
a relay;
the step-down holding circuit is connected with the relay;
the control signal input end is connected with the step-down holding circuit and is used for inputting a control signal to the step-down holding circuit, and the step-down holding circuit is used for adjusting the coil voltage of the relay according to the state of the control signal so as to control the action, the step-down holding and the reset of the relay;
the first voltage input end is connected with the step-down holding circuit and is used for supplying power to the step-down holding circuit;
the second voltage input end is connected with the relay and is used for supplying power to the relay;
the step-down holding circuit comprises a first logic circuit, a second logic circuit and a switch circuit connected with the relay;
the switching circuit comprises a first switching circuit, a second switching circuit and a voltage dividing resistor, wherein the second switching circuit is connected with the voltage dividing resistor in series and then connected with the first switching circuit in parallel;
the second logic circuit is used for outputting a second signal to the first logic circuit and the second switch circuit based on the control signal input by the control signal input end;
the first logic circuit is used for outputting a first signal to the first switch circuit based on the control signal input by the control signal input end and the second signal input by the second logic circuit;
the first signal is used for controlling the first switch circuit to be disconnected or connected;
the second signal is used for controlling the second switch circuit to be disconnected or connected.
2. The relay buck-boost-holding circuit of claim 1, wherein the first logic circuit includes a first and circuit, a not circuit, and a first delay circuit, the first and circuit including two first inputs;
the input end of the first delay circuit is connected with the output end of the second logic circuit, the output end of the first delay circuit is connected with the input end of the NOT gate circuit, the output end of the NOT gate circuit is connected with one first input end, the other first input end is connected with the control signal input end, and the output end of the first AND gate circuit is connected with the first switch circuit.
3. The relay buck holding circuit according to claim 2, wherein the second logic circuit includes a second and gate circuit and a second delay circuit, the second and gate circuit includes two second input terminals, one of the second input terminals is connected to the control signal input terminal, the output terminal of the second delay circuit is connected to the other of the second input terminals, the input terminal of the second delay circuit is connected to the control signal input terminal, and the output terminal of the second and gate circuit is connected to the first delay circuit and the second switch circuit.
4. The relay buck-boost-holding circuit of claim 3, wherein the first delay circuit includes a first boost circuit, a first comparator, and a first voltage divider circuit, an input of the first boost circuit is connected to an output of the second and gate circuit, an output of the first boost circuit is connected to a non-inverting input of the first comparator, and the first boost circuit includes a first resistor and a capacitor in series; the input end of the first voltage dividing circuit is connected with the first voltage input end, the output end of the first voltage dividing circuit is connected with the inverting input end of the first comparator, and the output end of the first comparator is connected with the NOT circuit.
5. The relay buck holding circuit according to claim 4, wherein the first delay circuit further includes a first buck circuit connected in parallel with the first resistor, the first buck circuit including a fourth resistor and a first diode, a forward direction of the first diode being coincident with a direction of flow of the non-inverting input of the first comparator to the output of the second and circuit.
6. The relay buck-boost-holding circuit according to claim 5, wherein the second delay circuit includes a second boost circuit, a second comparator, a second voltage divider circuit, and a second buck circuit, an input terminal of the second boost circuit is connected to the control signal input terminal, an output terminal of the second boost circuit is connected to a non-inverting input terminal of the second comparator, and the second boost circuit includes a fifth resistor and a second capacitor connected in series; the input end of the second voltage dividing circuit is connected with the first voltage input end, the output end of the second voltage dividing circuit is connected with the inverting input end of the second comparator, and the output end of the second comparator is connected with the input end of the second AND gate circuit; the second falling circuit is connected with the second rising circuit in parallel, the second falling circuit comprises a sixth resistor and a second diode, and the forward direction of the second diode is consistent with the direction of the non-inverting input end of the second comparator flowing to the control signal input end.
7. The relay step-down holding circuit according to any one of claims 1 to 6, further comprising a third diode connected in parallel with the relay, a forward direction of the second diode being coincident with a direction in which the switching circuit flows toward the second voltage input terminal.
8. The relay step-down holding circuit according to any one of claims 1 to 6, wherein the first switching circuit and the second switching circuit each include a switching device, the switching device being a fully-controlled semiconductor switching device.
9. The relay step-down holding circuit according to any one of claims 1 to 6, wherein the first switching circuit and the second switching circuit each include a switching device, the switching device being a mechanical structure switching device.
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| CN202211723626.6A CN115938860B (en) | 2022-12-30 | 2022-12-30 | Step-down holding circuit of relay |
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| CN202211723626.6A CN115938860B (en) | 2022-12-30 | 2022-12-30 | Step-down holding circuit of relay |
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| CN115938860A CN115938860A (en) | 2023-04-07 |
| CN115938860B true CN115938860B (en) | 2023-09-26 |
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| CN206210705U (en) * | 2016-11-14 | 2017-05-31 | 比亚迪股份有限公司 | The drive device of relay and the vehicle with it |
| CN107591281A (en) * | 2017-09-04 | 2018-01-16 | 珠海格力电器股份有限公司 | Relay decompression keeps control circuit and control method |
| CN207199530U (en) * | 2017-09-04 | 2018-04-06 | 珠海格力电器股份有限公司 | Relay decompression keeps control circuit |
| CN209232673U (en) * | 2019-02-28 | 2019-08-09 | 杭州萤石软件有限公司 | A kind of control relay circuit |
| CN216597422U (en) * | 2021-11-12 | 2022-05-24 | 阳光电源股份有限公司 | Relay control circuit and power converter |
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| CN115938860A (en) | 2023-04-07 |
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